TMS320C64X

The TMS320C6748 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI's Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardwarebased 'root-of-trust," the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects customers' IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI's Basic Secure Boot, see the TMS320C674x/OMAP-L1x Processor Security User's Guide .

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I 2 C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced highresolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

• Machine Vision (Low-End)

The Serial ATA (SATA) controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows ® debugger interface for visibility into source code execution.

1

• 375- and 456-MHz C674x Fixed- and FloatingPoint VLIW DSP
• C674x Instruction Set Features
• -Superset of the C67x+ and C64x+ ISAs
• -Up to 3648 MIPS and 2746 MFLOPS
• -Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
• -8-Bit Overflow Protection
• -Bit-Field Extract, Set, Clear
• -Normalization, Saturation, Bit-Counting
• -Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
• -32KB of L1P Program RAM/Cache
• -32KB of L1D Data RAM/Cache
• -256KB of L2 Unified Mapped RAM/Cache
• -Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
• -2 Channel Controllers
• -3 Transfer Controllers
• -64 Independent DMA Channels
• -16 Quick DMA Channels
• -Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
• -Load-Store Architecture With Nonaligned Support
• -64 General-Purpose Registers (32-Bit)
• -Six ALU (32- and 40-Bit) Functional Units
• -Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
• -Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
• -Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
• -Two Multiply Functional Units:
• -Mixed-Precision IEEE Floating-Point Multiply Supported up to:
• -2 SP × SP → SP Per Clock
• -2 SP × SP → DP Every Two Clocks

1

• One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem (PRUSS)
• -Two Independent Programmable Real-Time Unit (PRU) Cores
• -32-Bit Load-Store RISC Architecture
• -4KB of Instruction RAM Per Core
• -512 Bytes of Data RAM Per Core
• -PRUSS can be Disabled Through Software to Save Power
• -Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
• -Standard Power-Management Mechanism
• -Clock Gating
• -Entire Subsystem Under a Single PSC Clock Gating Domain
• -Dedicated Interrupt Controller
• -Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) With Integrated PHY (USB1)
• USB 2.0 OTG Port With Integrated PHY (USB0)
• -USB 2.0 High- and Full-Speed Client
• -USB 2.0 High-, Full-, and Low-Speed Host
• -End Point 0 (Control)
• -End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):
• -Two Clock Zones and 16 Serial Data Pins
• -Supports TDM, I2S, and Similar Formats
• -DIT-Capable
• -FIFO Buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports (McBSPs):
• -Supports TDM, I2S, and Similar Formats
• -AC97 Audio Codec Interface
• -Telecom Interfaces (ST-Bus, H100)
• -128-Channel TDM
• -FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
• -IEEE 802.3 Compliant
• -MII Media-Independent Interface
• -RMII Reduced Media-Independent Interface
• -Management Data I/O (MDIO) Module
• Video Port Interface (VPIF):
• -Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
• -Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
• Universal Parallel Port (uPP):
• -High-Speed Parallel Interface to FPGAs and Data Converters
• -Data Width on Both Channels is 8- to 16-Bit Inclusive
• -Single-Data Rate or Dual-Data Rate Transfers
• -Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
• Serial ATA (SATA) Controller:
• -Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)
• -Supports All SATA Power-Management Features
• -Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
• -Supports Port Multiplier and Command-Based Switching
• Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
• -Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
• -6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
• -Dead-Band Generation
• -PWM Chopping by High-Frequency Carrier
• -Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
• -Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
• -Single-Shot Capture of up to Four Event Timestamps
• Packages:
• -361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
• -361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
• Commercial, Extended, or Industrial Temperature

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

The following table shows the thermal resistance characteristics for the PBGA-ZCE mechanical package.

Table 8-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]