TMS320C6000

Part: TMS320C6748 — Texas Instruments

Type: Fixed- and Floating-Point DSP (C674x VLIW core)

Description: Low-power 375/456 MHz C674x fixed- and floating-point VLIW DSP delivering up to 3648 MIPS and 2746 MFLOPS, with 256 KB L2, 128 KB shared RAM, DDR2/mDDR controller, SATA, USB, EMAC and 361-ball BGA packaging.

Operating Conditions:

• Core supply (CVDD): 1.25–1.35 V at the 1.3 V operating point; 1.14–1.32 V at 1.2 V; 1.05–1.16 V at 1.1 V; 0.95–1.05 V at 1.0 V
• I/O supply (dual-voltage DVDD3318_x): 3.15–3.45 V (3.3 V) or 1.71–1.89 V (1.8 V)
• Operating junction temperature: 0 to 90 °C (commercial default); -40 to 90 °C (D suffix, industrial); -40 to 105 °C (A suffix, extended)
• Maximum CPU clock: 375 or 456 MHz, depending on version

Absolute Maximum Ratings:

• Core logic supplies (CVDD, RVDD, RTC_CVDD, PLLx_VDDA, SATA_VDD, USB_CVDD): -0.5 to 1.4 V
• 1.8 V I/O supplies: -0.5 to 2 V
• 3.3 V I/O supplies: -0.5 to 3.8 V
• Dual-voltage LVCMOS input/output voltage (steady state): -0.3 V to DVDD + 0.3 V
• USB 5 V tolerant I/Os: 5.25 V; USB0 VBUS pin: 5.50 V
• I/O clamp current: ±20 mA
• Operating junction temperature: 90 °C (commercial/industrial) or 105 °C (extended)

Key Specs:

• CPU: C674x DSP at 375 or 456 MHz, up to 3648 MIPS / 2746 MFLOPS
• On-chip memory: 32 KB L1P, 32 KB L1D, 256 KB L2, plus 128 KB shared RAM
• External memory: EMIFA (NOR, NAND, 16-bit SDRAM) and 16-bit DDR2 (up to 156 MHz) or mDDR (up to 150 MHz)
• RVDD (internal RAM supply): 1.25–1.35 V for 456 MHz versions; 1.14–1.32 V for 375 MHz versions
• RTC_CVDD: 0.9–1.32 V
• USB PHY supplies: 1.71–1.89 V and 3.15–3.45 V
• Networking and storage: 10/100 Mbps EMAC (MII/RMII), SATA I/II (1.5/3.0 Gbps)
• EDMA3: 64 independent channels and 16 QDMA channels

Features:

• C674x DSP supporting 32-bit integer and IEEE single- and double-precision floating point
• Two-level cache architecture
• Two PRU cores (PRUSS) with 4 KB instruction RAM each
• USB 2.0 OTG (USB0) and USB 1.1 OHCI host (USB1) with integrated PHYs
• McASP (16 serializers), 2 McBSPs, 3 UARTs, 2 SPIs, 2 I2C, 2 MMC/SD, HPI, uPP, VPIF, LCD controller
• 2 eHRPWM and 3 eCAP modules
• RTC with separate power rail
• Basic Secure Boot (SHA-1/SHA-256, AES-128) on security-enabled devices
• 1.8 V or 3.3 V LVCMOS I/Os (except USB and DDR2)

Applications:

• Currency inspection
• Biometric identification
• Machine vision (low-end)

Package:

• 361-ball PBGA (NFBGA), ZCE suffix, 13 mm × 13 mm, 0.65 mm ball pitch
• 361-ball PBGA (NFBGA), ZWT suffix, 16 mm × 16 mm, 0.80 mm ball pitch

1

• 375- and 456-MHz C674x Fixed- and FloatingPoint VLIW DSP
• C674x Instruction Set Features
• -Superset of the C67x+ and C64x+ ISAs
• -Up to 3648 MIPS and 2746 MFLOPS
• -Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
• -8-Bit Overflow Protection
• -Bit-Field Extract, Set, Clear
• -Normalization, Saturation, Bit-Counting
• -Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
• -32KB of L1P Program RAM/Cache
• -32KB of L1D Data RAM/Cache
• -256KB of L2 Unified Mapped RAM/Cache
• -Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
• -2 Channel Controllers
• -3 Transfer Controllers
• -64 Independent DMA Channels
• -16 Quick DMA Channels
• -Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
• -Load-Store Architecture With Nonaligned Support
• -64 General-Purpose Registers (32-Bit)
• -Six ALU (32- and 40-Bit) Functional Units
• -Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
• -Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
• -Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
• -Two Multiply Functional Units:
• -Mixed-Precision IEEE Floating-Point Multiply Supported up to:
• -2 SP × SP → SP Per Clock
• -2 SP × SP → DP Every Two Clocks

TMS320C6748

SPRS590G -JUNE 2009-REVISED JANUARY 2017

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

The following table shows the thermal resistance characteristics for the PBGA-ZCE mechanical package.

Table 8-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]