TM4C123BH6PMI

Part: Tiva ™ TM4C123BH6PM Microcontroller — Texas Instruments

Type: ARM Cortex-M4F Microcontroller

Description: 32-bit ARM Cortex-M4F processor core operating at up to 80 MHz, featuring on-chip Flash, SRAM, and EEPROM memory, serial communications, advanced motion control, and analog peripherals.

Operating Conditions:

• Operating temperature: -40 to 85 °C
• Max clock frequency: 80 MHz

Features:

• ARM Cortex-M4F Processor Core
• On-Chip Memory
• Serial Communications Peripherals
• System Integration
• Advanced Motion Control
• Analog Peripherals
• JTAG and ARM Serial Wire Debug
• Hibernation Module
• Micro Direct Memory Access (μDMA)

The TM4C123BH6PM microcontroller component features and general function are discussed in more detail in the following section.

Table 22-6. Possible Pin Assignments for Alternate Functions

Table 22-6. Possible Pin Assignments for Alternate Functions (continued)

Table 22-6. Possible Pin Assignments for Alternate Functions (continued)

Table 22-6. Possible Pin Assignments for Alternate Functions (continued)

Table 23-32. ADC Electrical Characteristics (continued)

• a. V REF+ = 3.3V, F ADC =16 MHz unless otherwise noted.
• b. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to reduce capacitive coupling and cross talk. Analog signals configured adjacent to ADC input channels should meet the same source resistance and bandwidth limitations that apply to the ADC input signals.
• c. Two capacitors in parallel.
• d. Internal reference is connected directly between V DDA and GNDA (VREFi = V DDA - GNDA). In this mode, E O , E G , E T , and dynamic specifications are adversely affected due to internal voltage drop and noise on V DDA and GNDA.
• e. V ADCIN = V INP - V INN
• f. With signal common mode as V DDA /2.
• g. This parameter is defined as the average of the differential inputs.
• h. As shown in Figure 23-18 on page 1260, R ADC is the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC.
• i. See 'System Clock Specification with ADC Operation' on page 1249 for full ADC clock frequency specification.
• j. ADC conversion time (Tc) includes the ADC sample time (Ts).
• k. 12-bit DNL
• l. Gain error is measured at max code after compensating for offset. Gain error is equivalent to "Full Scale Error." It can be given in % of slope error, or in LSB, as done here.
• m. Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset error, gain error and INL) at any given ADC code.
• n. A low-noise environment is assumed in order to obtain values close to spec. The board must have good ground isolation between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist bandwidth. No anti-aliasing filter is provided internally.
• o. ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage ( < -74dB noise level in signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and affect dynamic characteristics. Clean external reference must be used to achieve shown specs.
• p. Differential signal with correct common mode, applied between two ADC inputs.
• q. SDR = -THD in dB.
• r. For higher frequency inputs, degradation in SDR should be expected.
• s. SNDR = S/(N+D) = SINAD (in dB)
• t. Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR - 1.76) / 6.02.
• u. Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements on single-ended inputs are highly dependent on how clean the test set-up is. If the input signal is not well-isolated on the board, higher noise than specified could potentially be seen at the ADC output.
• v. Note that this parameter does not include ADC error.

Figure 23-18. ADC Input Equivalency Diagram

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Device reliability may be adversely affected by exposure to absolute-maximum ratings for extended periods.

Note: The device is not guaranteed to operate properly at the maximum ratings.

Table 23-1. Absolute Maximum Ratings

Important: This device contains circuitry to protect the I/Os against damage due to high-static voltages; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (see 'Connections for Unused Signals' on page 1226).

Table 23-2. ESD Absolute Maximum Ratings

For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the V OL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package with the total number of high-current GPIO outputs not exceeding four for the entire package.

Table 23-5. Recommended DC Operating Conditions

a. These values are valid when LDO is in operation.

b. There are peripheral timing restrictions for SSI and LPC in Deep-sleep mode. Please refer to those peripheral characteristic sections for more information.

Table 23-6. Recommended GPIO Pad Operating Conditions

a. I O specifications reflect the maximum current where the corresponding output voltage meets the V OH /V OL thresholds. I O current can exceed these limits (subject to absolute maximum ratings).

Table 23-7. GPIO Current Restrictions a

a. Based on design simulations, not tested in production.

b. Sum of sink and source current for GPIOs as shown in Table 23-8 on page 1230.

Table 23-8. GPIO Package Side Assignments

MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996

NOTES: A. All linear dimensions are in millimeters.

• B. This drawing is subject to change without notice.
• C. Falls within JEDEC MS-026
• D. May also be thermally enhanced plastic with leads connected to the die pads.