TLV9062IDDFR

TLV906xS 10MHz, RRIO, CMOS Operational Amplifiers for Cost-Sensitive Systems

Manufacturer

Texas Instruments

Overview

Part: TLV906xS family

Type: CMOS Operational Amplifiers

Key Specs:

  • Low input offset voltage: ±0.3mV
  • Unity-gain bandwidth: 10MHz
  • Low broadband noise: 10nV/√ Hz
  • Low input bias current: 0.5pA
  • Low quiescent current: 538µA
  • Supply voltage range: 1.8V to 5.5V
  • Extended temperature range: –40°C to 125°C

Features:

  • Rail-to-rail input and output
  • Unity-gain stable
  • Internal RFI and EMI filter
  • Operational at supply voltages as low as 1.8V
  • Easier to stabilize with higher capacitive load due to resistive open-loop output impedance
  • Shutdown version (TLV906xS)
  • No phase reversal in overdrive condition

Applications:

  • E-bikes
  • Smoke detectors
  • HVAC: heating, ventilating, and air conditioning
  • Motor control: AC induction
  • Refrigerators
  • Wearable devices
  • Laptop computers
  • Washing machines
  • Sensor signal conditioning
  • Power modules
  • Barcode scanners
  • Active Filters
  • Low-side current sensing

Package:

  • DBV (SOT-23, 5): 2.90mm × 1.60 mm
  • DCK (SC70, 5): 2.00mm × 1.25 mm
  • DRL (SOT-553, 5): 1.60mm × 1.20 mm
  • DPW (X2SON, 5): 0.80mm × 0.80mm
  • DBV (SOT-23, 6): 2.90mm × 1.60 mm
  • DRY (USON, 6): 1.45mm × 1.00 mm
  • D (SOIC, 8): 4.90mm × 3.90 mm
  • PW (TSSOP, 8): 3.00mm × 4.40 mm
  • DGK (VSSOP, 8): 3.00mm × 3.00 mm
  • DDF (SOT-23, 8): 2.90mm × 1.60 mm
  • DSG (WSON, 8): 2.00mm × 2.00 mm
  • DGS (VSSOP, 10): 3.00mm × 3.00 mm
  • RUG (X2QFN, 10): 2.00mm × 1.50mm
  • YCK (DSBGA, 9): 1.00mm x 1.00mm
  • D (SOIC, 14): 8.65mm × 3.90 mm
  • PW (TSSOP, 14): 5.00mm × 4.40 mm
  • RTE (WQFN, 16): 3.00mm × 3.00mm
  • RUC (X2QFN, 14): 2.00mm × 2.00mm
{
  "manufacturer": null,
  "part_family": "TLV906xS",
  "

Features

• Rail-to-rail input and output

• Low input offset voltage: ±0.3mV

• Unity-gain bandwidth: 10MHz

• Low broadband noise: 10nV/√ Hz

• Low input bias current: 0.5pA

• Low quiescent current: 538µA

• Unity-gain stable

• Internal RFI and EMI filter

• Operational at supply voltages as low as 1.8V

• Easier to stabilize with higher capacitive load due to resistive open-loop output impedance

• Shutdown version: TLV906xS

• Extended temperature range: –40°C to 125°C

Applications

Pin Configuration

Figure 4-1. TLV9061 DBV or DRL Package, 5-Pin SOT-23 or SOT-553 (Top View) Figure 4-2. TLV9061 DCK Package, 5-Pin SC70 (Top View)

Figure 4-3. TLV9061 DPW Package, 5-Pin X2SON (Top View)

Table 4-1. Pin Functions: TLV9061

| | PIN | |------|--------------------|------|-------|---------|---------------------------------------------------------------| | NAME | SOT-23,
SOT-553 | SC70 | X2SON | TYPE(1) | DESCRIPTION | | IN– | 4 | 3 | 2 | I | Inverting input | | IN+ | 3 | 1 | 4 | I | Noninverting input | | OUT | 1 | 4 | 1 | O | Output | | V– | 2 | 2 | 3 | I or — | Negative (low) supply or ground (for single-supply operation) | | V+ | 5 | 5 | 5 | I | Positive (high) supply |

(1) I = input, O = output

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Product Folder Links: TLV9061 TLV9062 TLV9064

Figure 4-4. TLV9061S DBV Package, 6-Pin SOT-23 (Top View)

Figure 4-5. TLV9061S DRY Package, 6-Pin USON (Top View)

Table 4-2. Pin Functions: TLV9061S

| | PIN | | TYPE(1) | |------|--------|------|---------|----------------------------------------------------------------------------------------------------------|--|--| | NAME | SOT-23 | USON | | DESCRIPTION | | IN– | 4 | 3 | I | Inverting input | | IN+ | 3 | 1 | I | Noninverting input | | OUT | 1 | 4 | O | Output | | SHDN | 5 | 5 | I | Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function
section for more information. | | V– | 2 | 2 | I or — | Negative (low) supply or ground (for single-supply operation) | | V+ | 6 | 6 | I | Positive (high) supply |

(1) I = input, O = output

Figure 4-6. TLV9062 D, DGK, PW, or DDF Package, 8-Pin SOIC, VSSOP, TSSOP, or SOT-23 (Top View)

A. Connect thermal pad to V–

Figure 4-7. TLV9062 DSG Package, 8-Pin WSON With Exposed Thermal Pad (Top View)

Table 4-3. Pin Functions: TLV9062

| | PIN | TYPE(1) | |------|-----|---------|------------------------------------------------------------------|--| | NAME | NO. | | DESCRIPTION | | IN1– | 2 | I | Inverting input, channel 1 | | IN1+ | 3 | I | Noninverting input, channel 1 | | IN2– | 6 | I | Inverting input, channel 2 | | IN2+ | 5 | I | Noninverting input, channel 2 | | OUT1 | 1 | O | Output, channel 1 | | OUT2 | 7 | O | Output, channel 2 | | V– | 4 | — | Negative (lowest) supply or ground (for single-supply operation) | | V+ | 8 | — | Positive (highest) supply |

Figure 4-8. TLV9062S DGS Package, 10-Pin VSSOP (Top View)

Figure 4-9. TLV9062S RUG Package, 10-Pin X2QFN (Top View)

Figure 4-10. TLV9062S YCK Package 9-Pin DSBGA (WCSP) Bottom View

Table 4-4. Pin Functions: TLV9062S

| | PIN | |-------|-------|-------|-----------------|--------|-------------------------------------------------------------------------------------------------------------|--|--| | NAME | VSSOP | X2QFN | DSBGA
(WCSP) | I/O | DESCRIPTION | | IN1– | 2 | 9 | B1 | I | Inverting input, channel 1 | | IN1+ | 3 | 10 | A1 | I | Noninverting input, channel 1 | | IN2– | 8 | 5 | B3 | I | Inverting input, channel 2 | | IN2+ | 7 | 4 | A3 | I | Noninverting input, channel 2 | | OUT1 | 1 | 8 | C1 | O | Output, channel 1 | | OUT2 | 9 | 6 | C3 | O | Output, channel 2 | | SHDN1 | 5 | 2 | — | I | Shutdown: low = amp disabled, high = amp enabled, channel 1. See Shutdown
Function for more information. | | SHDN2 | 6 | 3 | — | I | Shutdown: low = amp disabled, high = amp enabled, channel 1. See Shutdown
Function for more information. | | SHDN | — | — | B2 | | Shutdown: low = both amplifiers disabled, high = both amplifiers enabled | | V– | 4 | 1 | A2 | I or — | Negative (low) supply or ground (for single-supply operation) | | V+ | 10 | 7 | C2 | I | Positive (high) supply |

Figure 4-11. TLV9064 RUC Package, 14-Pin X2QFN (Top View)

A. Connect thermal pad to V-

Figure 4-12. TLV9064 RTE Package, 16-Pin WQFN With Exposed Thermal Pad (Top View)

Figure 4-13. TLV9064 D or PW Package, 14-Pin SOIC or TSSOP (Top View)

Table 4-5. Pin Functions: TLV9064

| | ı | PIN | | | DESCRIPTION | |------|----------------|------|-------|---------------------|---------------------------------------------------------------|--|--| | NAME | SOIC,
TSSOP | WQFN | X2QFN | TYPE (1) | | IN1- | 2 | 16 | 1 | I | Inverting input, channel 1 | | IN1+ | 3 | 1 | 2 | I | Noninverting input, channel 1 | | IN2- | 6 | 4 | 5 | I | Inverting input, channel 2 | | IN2+ | 5 | 3 | 4 | I | Noninverting input, channel 2 | | IN3- | 9 | 9 | 8 | I | Inverting input, channel 3 | | IN3+ | 10 | 10 | 9 | I | Noninverting input, channel 3 | | IN4- | 13 | 13 | 12 | ı | Inverting input, channel 4 | | IN4+ | 12 | 12 | 11 | ı | Noninverting input, channel 4 | | NC | _ | 6, 7 | _ | _ | No internal connection | | OUT1 | 1 | 15 | 14 | 0 | Output, channel 1 | | OUT2 | 7 | 5 | 6 | 0 | Output, channel 2 | | OUT3 | 8 | 8 | 7 | 0 | Output, channel 3 | | OUT4 | 14 | 14 | 13 | 0 | Output, channel 4 | | V- | 11 | 11 | 10 | I or — | Negative (low) supply or ground (for single-supply operation) | | V+ | 4 | 2 | 3 | I | Positive (high) supply |

A. Connect thermal pad to V-

Figure 4-14. TLV9064S RTE Package, 16-Pin WQFN With Exposed Thermal Pad (Top View)

Table 4-6. Pin Functions: TLV9064S

| P | IN | TYPE (1) | DESCRIPTION | |--------|-----|---------------------|-------------------------------------------------------------------------------------------------------------------------|--|--|--| | NAME | NO. | ITPE | DESCRIPTION | | IN1- | 16 | I | Inverting input, channel 1 | | IN1+ | 1 | I | Noninverting input, channel 1 | | IN2- | 4 | I | Inverting input, channel 2 | | IN2+ | 3 | I | Noninverting input, channel 2 | | IN3- | 9 | I | Inverting input, channel 3 | | IN3+ | 10 | I | Noninverting input, channel 3 | | IN4- | 13 | I | verting input, channel 4 | | IN4+ | 12 | I | Noninverting input, channel 4 | | OUT1 | 15 | 0 | Output, channel 1 | | OUT2 | 5 | 0 | Output, channel 2 | | OUT3 | 8 | 0 | Output, channel 3 | | OUT4 | 14 | 0 | Output, channel 4 | | SHDN12 | 6 | ı | Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function section for more information. | | SHDN34 | 7 | I | Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function section for more information. | | V- | 11 | I or — | Negative (low) supply or ground (for single-supply operation) | | V+ | 2 | I | Positive (high) supply |

Electrical Characteristics

For VS (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)

VOUT = VS / 2 (unless otherwise noted)
PARAMETER		TEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VS = 5V±0.3±1.6
VOS
Input offset voltage		VS = 5V, TA = –40°C to 125°C±2mV
dVOS/dTDriftVS = 5V, TA = –40°C to 125°C±0.53µV/°C
PSRRPower-supply rejection ratio±7±80µV/V
Channel separation, DCVS = 1.8V – 5.5V, VCM = (V–)
At DC		100dB
INPUT VOLTAGE RANGE
VCMCommon-mode voltage rangeVS = 1.8V to 5.5V(V–) – 0.1(V+) + 0.1V
VS = 5.5V, (V–) – 0.1V < VCM < (V+) – 1.4V,
TA = –40°C to 125°C		80103
VS = 5.5V, VCM = –0.1V to 5.6V,
TA = –40°C to 125°C		5787
CMRRCommon-mode rejection ratioVS = 1.8V, (V–) – 0.1V < VCM < (V+) – 1.4V,
TA = –40°C to 125°C		88dB
VS = 1.8V, VCM = –0.1V to 1.9V,
TA = –40°C to 125°C		81
INPUT BIAS CURRENT
IBInput bias current±0.5pA
IOSInput offset current±0.05pA
NOISE
EnInput voltage noise (peak-to
peak)		VS = 5V, f = 0.1Hz to 10Hz4.77µVPP
VS = 5V, f = 10kHz10
enInput voltage noise densityVS = 5V, f = 1kHz16nV/√ Hz
inInput current noise densityf = 1kHz23fA/√ Hz
INPUT CAPACITANCE
CIDDifferential2pF
CICCommon-mode4pF
OPEN-LOOP GAIN
VS = 1.8V, (V–) + 0.04V < VO < (V+) – 0.04V,
RL = 10kΩ		100
AOLOpen-loop voltage gainVS = 5.5V, (V–) + 0.05V < VO < (V+) – 0.05V,
RL = 10kΩ		104130dB
VS = 1.8V, (V–) + 0.06V < VO < (V+) – 0.06V,
RL = 2kΩ		100
VS = 5.5V, (V–) + 0.15V < VO < (V+) – 0.15V,
RL = 2kΩ		130
FREQUENCY RESPONSE
GBPGain bandwidth productVS = 5V, G = +110MHz
φmPhase marginVS = 5V, G = +155°
SRSlew rateVS = 5V, G = +16.5V/µs
To 0.1%, VS = 5V, 2V step , G = +1, CL = 100pF0.5
tSSettling timeTo 0.01%, VS = 5V, 2V step,
G = +1, CL = 100pF		1µs
tOROverload recovery timeVS = 5V, VIN × gain > VS0.2µs
THD + NTotal harmonic distortion +
noise(1)		VS = 5.5V, VCM = 2.5V, VO = 1VRMS, G = +1,
f = 1kHz		0.0008%
OUTPUT
VOVoltage output swing from supply
rails		VS = 5.5V, RL = 10kΩ
VS = 5.5V, RL = 2kΩ		20
60		mV
Short-circuit currentVS = 5V±50mA

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Absolute Maximum Ratings

over operating ambient temperature (unless otherwise noted)(1)

MINMAXUNIT
Supply voltage [(V+) – (V–)]06V
Voltage(2)Common-mode(V–) – 0.5(V+) + 0.5V
Signal input pinsDifferential(V+) – (V–) + 0.2V
Current(2)–1010mA
Output short-circuit(3)ContinuousmA
Specified, TA–40125
TemperatureJunction, TJ150°C
Storage, Tstg–65150

Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MINMAXUNIT
VSSupply voltage (VS = [V+] – [V–])1.85.5V
VIInput voltage range(V–) – 0.1(V+) + 0.1V
VOOutput voltage rangeV–V+V
VSHDN_IHHigh level input voltage at shutdown pin (amplifier enabled)1.1V+V
VSHDN_ILLow level input voltage at shutdown pin (amplifier disabled)V–0.2V
TASpecified temperature–40125°C

(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5V beyond the supply rails to 10mA or less.

(3) Short-circuit to ground, one amplifier per package.

(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

Thermal Information

Figure 4-14. TLV9064S RTE Package, 16-Pin WQFN With Exposed Thermal Pad (Top View)

Table 4-6. Pin Functions: TLV9064S

| P | IN | TYPE (1) | DESCRIPTION | |--------|-----|---------------------|-------------------------------------------------------------------------------------------------------------------------|--|--|--| | NAME | NO. | ITPE | DESCRIPTION | | IN1- | 16 | I | Inverting input, channel 1 | | IN1+ | 1 | I | Noninverting input, channel 1 | | IN2- | 4 | I | Inverting input, channel 2 | | IN2+ | 3 | I | Noninverting input, channel 2 | | IN3- | 9 | I | Inverting input, channel 3 | | IN3+ | 10 | I | Noninverting input, channel 3 | | IN4- | 13 | I | verting input, channel 4 | | IN4+ | 12 | I | Noninverting input, channel 4 | | OUT1 | 15 | 0 | Output, channel 1 | | OUT2 | 5 | 0 | Output, channel 2 | | OUT3 | 8 | 0 | Output, channel 3 | | OUT4 | 14 | 0 | Output, channel 4 | | SHDN12 | 6 | ı | Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function section for more information. | | SHDN34 | 7 | I | Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function section for more information. | | V- | 11 | I or — | Negative (low) supply or ground (for single-supply operation) | | V+ | 2 | I | Positive (high) supply |

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
TLV9062Texas Instruments—
TLV9062-Q1Texas Instruments—
TLV9062-Q1.HTMLTexas Instruments—
TLV9062IDDFR.ATexas Instruments—
TLV9062IDGKRTexas Instruments—
TLV9062IDGKR.ATexas Instruments—
TLV9062IDGKRG4Texas Instruments—
TLV9062IDGKTTexas Instruments—
TLV9062IDGKT.ATexas Instruments—
TLV9062IDRTexas Instruments—
TLV9062IDR.ATexas Instruments—
TLV9062IDRG4Texas Instruments—
TLV9062IDRG4.ATexas Instruments—
TLV9062IDSGRTexas Instruments—
TLV9062IDSGR.ATexas Instruments—
TLV9062IDSGRG4Texas Instruments—
TLV9062IDSGTTexas Instruments—
TLV9062IDSGT.ATexas Instruments—
TLV9062IPWRTexas Instruments—
TLV9062IPWR.ATexas Instruments—
TLV9062STexas Instruments—
TLV9062SIDGSRTexas Instruments—
TLV9062SIRUGRTexas Instruments—
TLV9062SIYCKRTexas Instruments—
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