TLE5012B-E5020

Part: TLE5012B, Infineon Technologies AG

Type: GMR-Based Angle Sensor

Key Specs:

• null

Features:

• null

Applications:

• null

Package:

• PG-DSO-8

• Giant Magneto Resistance (GMR)-based principle
• Integrated magnetic field sensing for angle measurement
• 360° angle measurement with revolution counter and angle speed measurement
• Two separate highly accurate single bit SD-ADC
• 15 bit representation of absolute angle value on the output (resolution of 0.01°)
• 16 bit representation of sine / cosine values on the interface
• Max. 1.0° angle error over lifetime and temperature-range with activated auto-calibration
• Bi-directional SSC Interface up to 8Mbit/s
• Supports Safety Integrity Level (SIL) with diagnostic functions and status information
• Interfaces: SSC, PWM, Incremental Interface (IIF), Hall Switch Mode (HSM), Short PWM Code (SPC, based on SENT protocol defined in SAE J2716)
• Output pins can be configured (programmed or pre-configured) as push-pull or open-drain
• Bus mode operation of multiple sensors on one line is possible with SSC or SPC interface in open-drain configuration
• 0.25 μm CMOS technology
• Automotive qualified: -40°C to 150°C (junction temperature)
• ESD > 4kV (HBM)
• RoHS compliant (Pb-free package)
• Halogen-free

Figure 2-4 Pin configuration (top view)

1. Internal pull-ups on CSQ and DATA pin are always enabled.

2. Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is always enabled.

Table 4-1 Absolute maximum ratings

The application circuits in this chapter show the various communication possibilities of the TLE5012B. The pin output mode configuration is device-specific and it can be either push-pull or open-drain. The bit IFAB_OD (register IFAB, 0DH) indicates the output mode for the IFA, IFB and IFC pins. The SSC pins are by default pushpull (bit SSC_OD, register MOD_3, 09H).

Figure 3-1 shows a basic block diagram of a TLE5012B with Incremental Interface and SSC configuration. The derivate TLE5012B - E1000 is by default configured with push-pull IFA (IIF_A), IFB (IIF_ B) and IFC (IIF_IDX) pins.

Figure 3-1 Application circuit for TLE5012B with IIF interface and SSC (using internal CLK)

In case that the IFA, IFB and IFC pins are configurated via the SSC interface as open-drain pins, three resistors (one for each line) between output line and VDD would be recommended (e.g. 2.2kΩ).

Figure 3-2 shows a basic block diagram of the TLE5012B with HS Mode and SSC configuration. The derivate TLE5012B - E3005 is by default configurated with push-pull IFA (HS1), IFB (HS2) and IFC (HS3) pins.

Figure 3-2 Application circuit for TLE5012B with HS Mode and SSC (using internal CLK)

Application Circuits

In case that the IFA, IFB and IFC pins are configurated via the SSC interface as open drain pins, three resistors (one for each line) between the output line and VDD would be recommended (e.g. 2.2kΩ).

The TLE5012B can be configured with PWM only (Figure 3-3). The derivate TLE5012B - E5000 is by default configurated with push-pull IFA (PWM) pin. Therefore the following configuration is recommended:

Figure 3-3 Application circuit for TLE5012B with only PWM interface (using internal CLK)

The TLE5012B - E5020 is also a PWM derivate but with open drain IFA (PWM) pin. A pull-up resistor (e.g. 2.2kΩ) should then be added between the IFA line and VDD, as shown in Figure 3-4.

Figure 3-4 Application circuit for TLE5012B with only PWM interface (using internal CLK)

For safety reasons it is better that the non-used pins are connected to ground, rather than floating. A resistor between he DATA line pin and ground is recommended to avoid shortcuts if DATA generates any unexpected output. The CSQ line has to be connected to VDD to avoid unintentional activation of the SSC interface.

TLE5012B

Application Circuits

The TLE5012B can be configured with SPC only (Figure 3-5). This is only possible with the TLE5012B - E9000 derivate, which is by default configurated with an open-drain IFA (SPC) pin.

Figure 3-5 Application circuit for TLE5012B with only SPC interface (using internal CLK)

In Figure 3-5 the IFC (S_NR[1]) and SCK (S_NR[0]) pins are set to ground to generate the slave number (S_NR) 0D (or 00B). For safety reasons it is better that the non-used pins are connected to ground, rather than floating. A resistor between the DATA line pin and ground is recommended to avoid shortcuts if DATA generates any unexpected output. The CSQ line has to be connected to VDD to avoid unintentional activation of the SSC interface.

Synchronous Serial Communication (SSC) configuration

In Figure 3-1 and Figure 3-2 the SSC interface has the default push-pull configuration (see details in Figure 3-6). Series resistors on the DATA, SCK (serial clock signal) and CSQ (chip select) lines are recommended to limit the current in the erroneous case that either the sensor pushes high and the microcontroller pulls low at the same time or vice versa. The resistors in the SCK and CSQ lines are only necessary in case of disturbances or noise.

Figure 3-6 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application)

Application Circuits

It is also possible to use an open-drain setup for the DATA, SCK and CSQ lines. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLE5012B devices for redundancy reasons). This mode can be activated using the bit SSC_OD.

The open-drain configuration can be seen in Figure 3-7. Series resistors on the DATA, SCK, and CSQ lines are recommended to limit the current in case either the microcontroller or the sensor are accidentally switched to pushpull. A pull-up resistor of typ. 1 kΩ is required on the DATA line.

Figure 3-7 SSC configuration in sensor-slave mode and open-drain (bus systems)

4.1 Absolute Maximum Ratings

Table 4-1 Absolute maximum ratings

4.2 Operating Range

The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012B. All parameters specified in the following sections refer to these operating conditions, unless otherwise noted. Table 4-2 is valid for -40°C < TJ < 150°C unless otherwise noted.

Parameter	Symbol	Min.	Typ.	Max.	Unit	Note / Test Condition
Supply voltage	VDD	3.0	5.0	5.5	V	1)
Supply current	IDD		14	16	mA
Magnetic induction at TJ = 25°C³)	BXY	30		50	mT	-40°C < TJ < 150°C
		30		60	mT	-40°C < TJ < 100°C
		30		70	mT	-40°C < TJ < 85°C
Extended magnetic induction range at TJ = 25°C³)	BXY	25		30	mT	Additional angle error of 0.1°
Angle range	Ang	0		360	°
POR level	VPOR	2.0		2.9	V	Power-on reset
POR hysteresis	VPORhy		30		mV
Parameter	Symbol	Values			Unit	Note / Test Condition
		Min.	Typ.	Max.
Supply voltage	VDD	3.0	5.0	5.5	V	1)
Supply current	IDD		14	16	mA
Magnetic induction at TJ = 25°C2)3)	BXY	30		50	mT	-40°C < TJ < 150°C
		30		60	mT	-40°C

Table 4-2 Operating range** (cont'd)**and parameters

1. Directly blocked with 100-nF ceramic capacitor

2. Values refer to a homogeneous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT).

• 1. During "Power-on time," write access is not permitted (except for the switch to External Clock which requires a readout as a confirmation that external clock is selected)
• 1. Not subject to production test verified by design/characterization

The field strength of a magnet can be selected within the colored area of Figure 4-1. By limitation of the junction temperature, a higher magnetic field can be applied. In case of a maximum temperature TJ=100°C, a magnet with up to 60mT at TJ = 25°C is allowed.

It is also possible to widen the magnetic field range for higher temperatures. In that case, additional angle errors have to be considered.

Figure 4-1 Allowed magnetic field range as function of junction temperature.

³⁾ See Figure 4-1

4.3 Characteristics

4.3.1 Input/Output characteristics

The indicated parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage VDD = 5.0 V and 25 °C, unless individually specified. All other values correspond to -40 °C < TJ < 150°C.

Within the register MOD_3, the driver strength and the slope for push-pull communication can be varied depending on the sensor output. The driver strength is specified in Table 4-3 and the slope fall and rise time in Table 4-4.

1. Max. current to GND over open-drain output

2. At VDD = 5 V

Table 4-4 Driver strength characteristic

1. Valid for push-pull output

2. Not subject to production test - verified by design/characterization

Table 4-5 Electrical parameters for 4.5 V < VDD < 5.5 V

1. Internal pull-ups on CSQ and DATA pin are always enabled.

2. Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is always enabled.

Table 4-6 Electrical parameters for 3.0 V < VDD < 3.6 V

1. Internal pull-ups on CSQ and DATA pin are always enabled.

2. Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is always enabled.

4.3.2 ESD Protection

Table 4-7 ESD protection

1. Socketed Device Model (SDM) according to: ESDA/ANSI/ESD SP5.3.2-2008

4.3.3 GMR Parameters

All parameters apply over BXY = 30mT and TA = 25°C, unless otherwise specified.

Table 4-8 Basic GMR parameters

1. Not subject to production test - verified by design/characterization

2. See Figure 4-2

3. k = 100*(AX/AY)

4. OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2

Figure 4-2 Offset and amplitude definition

4.3.4 Angle Performance

After internal calculation, the sensor has a remaining error, as shown in Table 4-9. The error value refers to BZ= 0mT and the operating conditions given in Table 4-2 "Operating range and parameters" on Page 19.

The overall angle error represents the relative angle error. This error describes the deviation from the reference line after zero-angle definition. It is valid for a static magnetic field.

If the magnetic field is rotating during the measurement, an additional propagation error is caused by the angle delay time (see Table 4-10 "Signal processing" on Page 27), which the sensor needs to calculate the angle from the raw sine and cosine values from the MR bridges. In fast-turning applications, prediction can be enabled to reduce this propagation error.

Table 4-9 Angle performance

1. At 25°C, B = 30mT

2. Including hysteresis error, caused by revolution direction change

3. Relative error after zero angle definition

4. Not subject to production test - verified by design/characterization

5. 0h

If autocalibration (see Chapter 4.3.5) is enabled and the temperature changes by more than 5 Kelvin during 1.5 revolutions an additional error has to be added to the specified angle error in Table 4-9. This error depends on the temperature change (Delta Temperature) as well as from the initial temperature (Tstart) as shown in Figure 4-3. Once the temperature stabilizes and the application completes 1.5 revolutions, then the angle error is as specified in Table 4-9.

For negative Delta Temperature changes (from higher to lower temperatures) the additional angle error will be smaller than the corresponding positive Delta Temperature changes (from lower to higher temperatures) shown in Figure 4-3. The Figure 4-3 applies to the worst case.

Figure 4-3 Additional angle error for temperature changes above 5 Kelvin within 1.5 revolutions

4.3.5 Autocalibration

The autocalibration enables online parameter calculation and therefore reduces the angle error due to temperature and lifetime drifts.

The TLE5012B is a pre-calibrated sensor, so autocalibration is only enabled in some devices by default. The update mode can be chosen with the AUTOCAL setting in the MOD_2 register. The TLE5012B needs 1.5 revolutions to generate new autocalibration parameters. These parameters are continuously updated. The parameters are updated in a smooth way (one Least-Significant Bit within the chosen range or time) to avoid an angle jump on the output.

AUTOCAL Modes:

• 00: No autocalibration
• 01: Autocalibration Mode 1. One LSB to final values within the update time tupd (depending on FIR_MD setting).
• 10: Autocalibration Mode 2. Only one LSB update over one full parameter generation (1.5 revolutions). After update of one LSB, the autocalibration will calculate the parameters again.
• 11: Autocalibration Mode 3. One LSB to final values within an angle range of 11.25°

(4.1)

4.3.6 Signal Processing

The signal path of the TLE5012B is depicted in Figure 4-4. It consists of the GMR-bridge, ADC, filter and angle calculation. The delay time between a physical change in the GMR elements and a signal on the output depends on the filter and interface configurations. In fast turning applications, this delay causes an additional rotation speed dependent angle error.

The TLE5012B has an optional prediction feature, which serves to reduce the speed dependent angle error in applications where the rotation speed does not change abruptly. Prediction uses the difference between current and last two angle values to approximate the angle value which will be present after the delay time (see Figure 4-5). The output value is calculated by adding this difference to the measured value, according to Equation (4.1).

α(t+1) = α(t) + α(t-1) - α(t-2)time Angle With Prediction Without Prediction tadel tupd Magnetic field direction Sensor output

Figure 4-5 Delay of sensor output

Table 4-10 Signal processing

1. Not subject to production test - verified by design/characterization

2. Valid at constant rotation speed

All delay times specified in Table 4-10 are valid for an ideal internal oscillator frequency of 24 MHz. For the exact timing, the variation of the internal oscillator frequency has to be taken into account (see Chapter 4.3.7)

4.3.7 Clock Supply (CLK Timing Definition)

The internal clock supply of the TLE5012B is subject to production-specific variations, which have to be considered for all timing specifications.

• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike-filtered.
• The duty cycle factor should typically be 50%, but it can vary between 30% and 70%.
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically and the sensor restarts with the internal clock. This is indicated by the S_RST, and CLK_SEL bits, and additionally by the Safety Word (see Chapter 4.4.1.2).

Figure 4-6 External CLK timing definition

1. Maximum duty cycle factor: tCLKh(max) / tCLK with tCLK= 1 / fCLK

4.4 Interfaces

4.4.1 Synchronous Serial Communication (SSC)

The 3-pin SSC interface consists of a bi-directional push-pull (tri-state on receive) or open-drain data pin (configurable with SSC_OD bit) and the serial clock and chip-select input pins. The SSC Interface is designed to communicate with a microcontroller peer-to-peer for fast applications.

4.4.1.1 SSC Timing Definition

Figure 4-7 SSC timing

SSC Inactive Time (CSoff)

The SSC inactive time defines the delay time after a transfer before the TLE5012B can be selected again.

1. Not subject to production test - verified by design/characterization

TLE5012B

Specification

1. Not subject to production test - verified by design/characterization

4.4.1.2 SSC Data Transfer

The SSC data transfer is word-aligned. The following transfer words are possible:

• Command Word (to access and change operating modes of the TLE5012B)
• Data words (any data transferred in any direction)
• Safety Word (confirms the data transfer and provides status information)

Figure 4-8 SSC data transfer (data-read example)

Figure 4-9 SSC data transfer (data-write example)

Command Word

SSC Communication between the TLE5012B and a microcontroller is generally initiated by a command word. The structure of the command word is shown in Table 4-15. If an update is triggered by shortly pulling low CSQ without a clock on SCK a snapshot of all system values is stored in the update registers simultaneously. A read command with the UPD bit set then allows to readout this consistent set of values instead of the current values. Bits with an update buffer are marked by an "u" in the Type column in register descriptions. The initialization of such an update is described on page 33.

Table 4-15 Structure of the Command Word (cont'd)

Safety Word

The safety word consists of the following bits:

1. When an error occurs, the corresponding status bit in the safety word remains "low" until the STAT register (address 00H) is read via SSC interface.

Bit Types

The types of bits used in the registers are listed here:

Table 4-17 Bit Types

Data communication via SSC

Figure 4-11 Update of update registers

The data communication via SSC interface has the following characteristics:

• The data transmission order is Most-Significant Bit (MSB) first, Last-Significant Bit (LSB) last.
• Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
• The SSC Interface is word-aligned. All functions are activated after each transmitted word.
• After every data transfer with ND ≥ 1, the 16-bit Safety Word is appended by the TLE5012B.
• A "high" condition on the Chip Select pin (CSQ) of the selected TLE5012B interrupts the transfer immediately. The CRC calculator is automatically reset.
• After changing the data direction, a delay twr_delay (see Table 4-14) has to be implemented before continuing the data transfer. This is necessary for internal register access.
• If in the Command Word the number of data is greater than 1 (ND > 1), then a corresponding number of consecutive registers is read, starting at the address given by ADDR.
• In case an overflow occurs at address 3FH, the transfer continues at address 00H.
• If in the Command Word the number of data is zero (ND = 0), the register at the address given by ADDR is read, but no Safety Word is sent by the TLE5012B. This allows a fast readout of one register.
• At a rising edge of CSQ without a preceding data transfer (no SCK pulse, see Figure 4-11), the content of all registers which have an update buffer is saved into the buffer. This procedure serves to take a snapshot of all relevant sensor parameters at a given time. The content of the update buffer can then be read by sending a read command for the desired register and setting the UPD bit of the Command Word to "1".
• After sending the Safety Word, the transfer ends. To start another data transfer, the CSQ has to be deselected once for at least tCSoff.
• By default, the SSC interface is set to push-pull. The push-pull driver is active only if the TLE5012B has to send data, otherwise the DATA pin is set to high-impedance.

Cyclic Redundancy Check (CRC)

• This CRC is according to the J1850 Bus Specification.
• Every new transfer restarts the CRC generation.
• Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
• Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used (see Figure 4-12)
• The seed value of the fast CRC circuit is '11111111B'.
• The remainder is inverted before transmission.

Figure 4-12 Fast CRC polynomial division circuit

4.4.2 Pulse Width Modulation (PWM) Interface

The Pulse Width Modulation (PWM) interface can be selected via SSC (IF_MD = '01').

The PWM update rate can be programmed within the register 0EH (IFAB_RES) in the following steps:

• ~0.25 kHz with 12-bit resolution
• ~0.5 kHz with 12-bit resolution
• ~1.0 kHz with 12-bit resolution
• ~2.0 kHz with 12-bit resolution

PWM uses a square wave with constant frequency whose duty cycle is modulated according to the last measured angle value (AVAL register).

Figure 4-13 shows the principal behavior of a PWM with various duty cycles and the definition of timing values. The duty cycle of a PWM is defined by the following general formulas:Duty Cycle &= frac{t_on}{t_PWM} If t_PWM &= t_on + t_off If t_PWM &= frac{1}{t_PWM}The duty cycle range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. In case the sensor detects an error, the corresponding error bit in the Status register is set and the PWM duty cycle goes to the lower (0 - 6.25%) or upper (93.75 - 100%) diagnostic range, depending on the kind of error (see "Output duty cycle range" in Table 4-18). Except for an S_ADCT error, an error is only indicated by the corresponding diagnostic duty-cycle as long as it persists, but at least once. However the value in the status register will remain until a readout via the SSC interface or a chip reset is performed. An S_ADCT error on the other side will be transmitted until the next chip reset. This fail-safe diagnostic function can be disabled via the MOD₄ register. Sensors with preset PWM are available as TLE5012B E50x0.

(4.2)

Figure 4-13 Typical example of a PWM signal

Table 4-18 PWM interface

1. Not subject to production test - verified by design/characterization

The PWM frequency is derived from the digital clock via{rcl}f_PWM &=& frac{f_DIG ast 2 IFAB _RES}{24 ast 4096}

The min/max values given in Table 4-18 take into account the internal digital clock variation specified in Chapter 4.3.7. If external clock is used, the variation of the PWM frequency can be derived from the variation of the external clock using Equation (4.3).

(4.3)

4.4.3 Short PWM Code (SPC)

The Short PWM Code (SPC) is a synchronized data transmission based on the SENT protocol (Single Edge Nibble Transmission) defined by SAE J2716. As opposed to SENT, which implies a continuous transmission of data, the SPC protocol transmits data only after receiving a specific trigger pulse from the microcontroller. The required length of the trigger pulse depends on the sensor number, which is configurable. Thereby, SPC allows the operation of up to four sensors on one bus line.

SPC enables the use of enhanced protocol functionality due to the ability to select between various sensor slaves (ID selection). The slave number (S_NR) can be given by the external circuit of SCK and IFC pin. In case of VDD on SCK, the S_NR[0] can be set to 1 and in the case of GND on SCK the S_NR[0] is equal to 0. S_NR[1] can be adjusted in the same way by the IFC pin.

As in SENT, the time between two consecutive falling edges defines the value of a 4-bit nibble, thus representing numbers between 0 and 15. The transmission time therefore depends on the transmitted data values. The single edge is defined by a 3 Unit Time (UT, see Chapter 4.4.3.1) low pulse on the output, followed by the high time defined in the protocol (nominal values, may vary depending on the tolerance of the internal oscillator and the influence of external circuitry). All values are multiples of a unit time frame concept. A transfer consists of the following parts (Figure 4-14):

• A trigger pulse by the master, which initiates the data transmission
• A synchronization period of 56 UT (in parallel, a new sample is calculated)
• A status nibble of 12-27 UT
• Between 3 and 6 data nibbles of 12-27 UT
• A CRC nibble of 12-27 UT
• An end pulse to terminate the SPC transmission

Figure 4-14 SPC frame example

The CRC checksum includes the status nibble and the data nibbles, and can be used to check the validity of the decoded data. The sensor is available for the next trigger pulse 90μs after the falling edge of the end pulse (see Figure 4-15).

In SPC mode, the sensor does not continuously calculate an angle from the raw data. Instead, the angle calculation is started by the trigger nibble from the master. In this mode, the AVAL register, which stores the angle value and can be read via SSC, contains the angle which was calculated after the last SPC trigger nibble.

In parallel to SPC, the SSC interface can be used for individual configuration. The number of transmitted SPC nibbles can be changed to customize the amount of information sent by the sensor. The frame contains a 16-bit angle value and an 8-bit temperature value in the full configuration (Table 4-19).

Sensors with preset SPC are available as TLE5012B E9000

Table 4-19 Frame configuration

The status nibble, which is sent with each SPC data frame, provides an error indication similar to the Safety Word of the SSC protocol. In case the sensor detects an error, the corresponding error bit in the Status register is set and either the bit SYS_ERR or the bit ELEC_ERR of the status nibble will be "high", depending on the kind of error (see Table 4-20). Except for an S_ADCT error, an error is only indicated by the corresponding error bit in the status nibble as long as it persists, but at least once. However the value in the status register will remain until a read-out via the SSC interface or a chip reset is performed. An S_ADCT error on the other side will be transmitted until the next chip reset. The fail-safe diagnostic function can be disabled via the MOD_4 register.

Table 4-20 Structure of status nibble

4.4.3.1 Unit Time Setup

The basic SPC protocol unit time granularity is defined as 3 μs. Every timing is a multiple of this basic time unit.To achieve more flexibility, trimming of the unit time can be done within IFAB_HYST. This enables a setup of different unit times.

1. Not subject to production test - verified by design/characterization

4.4.3.2 Master Trigger Pulse Requirements

An SPC transmission is initiated by a master trigger pulse on the IFA pin. To detect a low-level on the IFA pin, the voltage must be below a threshold Vth. The sensor detects that the IFA line has been released as soon as Vth is crossed. Figure 4-16 shows the timing definitions for the master pulse. The master low time tmlow as well as the total trigger time tmtr are given in Table 4-22.

If the master low time exceeds the maximum low time, the sensor does not respond and is available for a next triggering 30 μs after the master pulse crosses Vthr. tmd,tot is the delay between internal triggering of the falling edge in the sensor and the triggering of the ECU.

Figure 4-16 SPC Master pulse timing

Table 4-22 Master pulse parameters

1. Not subject to production test - verified by design/characterization

2. Trigger time in the sensor is fixed to the number of units specified in the "typ." column, but the effective trigger time varies due to the sensor's clock variation

4.4.3.3 Checksum Nibble Details

The checksum nibble is a 4-bit CRC of the data nibbles including the status nibble. The CRC is calculated using a polynomial x⁴ +x3 +x² +1 with a seed value of 0101B. The remainder after the last data nibble is transmitted as CRC.

4.4.4 Hall Switch Mode (HSM)

The Hall Switch Mode (HSM) within the TLE5012B makes it possible to emulate the output of 3 Hall switches. Hall switches are often used in electrical commutated motors to determine the rotor position. With these 3 output signals, the motor will be commutated in the right way. Depending on which pole pairs of the rotor are used, various electrical periods have to be controlled. This is selectable within 0EH (HSM_PLP). Figure 4-17 depicts the three output signals with the relationship between electrical angle and mechanical angle. The mechanical 0° point is always used as reference.

The HSM is generally used with push-pull output, but it can be changed to open-drain within the register IFAB_OD. Sensors with preset HSM are available as TLE5012B E3005.

Figure 4-17 Hall Switch Mode

The HSM Interface can be selected via SSC (IF_MD = 010).

Table 4-23 Hall Switch Mode

Table 4-23 Hall Switch Mode (cont'd)

• Parameter Symbol Values Unit Note / Test Condition
• Min. Typ. Max.
• Electrical angle accuracy αelect 0.6 1 ° 1 pole pair with
  autocalibration1)2)
• 1.2 2 ° 2 pole pairs with autocal.1)2)
• 1.8 3 ° 3 pole pairs with autocal.1)2)
• 2.4 4 ° 4 pole pairs with autocal.1)2)
• 3.0 5 ° 5 pole pairs with autocal.1)2)
• 3.6 6 ° 6 pole pairs with autocal.1)2)
• 4.2 7 ° 7 pole pairs with autocal.1)2)
• 4.8 8 ° 8 pole pairs with autocal.1)2)
• 5.4 9 ° 9 pole pairs with autocal.1)2)
• 6.0 10 ° 10 pole pairs with
  autocal.1)2)
• 6.6 11 ° 11 pole pairs with
  autocal.1)2)
• 7.2 12 ° 12 pole pairs with
  autocal.1)2)
• 7.8 13 ° 13 pole pairs with
  autocal.1)2)
• 8.4 14 ° 14 pole pairs with
  autocal.1)2)
• 9.0 15 ° 15 pole pairs with
  autocal.1)2)
• 9.6 16 ° 16 pole pairs with
  autocal.1)2)
• Mechanical angle switching
  hysteresis αHShystm 0 0.703 ° Selectable by
  IFAB_HYST2)3)4)

Table 4-23 Hall Switch Mode (cont'd)

• Parameter Symbol Values Unit Note / Test Condition
• Min. Typ. Max.
• Electrical angle switching
  hysteresis5) αHShystel 0.70 °
• 1.41 °
• 2.11 °
• 2.81 °
• 3.52 °
• 4.22 °
• 4.92 °
• 5.62 °
• 6.33 °
• 7.03 °
• 7.73 °
• 8.44 °
• 9.14 °
• 9.84 °
• 10.55 °
• 11.25 °
• Fall time tHSfall 0.02 1 μs
• Rise time tHSrise 0.4 1 μs

1. Depends on internal oscillator frequency variation (Section 4.3.7)

2. Not subject to production test - verified by design/characterization

3. GMR hysteresis not considered

4. Minimum hysteresis without switching

5. The hysteresis has to be considered only at change of rotation direction

To avoid switching due to mechanical vibrations of the rotor, an artificial hysteresis is recommended (Figure 4-18).

Figure 4-18 HS hysteresis

4.4.5 Incremental Interface (IIF)

The Incremental Interface (IIF) emulates the operation of an optical quadrature encoder with a 50% duty cycle. It transmits a square pulse per angle step, where the width of the steps can be configured from 9bit (512 steps per full rotation) to 12bit (4096 steps per full rotation) within the register MOD_4 (IFAB_RES). The rotation direction is given either by the phase shift between the two channels IFA and IFB (A/B mode) or by the level of the IFB channel (Step/Direction mode), as shown in Figure 4-19 and Figure 4-20. The incremental interface can be configured for A/B mode or Step/Direction mode in register MOD_1 (IIF_MOD).

Using the Incremental Interface requires an up/down counter on the microcontroller, which counts the pulses and thus keeps track of the absolute position. The counter can be synchronized periodically by using the SSC interface in parallel. The angle value (AVAL register) read out by the SSC interface can be compared to the stored counter value. In case of a non-synchronization, the microcontroller adds the difference to the actual counter value to synchronize the TLE5012B with the microcontroller.

After startup, the IIF transmits a number of pulses which correspond to the actual absolute angle value. Thus, the microcontroller gets the information about the absolute position. The Index Signal that indicates the zero crossing is available on the IFC pin.

Sensors with preset IIF are available as TLE5012B E1000.

A/B Mode

The phase shift between phases A and B indicates either a clockwise (A follows B) or a counterclockwise (B follows A) rotation of the magnet.

Figure 4-19 Incremental interface with A/B mode

Step/Direction Mode

Phase A pulses out the increments and phase B indicates the direction.

Figure 4-20 Incremental interface with Step/Direction mode

Table 4-24 Incremental Interface

1) Not subject to production test - verified by design/characterization

4.5 Test Mechanisms

4.5.1 ADC Test Vectors

In order to test the correct functionality of the ADCs, the ADC inputs can be switched from the GMR bridge outputs to a chain of fixed resitors which act as a voltage divider. The ADCs are then fed with test vectors of fixed voltages to simulate a set of magnet positions. The functionality of the ADCs is verified by checking the angle value (AVAL register) for each test vector. This test is activated via SSC command within the SIL register (ADCTV_EN). Registers ADCTV_Y and ADCTV_X are used to select the test vector, as shown in Figure 4-21.

The following X/Y ADC values can be programmed:

• 4 points, circle amplitude = 70% (0°,90°, 180°, 270°)
• 8 points, circle amplitude = 100% (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°)
• 8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°)
• 4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°)

Note: The 100% values typically correspond to 21700 digits and the 70% values to 15500 digits.

• Min.
• 000
• 001
• 010
• 011
• 101

Table 4-25 ADC test vectors

Figure 4-21 ADC test vectors

4.6 Supply Monitoring

The internal voltage nodes of the TLE5012B are monitored by a set of comparators in order to ensure error-free operation. An over- or undervoltage condition must be active at least 256 periods of the digital clock to set the corresponding error bits in the Status register. This works as digital spike suppression.

Over- or undervoltage errors trigger the S_VR bit of Status register. This error condition is signaled via the in the Safety Word of the SSC protocol, the status nibble of the SPC interface or the lower diagnostic range of the PWM interface.

1. Not subject to production test - verified by design/characterization

4.6.1 Internal Supply Voltage Comparators

Every voltage regulator has an overvoltage (OV) comparator to detect malfunctions. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated.

4.6.2 VDD Overvoltage Detection

The overvoltage detection comparator monitors the external supply voltage at the VDD pin.

Figure 4-22 Overvoltage comparator

4.6.3 GND - Off Comparator

The GND - Off comparator is used to detect a voltage difference between the GND pin and SCK. This circuit can detect a disconnection of the supply GND Pin.

Figure 4-23 GND - off comparator

4.6.4 VDD - Off Comparator

The VDD - Off comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012B is supplied by the SCK and CSQ input pins via the ESD structures.

Figure 4-24 VDD - off comparator

Pre-Configured Derivates

Figure 6-1 PG-DSO-8 package dimension