Overview

Part: TCA9548A Texas Instruments

Type: Low-Voltage 8-Channel I2C Switch with Reset

Key Specs:

Operating power-supply voltage range: 1.65V to 5.5V
Clock frequency: 0 to 400kHz
Latch-up performance: exceeds 100mA Per JESD 78, class II
ESD Protection (Human-body model): ±2000V (A114-A)
ESD Protection (Machine model): 200V (A115-A)
ESD Protection (Charged-device model): ±1000V (C101)
Voltage-level translation: between 1.8V, 2.5V, 3.3V, and 5V buses
Inputs: 5-V Tolerant

Features:

1-to-8 Bidirectional translating switches
I2C Bus and SMBus compatible
Active-low reset input
Three address pins, allowing up to eight TCA9548A devices on the I2C bus
Channel selection through an I2C Bus, in any combination
Power up with all switch channels deselected
Low RON switches
No glitch on power up
Supports hot insertion
Low standby current

Applications:

Servers
Routers (telecom switching equipment)
Factory Automation
Products with I2C target address conflicts (such as multiple, identical temperature sensors)

Package:

PW (TSSOP, 24): 7.80mm × 4.40mm
RGE (VQFN, 24): 4.00mm × 4.00mm
DGS (VSSOP, 24): 6.10mm x 3.00mm

Features

1-to-8 Bidirectional translating switches
I ²C Bus and SMBus compatible
Active-low reset input
Three address pins, allowing up to eight TCA9548A devices on the I2C bus
Channel selection through an I2C Bus, in any combination
Power up with all switch channels deselected
Low RON switches
Allows voltage-level translation between 1.8V, 2.5V, 3.3V, and 5V buses
No glitch on power up
Supports hot insertion
Low standby current
Operating power-supply voltage range of 1.65V to 5.5V
5-V Tolerant inputs
0 to 400kHz Clock frequency
Latch-up performance exceeds 100mA Per JESD 78, class II
ESD Protection exceeds JESD 22
- ±2000V Human-body model (A114-A)
- 200V Machine model (A115-A)
- ±1000V Charged-device model (C101)

Applications

Servers
Routers (telecom switching equipment)
Factory Automation
Products with I2C target address conflicts (such as multiple, identical temperature sensors)

3 Description

The TCA9548A device has eight bidirectional translating switches that can be controlled through the I2C bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. These downstream channels can be used to resolve I2C target address conflicts. For example, if eight identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0-7.

The system controller can reset the TCA9548A in the event of a time-out, or other improper operation by asserting a low in the RESET input. Similarly, the power-on reset deselects all channels and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset and initialization to occur without powering down the part. This allows recovery if one of the downstream I2C buses get stuck in a low state.

The pass gates of the switches are constructed so that the VCC pin can be used to limit the maximum high voltage, which is passed by the TCA9548A. Limiting the maximum high voltage allows the use of different bus voltages on each pair, so that 1.8V, 2.5V or 3.3V parts can communicate with 5V parts, without any additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5V tolerant.

Packaging Information

| PART NUMBER | PACKAGE (1) | BODY SIZE (NOM) | |-------------|-----------------|-----------------|--| | | PW (TSSOP, 24) | 7.80mm × 4.40mm | | TCA9548A | RGE (VQFN, 24) | 4.00mm × 4.00mm | | | DGS (VSSOP, 24) | 6.10mm x 3.00mm | (1) For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application Diagram

Pin Configuration

Figure 4-2. RGE Package, 24-Pin VQFN (Top View)

Figure 4-1. PW, DGS Package, 24-Pin TSSOP, VSSOP (Top View)

Table 4-1. Pin Functions

| | PIN | |-------|---------------------------|--- | NAME | TSSOP, VSSOP
(PW, | A0 | 1 | 22 | A1 | 2 | 23 | A2 | 21 | 18 | GND | 12 | 9 | RESET | 3 | 24 | SD0 | 4 | 1 | SC0 | 5 | 2 | SD1 | 6 | 3 | SC1 | 7 | 4 | SD2 | 8 | 5 | SC2 | 9 | 6 | SD3 | 10 | 7 | SC3 | 11 | 8 | SD4 | 13 | 10 | SC4 | 14 | 11 | SD5 | 15 | 12 | SC5 | 16 | 13 | SD6 | 17 | 14 | SC6 | 18 | 15 | SD7 | 19 | 16 | SC7 | 20 | 17 | SCL | 22 | 19 | SDA | 23 | 20 | VCC | 24 | 21 ---------|-------|--------------------------------------------------------------------------------------------------------------------------------| DGS) | VQFN (RGE) | TYPE | DESCRIPTION | | I | Address input 0. Connect directly to V _CC or ground | | 1 | Address input 1. Connect directly to V _CC or ground | | 1 | Address input 2. Connect directly to V _CC or ground | | _ | Ground | | 1 | Active-low reset input. Connect to V _CC or V _DPUM ⁽¹⁾ through a pull-up resistor, if not used | | I/O | Serial data 0. Connect to V _DPU0 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 0. Connect to V _DPU0 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 1. Connect to V _DPU1 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 1. Connect to V _DPU1 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 2. Connect to V _DPU2 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 2. Connect to V _DPU2 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 3. Connect to V _DPU3 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 3. Connect to V _DPU3 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 4. Connect to V _DPU4 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 4. Connect to V _DPU4 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 5. Connect to V _DPU5 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 5. Connect to V _DPU5 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 6. Connect to V _DPU6 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 6. Connect to V _DPU6 ⁽¹⁾ through a pull-up resistor | | I/O | Serial data 7. Connect to V _DPU7 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock 7. Connect to V _DPU7 ⁽¹⁾ through a pull-up resistor | | I/O | Serial clock bus. Connect to V _DPUM ⁽¹⁾ through a pull-up resistor | | I/O | Serial data bus. Connect to V _DPUM ⁽¹⁾ through a pull-up resistor | | Power | Supply voltage |

⁽¹⁾ V_DPUX is the pull-up reference voltage for the associated data line. V_DPUM is the controller I²C reference voltage and V_DPU0-V_DPU7 are the target channel reference voltages.

Electrical Characteristics

$V_{CC}$ = 1.65 V to 5.5 V, over recommended operating free-air temperature ranges supported by Recommended Operating Conditions (unless otherwise noted) (1)

	PARAMETI	ER	TEST CONDITIONS	V _cc	MIN	TYP (2)	MAX	UNIT
V _PORR	Power-on reset vo	tage, V _CC rising	No load, V _I = V _CC or GND ⁽³⁾			1.2	1.5	V
V _PORF	Power-on reset vo	tage, V _CC falling ⁽⁴⁾	No load, V _I = V _CC or GND ⁽³⁾		0.8	1		V
				5 V		3.6
				4.5 V to 5.5 V	2.6		4.5
				3.3 V		1.9
.,			\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \	3 V to 3.6 V	1.6		2.8	.,
$V_{o(sw)}$	Switch output volta	ige	$V_{i(sw)} = V_{CC}$ , $I_{SWout} = -100 \mu A$	2.5 V		1.5		V
				2.3 V to 2.7 V	1.1		2
				1.8 V		1.1
				1.65 V to 1.95 V	0.6		1.25
	004		V _OL = 0.4 V	4.05.7/1 .5.5.7/	3	6		•
I _OL	SDA		V _OL = 0.6 V	1.65 V to 5.5 V	6	9		mA
	SCL, SDA				-1		1
	SC7-SC0, SD7-S	D0	OND(3)	4.05.77. 5.577	-1		1
I _I A2–A	A2-A0		$V_I = V_{CC} \text{ or } GND^{(3)}$	1.65 V to 5.5 V	-1		1	μA
	RESET				-1		1
				5.5 V		50	80
			0.15(2)	3.6 V		20	35
		f _SCL = 400 kHz	$V_I = V_{CC}$ or $GND^{(3)}$ , $I_O = 0$	2.7 V		11	20
				1.65 V		6	10
	Operating mode			5.5 V		9	30
			0.15(2)	3.6 V		6	15
		f _SCL = 100 kHz	$V_1 = V_{CC} \text{ or } GND^{(3)}, I_0 = 0$	2.7 V		4	8
				1.65 V		2	4
			puts $V_{\rm I} = {\rm GND^{(3)}}, \ {\rm I}_{\rm O} = 0, \ -40 \ ^{\circ}{\rm C} \le {\rm TA} \le 85 \ ^{\circ}{\rm C}$	5.5 V		0.2	2
I _CC				3.6 V		0.1	2
		Low inputs		2.7 V		0.1	1
				1.65 V		0.1	1
				5.5 V		0.2	2
	Standby mode	I link in make	V - V	3.6 V		0.1	2
		High inputs	$V_1 = V_{CC}, I_0 = 0, -40 \text{ °C} \le TA \le 85 \text{ °C}$	2.7 V		0.1	1
				1.65 V		0.1	1
				3.6 V		1	2	μA
		Low and High Inputs	Vi = Vcc or GND, lo = 0, 85 °C < TA ≤ 125 °C	2.7 V		0.7	1.5	μA
				1.65 V		0.4	1	μA
Δl _CC	Supply-current	SCL or SDA input at 0.6 V, Other inputs at V _CC or GND ⁽³⁾		1.65 V to 5.5 V		3	20	^
DICC	change	SCL, SDA	SCL or SDA input at $V_{CC} - 0.6 \text{ V}$ , Other inputs at $V_{CC}$ or $\text{GND}^{(3)}$	1.03 V to 3.3 V		3	20	μA
	A2-A0		$V_{I} = V_{CC}$ or $GND^{(3)}$			4	5
C _i	RESET		AT = ACC OL CLADA	1.65 V to 5.5 V		4	5	4 '
	SCL		V _I = V _CC or GND ⁽³⁾ , Switch OFF			20	28
C (5)	SDA		$V_{I} = V_{CC}$ or $GND^{(3)}$ , Switch OFF	1 65 V to 5 5 V		20	28	pF
C _io(off) (5)	SC7-SC0, SD7-S	D0	VI - VCC OF GIND (-7, SWITCH OFF	1.65 V to 5.5 V		5.5	7.5	þΓ

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VCC = 1.65 V to 5.5 V, over recommended operating free-air temperature ranges supported by Recommended Operating Conditions (unless otherwise noted) (1)

PARAMETER	TEST CONDITIONS	VCC	MIN	TYP (2)	MAX	UNIT
	VO = 0.4 V, IO = 15 mA	4.5 V to 5.5 V	4	10	20
RON Switch-on resistance		3 V to 3.6 V	5	12	30
	VO = 0.4 V, IO = 10 mA	2.3 V to 2.7 V	7	15	45	Ω
		1.65 V to 1.95 V	10	25	70

(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges
(2) All typical values are at nominal supply voltage (1.8-, 2.5-,3.3-, or 5-V VCC), TA = 25°C
(3) RESET = VCC (held high) when all other input voltages, V^I = GND.
(4) The power-on reset circuit resets the I2C bus logic with VCC < VPORF
(5) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.

5.6 I ²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)

			MIN	MAX	UNIT
STANDARD MODE
fscl	2C clock frequency I		0	100	kHz
tsch	2C clock high time I		4		μs
tscl	2C clock low time I		4.7		μs
tsp	2C spike time I			50	ns
tsds	2C serial-data setup time I		250		ns
tsdh	2C serial-data hold time I		(1) 0		μs
ticr	2C input rise time I			1000	ns
ticf	2C input fall time I			300	ns
tocf	2C output (SDn) fall time (10-pF to 400-pF bus) I			300	ns
tbuf	2C bus free time between stop and start I		4.7		μs
tsts	2C start or repeated start condition setup I		4.7		μs
tsth	2C start or repeated start condition hold I		4		μs
tsps	2C stop condition setup I		4		μs
tvdL(Data)	Valid-data time (high to low)(2)	SCL low to SDA output low valid		1	μs
tvdH(Data)	Valid-data time (low to high)(2)	SCL low to SDA output high valid		0.6	μs
tvd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		1	μs
Cb	2C bus capacitive load I			400	pF
FAST MODE
fscl	2C clock frequency I		0	400	kHz
tsch	2C clock high time I		0.6		μs
tscl	2C clock low time I		1.3		μs
tsp	2C spike time I			50	ns
tsds	2C serial-data setup time I		100		ns
tsdh	2C serial-data hold time I		(1) 0		μs
ticr	2C input rise time I		20 + 0.1Cb (3)	300	ns
ticf	2C input fall time I		20 + 0.1Cb (3)	300	ns
tocf	2C output (SDn) fall time (10-pF to 400-pF bus) I		20 + 0.1Cb (3)	300	ns
tbuf	2C bus free time between stop and start I		1.3		μs
tsts	2C start or repeated start condition setup I		0.6		μs
tsth	2C start or repeated start condition hold I		0.6		μs
tsps	2C stop condition setup I		0.6		μs
tvdL(Data)	Valid-data time (high to low)(2)	SCL low to SDA output low valid		1	μs
tvdH(Data)	Valid-data time (low to high)(2)	SCL low to SDA output high valid		0.6	μs
tvd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		1	μs

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)

		MIN	MAX	UNIT
Cb	2C bus capacitive load I		400	pF

(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩ pull-up resistor and 50-pF load.
(3) Cb = total bus capacitance of one bus line in pF.

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

			MIN	MAX	UNIT
VCC	Supply voltage		–0.5	7	V
VI	Input voltage(2)		–0.5	7	V
II	Input current				mA
IO	Output current		–25		mA
ICC	Supply current		–100	100	mA
Tstg	Storage temperature		–65	150	°C
TJ		VCC ≤ 3.6 V		130
TJ	Max Junction Temperature	VCC ≤ 5.5 V		90	℃

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

Recommended Operating Conditions

			MIN	MAX	UNIT
	Supply voltage	-40 ℃ ≤ TA ≤ 85 ℃	1.65	5.5	V
	VCC	85 ℃ < TA ≤ 125 ℃	1.65	3.6
	VIH High-level input voltage	SCL, SDA	0.7 × VCC	6
		A2–A0, RESET	0.7 × VCC	VCC + 0.5	V
		SCL, SDA	–0.5	0.3 × VCC
VIL	Low-level input voltage	A2–A0, RESET	–0.5	0.3 × VCC	V
		3.6 V < VCC ≤ 5.5 V	–40	85
TA	Operating free-air temperature	1.65 V ≤ VCC ≤ 3.6 V	–40	125	°C

Thermal Information

| | | | TCA9548A | |-----------|----------------------------------------------|------------|------------|-------------|------|--| | | THERMAL METRIC(1) | PW (TSSOP) | RGE (VQFN) | DGS (VSSOP) | UNIT | | | | 24 PINS | 24 PINS | 24 PINS | | RθJA | Junction-to-ambient thermal resistance | 108.8 | 57.2 | 86.1 | °C/W | | RθJC(top) | Junction-to-case (top) thermal resistance | 54.1 | 62.5 | 34.3 | °C/W | | RθJB | Junction-to-board thermal resistance | 62.7 | 34.4 | 47.3 | °C/W | | ψJT | Junction-to-top characterization parameter | 10.9 | 3.8 | 1.5 | °C/W | | ψJB | Junction-to-board characterization parameter | 62.3 | 34.4 | 47.0 | °C/W | | RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | 15.5 | N/A | °C/W | ⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

TCA9548A