Si5351A-B-GTR

Manufacturer

Skyworks Solutions Inc.

Category

Integrated Circuits (ICs)

Package

10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Lifecycle

Active

Overview

Part: Si5351 from Skyworks Solutions, Inc.

Type: I2C-Programmable Any-Frequency CMOS Clock Generator + VCXO

Key Specs:

  • Output frequency range: 2.5 kHz to 200 MHz
  • Frequency error: 0 ppm
  • Output period jitter: < 70 ps pp, typ
  • Crystal frequency: 25 or 27 MHz
  • Core VDD: 2.5 or 3.3 V
  • Output VDDO: 1.8, 2.5, or 3.3 V
  • CLKIN frequency: 10 to 100 MHz

Features:

  • Generates up to eight non-integer related frequencies
  • I2C user definable configuration
  • Exact frequency synthesis at each output (0 ppm error)
  • Highly linear VCXO
  • Optional clock input (CLKIN)
  • Low output period jitter: < 70 ps pp, typ
  • Configurable spread spectrum selectable at each output
  • Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz
  • Supports static phase offset
  • Programmable rise/fall time control
  • Power supply filtering
  • Very low power consumption
  • Adjustable output delay
  • Glitchless frequency changes
  • Separate voltage supply pins provide level translation
  • PCIE Gen 1 compatible
  • Supports HCSL compatible swing

Applications:

  • Audio/video equipment, gaming
  • Printers, scanners, projectors
  • Handheld Instrumentation
  • Laser range finder
  • Residential gateways
  • Networking/communication
  • Servers, storage
  • XO replacement

Package:

  • 10-MSOP: 3 outputs
  • 16-QFN (3x3 mm): 4 outputs
  • 20-QFN (4x4 mm): 8 outputs

Features

  • https://www.skyworksinc.com/Products/Timi ng/CMOS-Clock-Generators
  • Generates up to eight non-integerrelated frequencies from 2.5 kHz to 200 MHz
  • I 2C user definable configuration
  • Exact frequency synthesis at each output (0 ppm error)
  • Highly linear VCXO
  • Optional clock input (CLKIN)
  • Low output period jitter: < 70 ps pp, typ
  • Configurable spread spectrum selectable at each output
  • Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz
  • Supports static phase offset
  • Programmable rise/fall time control

Applications

  • Audio/video equipment, gaming
  • Printers, scanners, projectors
  • Handheld Instrumentation
  • Laser range finder

Pin Configuration

10.1. Si5351A 20-pin QFN

Figure 17. Si5351A 20-QFN Top View

Table 14. Si5351A Pin Descriptions

Pin NamePin NumberPin Type1Function
XA1IInput pin for external crystal.
XB2IInput pin for external crystal.
CLK013OOutput clock 0.
CLK112OOutput clock 1.
CLK29OOutput clock 2.
CLK38OOutput clock 3.
CLK419OOutput clock 4.
CLK517OOutput clock 5.
CLK616OOutput clock 6.
CLK715OOutput clock 7.
A03II2C address bit.
SCL4II2C bus serial clock input. Pull-up to VDD core with 1 kΩ.
SDA5I/OI2C bus serial data input. Pull-up to VDD core with 1 kΩ.
SSEN6ISpread spectrum enable. High = enabled, Low = disabled.
OEB7IOutput driver enable. Low = enabled, High = disabled.
VDD20PCore voltage supply pin. See 7.2.
VDDOA11POutput voltage supply pin for CLK0 and CLK1. See 7.2.
VDDOB10POutput voltage supply pin for CLK2 and CLK3. See 7.2.
VDDOC18POutput voltage supply pin for CLK4 and CLK5. See 7.2.
VDDOD14POutput voltage supply pin for CLK6 and CLK7. See 7.2.
GNDCenter PadPGround. Use multiple vias to ensure a solid path to GND.

10.2. Si5351B 20-Pin QFN

Pin NamePin NumberPin Type¹Function
XA1IInput pin for external crystal
XB2IInput pin for external crystal
CLK013OOutput clock 0
CLK112OOutput clock 1
CLK29OOutput clock 2
CLK38OOutput clock 3
CLK419OOutput clock 4
CLK517OOutput clock 5
CLK616OOutput clock 6
CLK715OOutput clock 7
VC3IVCXO control voltage input
SCL4II²C bus serial clock input. Pull-up to VDD core with 1 kΩ.
SDA5I/OI²C bus serial data input. Pull-up to VDD core with 1 kΩ.
SSEN6ISpread spectrum enable. High = enabled, Low = disabled.
OEB7IOutput driver enable. Low = enabled, High = disabled.
VDD20PCore voltage supply pin
VDDOA11POutput voltage supply pin for CLK0 and CLK1. See 7.2
VDDOB10POutput voltage supply pin for CLK2 and CLK3. See 7.2
VDDOC18POutput voltage supply pin for CLK4 and CLK5. See 7.2
VDDOD14POutput voltage supply pin for CLK6 and CLK7. See 7.2
GNDCenter PadPGround

Pin NamePin NumberPin Type1Function
XA1IInput pin for external crystal
XB2IInput pin for external crystal
CLK013OOutput clock 0
CLK112OOutput clock 1
CLK29OOutput clock 2
CLK38OOutput clock 3
CLK419OOutput clock 4
CLK517OOutput clock 5
CLK616OOutput clock 6
CLK715OOutput clock 7
VC3IVCXO control voltage input
SCL4II2C bus serial clock input. Pull-up to VDD core with 1 kΩ.
SDA5I/OI2C bus serial data input. Pull-up to VDD core with 1 kΩ.
SSEN6ISpread spectrum enable. High = enabled, Low = disabled.
OEB7IOutput driver enable. Low = enabled, High = disabled.
VDD20PCore voltage supply pin
VDDOA11POutput voltage supply pin for CLK0 and CLK1. See 7.2
VDDOB10POutput voltage supply pin for CLK2 and CLK3. See 7.2
VDDOC18POutput voltage supply pin for CLK4 and CLK5. See 7.2
VDDOD14POutput voltage supply pin for CLK6 and CLK7. See 7.2
GNDCenter PadPGround

10.3. Si5351C 20-Pin QFN

Table 16. Si5351C Pin Descriptions

Pin NamePin NumberPin Type1
20-QFN
XA1I
XB2I
CLK013O
CLK112O
CLK29O
CLK38O
CLK419O
CLK517O
CLK616O
CLK715O
INTR3O
SCL4I
SDA5I/O
CLKIN6I
OEB7I
VDD20P
VDDOA11P
VDDOB10P
VDDOC18P
VDDOD14P
GNDCenter PadP

10.4. Si5351A 16-Pin QFN

Pin NamePin NumberPin Type¹Function
Pin NamePin NumberPin Type1Function
XA1IInput pin for external crystal.
XB2IInput pin for external crystal.
CLK010OOutput Clock 0.
CLK17OOutput Clock 1.
CLK213OOutput Clock 2.
CLK312OOutput Clock 3.
A03II²C address bit.
SCL4II²C bus serial clock input. Pull-up to VDD core with 1 kΩ.
SDA5I/OI²C bus serial data input. Pull-up to VDD core with 1 kΩ.
OEB6IOutput driver enable. Low = Enabled; High = Disabled.
VDD16PCore voltage supply pin. See "7.2. Power Supply Sequencing"
VDDOA9POutput voltage supply pin for CLK0. See "7.2. Power Supply Sequencing".
VDDOB8POutput voltage supply pin for CLK1. See "7.2. Power Supply Sequencing".
VDDOC14POutput voltage supply pin for CLK2. See "7.2. Power Supply Sequencing".
VDDOD11POutput voltage supply pin for CLK3. See "7.2. Power Supply Sequencing".
GND15GNDGround.
GND PADCenter PadGNDGround pad. Use multiple vias to ensure a solid path to Ground.
Notes:
1.
I = Input, O = Output, P= Power, GND = Ground Input pins are not internally pulled up.

10.5. Si5351B 16-Pin QFN

Table 18. Si5351B Pin Descriptions

Pin NamePin NumberPin Type1Function
XA1IInput pin for external crystal.
XB2IInput pin for external crystal.
CLK010OOutput Clock 0.
CLK17OOutput Clock 1.
CLK213OOutput Clock 2.
CLK312OOutput Clock 3.
VC3IVCXO control voltage input
SCL4II2C bus serial clock input. Pull-up to VDD core with 1 kΩ.
SDA5I/OI2C bus serial data input. Pull-up to VDD core with 1 kΩ.
OEB6IOutput driver enable. Low = Enabled; High = Disabled.
VDD16PCore voltage supply pin. See "7.2. Power Supply Sequencing"
VDDOA9POutput voltage supply pin for CLK0. See "7.2. Power Supply Sequencing" .
VDDOB8POutput voltage supply pin for CLK1. See "7.2. Power Supply Sequencing" .
VDDOC14POutput voltage supply pin for CLK2. See "7.2. Power Supply Sequencing" .
VDDOD11POutput voltage supply pin for CLK3. See "7.2. Power Supply Sequencing" .
GND15GNDGround.
GND PADCenter PadGNDGround pad. Use multiple vias to ensure a solid path to Ground

10.6. Si5351C 16-Pin QFN

Figure 22. Si5351C 16-QFN Top View

Table 19. Si5351C Pin Descriptions

Pin NamePin NumberPin Type1Function
XA1IInput pin for external crystal.
XB2IInput pin for external crystal.
CLK010OOutput Clock 0.
CLK17OOutput Clock 1.
CLK213OOutput Clock 2.
CLK312OOutput Clock 3.
CLKIN6IPLL clock input
SCL4II²C bus serial clock input. Pull-up to VDD core with 1 kΩ.
SDA5I/OI²C bus serial data input. Pull-up to VDD core with 1 kΩ.
OEB3IOutput driver enable. Low = Enabled; High = Disabled.
VDD16PCore voltage supply pin. See "7.2. Power Supply Sequencing"
VDDOA9POutput voltage supply pin for CLK0. See "7.2. Power Supply Sequencing"
VDDOB8POutput voltage supply pin for CLK1. See "7.2. Power Supply Sequencing"
VDDOC14POutput voltage supply pin for CLK2. See "7.2. Power Supply Sequencing"
VDDOD11POutput voltage supply pin for CLK3. See "7.2. Power Supply Sequencing"
GND15GNDGround.
GND PADCenter PadGNDGround pad. Use multiple vias to ensure a solid path to Ground.
Notes:
1.		I = Input, O = Output, P= Power, GND = Ground Input pins are not internally pulled up.

32 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021

10.7. Si5351A 10-Pin MSOP

Table 20. Si5351A 10-MSOP Pin Descriptions

Pin NamePin
Number
10-MSOP		Pin Type*Function
XA2IInput pin for external crystal.
XB3IInput pin for external crystal.
CLK010OOutput clock 0.
CLK19OOutput clock 1.
CLK26OOutput clock 2.
SCL4ISerial clock input for the I²C bus. This pin must be pulled-up using a pull-up resistor of at least 1 kΩ.
SDA5I/OSerial data input for the I²C bus. This pin must be pulled-up using a pull-up resistor of at least 1 kΩ.
VDD1PCore voltage supply pin.
VDDO7POutput voltage supply pin for CLK0, CLK1, and CLK2. See "7.2. Power Supply Sequencing" on page 25.
GND8PGround.

Electrical Characteristics

Table 3. Recommended Operating Conditions

ParameterSymbolTest ConditionMinTypMaxUnit
Ambient TemperatureTA–402585°C
Core Supply VoltageVDD3.03.33.60V
Core Supply VoltageVDD2.252.52.75V
Core Supply VoltageVDD1.711.81.89V
Output Buffer VoltageVDDOx2.252.52.75V
Output Buffer VoltageVDDOx3.03.33.60V

**Notes:**All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD and VDDOx can be operated at independent voltages.

Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same time as VDD.

Table 4. DC Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

ParameterSymbolTest ConditionMinTypMaxUnit
Core Supply CurrentIDDEnabled 3 outputs—2235mA
Enabled 4 outputs—2438mA
Enabled 8 outputs—2745mA
Output Buffer Supply Current
(Per Output)*		IDDOxCL
= 5 pF		—2.25.6mA
Input CurrentICLKINCLKIN, SDA, SCL
Vin < 3.6 V		——10μA
IVCVC——30μA
Output ImpedanceZO3.3 V VDDO, default high
drive		—50—
*Note: Output clocks less than or equal to 100 MHz.

Table 5. AC Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

ParameterSymbolTest ConditionMinTypMaxUnit
Power-up TimeTRDYFrom VDD
= VDDmin to valid
output clock, CL
= 5 pF,
fCLKn
> 1 MHz		210ms
Power-up Time, PLL Bypass
Mode		TBYPFrom VDD
= VDDmin to valid
output clock, CL
= 5 pF,
fCLKn
> 1 MHz		0.51ms
Output Enable TimeTOEFrom OEB pulled low to valid
clock output, CL
= 5 pF,
fCLKn
> 1 MHz		——10μs
Output Frequency Transition
Time		TFREQfCLKn
> 1 MHz		——10μs
Output Phase OffsetPSTEP—333—ps/step
Spread Spectrum Frequency
Deviation		SSDEVDown spread. Selectable in 0.1%
steps.		–0.1—–2.5%
Center spread. Selectable in
0.1% steps.		±0.1—±1.5%
Spread Spectrum Modulation
Rate		SSMOD3031.533kHz
VCXO Specifications (Si5351B Only)
VCXO Control Voltage RangeVc0VDD/2VDDV
VCXO Gain (configurable)KvVc = 10–90% of VDD, VDD = 3.3 V18—150ppm/V
VCXO Control Voltage LinearityKVLVc = 10–90% of VDD–5—+5%
VCXO Pull Range
(configurable)		PRVDD = 3.3 V*±300±240ppm
VCXO Modulation Bandwidth—10—kHz
*Note: Contact Skyworks Solutions for 2.5 V VCXO operation.

Table 6. Input Clock Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

ParameterSymbolTest ConditionMinTypMaxUnit
Crystal FrequencyfXTAL25—27MHz
CLKIN Input Low VoltageVIL–0.1—0.3 x VDDV
CLKIN Input High VoltageVIH0.7 x VDD—3.60V
CLKIN Frequency RangefCLKIN10—100MHz

Table 7. Output Clock Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

ParameterSymbolTest ConditionMinTypMaxUnit
Frequency Range1FCLK0.0025—200MHz
Load CapacitanceCL——15pF
DCFCLK < 160 MHz, Measured
at VDD/2		455055%
Duty CycleFCLK > 160 MHz, Measured
at VDD/2		405060%
tr20%–80%, CL
= 5 pF,		—11.5ns
Rise/Fall TimetfDefault high drive strength—11.5ns
Output High VoltageVOHVDD – 0.6——V
Output Low VoltageVOLCL
= 5 pF		——0.6V
Period Jitter2,3JPER16, 20-QFN, 4 outputs run
ning, 1 per VDDO		—4095ps, pk-pk
10-MSOP or 20-QFN,
all outputs running		—70155ps, pk-pk
Cycle-to-Cycle Jitter2,3JCC16, 20-QFN, 4 outputs run
ning, 1 per VDDO		—5090ps, pk
10-MSOP or 20-QFN,
all outputs running		—70150ps, pk
Period Jitter VCXO2,3JPER_VCXO16, 20-QFN, 4 outputs run
ning, 1 per VDDO		—5095ps, pk-pk
10-MSOP or 20-QFN,
all outputs running		—70155ps, pk-pk
Cycle-to-Cycle Jitter
VCXO2,3		16, 20-QFN, 4 outputs run
ning, 1 per VDDO		—5090ps, pk
JCC_VCXO10-MSOP or 20-QFN,
all outputs running		—70150ps, pk

Notes:

1. Only two unique frequencies above 112.5 MHz can be simultaneously output.

2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50 output impedance).

3. Jitter is highly dependent on device frequency configuration. Specifications represent a "worst case, real world" frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock outputs of 74.25, 24.576, and 48 MHz. Eight-output 20-QFN package measured with clock outputs of 33.333, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz. Four-output 16-QFN package measured with clock outputs of 33.333, 27, 28.322, and 48 MHz.

10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021

Table 8. Crystal Requirements1,2

ParameterSymbolTest ConditionMinTypMaxUnit
Crystal FrequencyfXTAL25—27MHz
CLKIN Input Low VoltageVIL-0.1—0.3 x VDDV
CLKIN Input High VoltageVIH0.7 x VDD—3.60V
CLKIN Frequency RangefCLKIN10—100MHz

Notes:

1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device's internal load capacitance for optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF capacitors on XA and XB).

2. Refer to "AN551: Crystal Selection Guide" for more details.

Table 9. I2C Specifications (SCL,SDA)1

ParameterSymbolTest ConditionStandard Mode
100 kbps		Fast Mode
400 kbps		Unit
MinMaxMinMax
LOW Level
Input Voltage		VILI2C–0.50.3 x VDDI2C–0.50.3 x VDDI2C²V
HIGH Level
Input Voltage		VIHI2C0.7 x VDDI2C3.60.7 x VDDI2C²3.6V
Hysteresis of
Schmitt Trigger
Inputs		VHYS——0.1—V
LOW Level
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current		VOLI2C²VDDI2C² = 2.5/3.3 V00.400.4V
Input CurrentIII2C–1010–1010μA
Capacitance for
Each I/O Pin		CII2CVIN = –0.1 to VDDI2C—4—4pF
I²C Bus
Timeout		TTOTimeout Enabled25352535ms

1. Refer to NXP's UM10204 I2C-bus specification and user manual, revision 03.

2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.

Table 10. Thermal Characteristics (2-Layer Board)
-----------------------------------------------------
ParameterSymbolTest ConditionPackageValueUnit
Thermal Resistance
Junction to Ambient		θJAStill Air¹10-MSOP150°C/W
16-QFN103°C/W
20-QFN74.9°C/W
Thermal Resistance
Junction to Board		ΨJBStill Air¹10-MSOP82°C/W
16-QFN37°C/W

Table 11. Thermal Characteristics (4-Layer Board)

ParameterSymbolTest ConditionPackageValueUnit
Thermal Resistance
Junction to Ambient		θJAStill Air¹10-MSOP126°C/W
16-QFN65°C/W
20-QFN41°C/W
Thermal Resistance
Junction to Board		θJBJunction to Board²10-MSOP84°C/W
16
1. Based on environment and board designed per JESD51-2A, JESD51-5, and JESD51-7.

2. Based on conditions set in JESD51-8.

ParameterSymbolTest ConditionPackageValueUnit
Thermal Resistance
Junction to Case1		θJCStill Air10-MSOP36°C/W
16-QFN82°C/W
20-QFN51°C/W
Notes:
1. Based on board designed per JESD51-1 (Top center of packages used).

Table 13. Absolute Maximum Ratings1

ParameterSymbolTest ConditionValueUnit
DC Supply VoltageVDD_max–0.5 to 3.8V
Input VoltageVIN_CLKINCLKIN, SCL, SDA–0.5 to 3.8V
VIN_VCVC–0.5 to (VDD+0.3)V
VIN_XA/BPins XA, XB–0.5 to 1.3 VV
Junction TemperatureTJ–55 to 150°C
Soldering Temperature
(Pb-free profile)2		TPEAK260°C
Soldering Temperature Time at
TPEAK (Pb-free profile)2		TP20–40Sec

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020.

Absolute Maximum Ratings

ParameterSymbolTest ConditionValueUnit
DC Supply VoltageVDD_max–0.5 to 3.8V
Input VoltageVIN_CLKINCLKIN, SCL, SDA–0.5 to 3.8V
VIN_VCVC–0.5 to (VDD+0.3)V
VIN_XA/BPins XA, XB–0.5 to 1.3 VV
Junction TemperatureTJ–55 to 150°C
Soldering Temperature
(Pb-free profile)2		TPEAK260°C
Soldering Temperature Time at
TPEAK (Pb-free profile)2		TP20–40Sec

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020.

Recommended Operating Conditions

ParameterSymbolTest ConditionMinTypMaxUnit
Ambient TemperatureTA–402585°C
Core Supply VoltageVDD3.03.33.60V
Core Supply VoltageVDD2.252.52.75V
Core Supply VoltageVDD1.711.81.89V
Output Buffer VoltageVDDOx2.252.52.75V
Output Buffer VoltageVDDOx3.03.33.60V

**Notes:**All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD and VDDOx can be operated at independent voltages.

Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same time as VDD.

Thermal Information

ParameterSymbolTest ConditionPackageValueUnit
Thermal Resistance
Junction to Ambient		θJAStill Air¹10-MSOP126°C/W
16-QFN65°C/W
20-QFN41°C/W
Thermal Resistance
Junction to Board		θJBJunction to Board²10-MSOP84°C/W
16
1. Based on environment and board designed per JESD51-2A, JESD51-5, and JESD51-7.

2. Based on conditions set in JESD51-8.

ParameterSymbolTest ConditionPackageValueUnit
Thermal Resistance
Junction to Case1		θJCStill Air10-MSOP36°C/W
16-QFN82°C/W
20-QFN51°C/W
Notes:
1. Based on board designed per JESD51-1 (Top center of packages used).

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
SI5351Skyworks Solutions Inc.—
SI535120Skyworks Solutions Inc.—
SI5351ASkyworks Solutions Inc.—
SI5351A-B-GMSkyworks Solutions Inc.—
SI5351A-B-GM1Skyworks Solutions Inc.—
SI5351A-B-GTSkyworks Solutions Inc.—
SI5351A/BSkyworks Solutions Inc.—
SI5351A/B/CSkyworks Solutions Inc.—
SI5351A/B/C-BSkyworks Solutions Inc.—
SI5351BSkyworks Solutions Inc.—
SI5351B-B-GMSkyworks Solutions Inc.—
SI5351B-B-GM1Skyworks Solutions Inc.—
SI5351CSkyworks Solutions Inc.—
SI5351C-B-GMSkyworks Solutions Inc.—
SI5351C-B-GM1Skyworks Solutions Inc.—
SI5351XSkyworks Solutions Inc.—
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