STM32U585XX
Ultra-low-power Arm Cortex-M33 32-bit MCUThe STM32U585XX is a ultra-low-power arm cortex-m33 32-bit mcu from STMicroelectronics. View the full STM32U585XX datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Category
Ultra-low-power Arm Cortex-M33 32-bit MCU
Key Specifications
| Parameter | Value |
|---|---|
| Connectivity | CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG |
| Core Processor | ARM® Cortex®-M33 |
| Core Size | 32-Bit |
| Data Converters | A/D 24x12/14b SAR; D/A 2x12b |
| Mounting Type | Surface Mount |
| Number of I/O | 136 |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Oscillator Type | External, Internal |
| Oscillator Type | External, Internal |
| Oscillator Type | External, Internal |
| Oscillator Type | External, Internal |
| Package / Case | 169-UFBGA |
| Peripherals | Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT |
| Flash Memory Size | 2MB (2M x 8) |
| Program Memory Type | FLASH |
| RAM Size | 784K x 8 B |
| Clock Speed | 160MHz |
| Supplier Device Package | 169-UFBGA (7x7) |
| Supplier Device Package | 169-UFBGA (7x7) |
| Supplier Device Package | 169-UFBGA (7x7) |
| Supplier Device Package | 169-UFBGA (7x7) |
| Supply Voltage | 1.71V ~ 3.6V |
Overview
Part: STM32U585xx — STMicroelectronics
Type: Ultra-low-power Arm Cortex-M33 32-bit MCU
Description: Ultra-low-power Arm Cortex-M33 32-bit MCU with TrustZone and FPU, offering up to 2 MB Flash memory, 786 KB SRAM, and advanced cryptographic features, achieving 240 DMIPS at up to 160 MHz.
Operating Conditions:
- Supply voltage: 1.71 V to 3.6 V
- Operating temperature: -40 °C to +85/125 °C (suffix-dependent — see Table N for grade-specific ranges)
- Max CPU frequency: 160 MHz
Absolute Maximum Ratings:
- Max supply voltage: 4.0 V (VDD, VDDA, VDDIO2, VDDUSB, VDDSDMMC, VDD_SMPS)
- Max junction/storage temperature: 150 °C
Key Specs:
- Flash memory: 2 MB with ECC
- SRAM: 786 KB with ECC OFF or 722 KB with ECC ON
- Run mode current: 19.5 μA/MHz @ 3.3 V
- Stop 3 mode current (full SRAM): 4.3 μA
- Standby mode current (RTC): 530 nA
- Shutdown mode current: 160 nA
- ADC1 resolution: 14-bit
- ADC1 sampling rate: 2.5 Msps
- DAC resolution: 12-bit
Features:
- Arm TrustZone and securable I/Os, memories, and peripherals
- Embedded regulator (LDO) and SMPS step-down converter
- 2 AES coprocessors, Public key accelerator, HASH hardware accelerator, True random number generator
- 2 Octo-SPI memory interfaces
- Up to 136 fast I/Os, most 5V-tolerant
- Up to 17 timers and 2 watchdogs
- 1 USB Type-C /USB power delivery controller, 1 USB OTG 2.0 full-speed controller
- 4 I2C FM+, 6 U(S)ART, 3 SPI, 1 CAN FD controller, 2 SDMMC interfaces
- Chrom-ART Accelerator (DMA2D) for graphic content
- CORDIC and FMAC mathematical coprocessors
- Up to 22 capacitive sensing channels
- 14-bit ADC, 12-bit ADC, 2 12-bit DAC, 2 operational amplifiers, 2 ultra-low-power comparators
Applications:
Package:
- LQFP48 (7 x 7 mm)
- LQFP64 (10 x 10 mm)
- LQFP100 (14 x 14 mm)
- LQFP144 (20 x 20 mm)
- UFQFPN48 (7 x 7 mm)
- WLCSP90 (4.2 x 3.95 mm)
- UFBGA132 (7 x 7 mm)
- UFBGA169 (7 x 7 mm)
Features
- Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
- 1 digital camera interface
Pin Configuration
STM32U585XX LQFP48_SMPS Pinout
| Pin Number | Pin Name | Type | Description |
|---|---|---|---|
| 1 | VBAT | P | Battery voltage supply |
| 2 | PC13 | I/O | Port C, bit 13 |
| 3 | PC14-OSC32_IN | I/O | Port C, bit 14 / 32 kHz oscillator input |
| 4 | PC15-OSC32_OUT | I/O | Port C, bit 15 / 32 kHz oscillator output |
| 5 | PH0-OSC_IN | I/O | Port H, bit 0 / Main oscillator input |
| 6 | PH1-OSC_OUT | I/O | Port H, bit 1 / Main oscillator output |
| 7 | NRST | I | Reset pin (active low) |
| 8 | VSSA | P | Ground (analog) |
| 9 | VDDA | P | Analog power supply |
| 10 | PA0 | I/O | Port A, bit 0 |
| 11 | PA1 | I/O | Port A, bit 1 |
| 12 | PA2 | I/O | Port A, bit 2 |
| 13 | PA3 | I/O | Port A, bit 3 |
| 14 | PA4 | I/O | Port A, bit 4 |
| 15 | PA5 | I/O | Port A, bit 5 |
| 16 | PA6 | I/O | Port A, bit 6 |
| 17 | PA7 | I/O | Port A, bit 7 |
| 18 | PB0 | I/O | Port B, bit 0 |
| 19 | PB1 | I/O | Port B, bit 1 |
| 20 | VDD/SMPS_PS | P | Digital power supply / SMPS power switch |
| 21 | VDDSMPS | P | SMPS output voltage |
| 22 | VDDSMPS | P | SMPS output voltage |
| 23 | VDD1 | P | Digital power supply |
| 24 | VSS | P | Ground |
| 25 | VDD | P | Digital power supply |
| 26 | PB13 | I/O | Port B, bit 13 |
| 27 | PB14 | I/O | Port B, bit 14 |
| 28 | PB15 | I/O | Port B, bit 15 |
| 29 | PA8 | I/O | Port A, bit 8 |
| 30 | PA9 | I/O | Port A, bit 9 |
| 31 | PA10 | I/O | Port A, bit 10 |
| 32 | PA11 | I/O | Port A, bit 11 |
| 33 | PA12 | I/O | Port A, bit 12 |
| 34 | PA13 | I/O | Port A, bit 13 |
| 35 | VSS | P | Ground |
| 36 | VDD | P | Digital power supply |
Notes
- This is the LQFP48_SMPS package variant of the STM32U585XX.
- Pins 20–23 are SMPS (Switched-Mode Power Supply) related pins specific to this variant.
- PC14-OSC32_IN, PC15-OSC32_OUT, PH0-OSC_IN, and PH1-OSC_OUT support alternate oscillator functions.
- NRST (pin 7) is the active-low reset input.
- Multiple VDD, VSS, VDDA, and VSSA pins provide distributed power and ground connections.
Electrical Characteristics
The definition and values of output AC characteristics are given in Figure 37: Output AC characteristics definition and in the table below respectively.
Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 33 .
Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4)
| Speed | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| 00 | Fmax | Maximum frequency all I/Os | C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 12.5 | MHz |
| 00 | Fmax | Maximum frequency all I/Os | C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 5 | MHz |
| 00 | Fmax | Maximum frequency all I/Os | C L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 1 | MHz |
| 00 | Fmax | Maximum frequency all I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 12.5 | MHz |
| 00 | Fmax | Maximum frequency all I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 5 | MHz |
| 00 | Fmax | Maximum frequency all I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 1 | MHz |
| 00 | t r /t f | Output rise and fall time all I/Os | C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 17 | ns |
| 00 | t r /t f | Output rise and fall time all I/Os | C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 33 | ns |
| 00 | t r /t f | Output rise and fall time all I/Os | C L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 85 | ns |
| 00 | t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 12.5 | ns |
| 00 | t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 25 | ns |
| 00 | t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 50 | ns |
| 01 | Fmax | Maximum frequency all I/Os | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 55 | MHz |
| 01 | Fmax | Maximum frequency all I/Os | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 12.5 | MHz |
| 01 | Fmax | Maximum frequency all I/Os | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 2.5 | MHz |
| 01 | Fmax | Maximum frequency all I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 55 | MHz |
| 01 | Fmax | Maximum frequency all I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 12.5 | MHz |
| 01 | Fmax | Maximum frequency all I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx ≤ <1.58 V | - | 2.5 | MHz |
| 01 | t r /t f | Output rise and fall time all I/Os | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 5.8 | ns |
| 01 | t r /t f | Output rise and fall time all I/Os | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 10 | ns |
| 01 | t r /t f | Output rise and fall time all I/Os | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 18 | ns |
| 01 | t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 4.2 | ns |
| 01 | t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 7.5 | ns |
| 01 | t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 12 | ns |
Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4)
309
Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4) (continued)
| Speed | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| 10 | Fmax | Maximum frequency all I/Os | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 100 (5) | MHz |
| Fmax | Maximum frequency all I/Os | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 33 (5) | MHz | |
| Fmax | Maximum frequency all I/Os | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 5 | MHz | |
| Fmax | Maximum frequency all I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 133 (5) | MHz | |
| Fmax | Maximum frequency all I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 40 (5) | MHz | |
| Fmax | Maximum frequency all I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 5 | MHz | |
| t r /t f | Output rise and fall time all I/Os | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 3.3 (5) | ns | |
| t r /t f | Output rise and fall time all I/Os | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 6.0 (5) | ns | |
| t r /t f | Output rise and fall time all I/Os | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 13.3 | ns | |
| t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 2 (5) | ns | |
| t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 4.1 (5) | ns | |
| t r /t f | Output rise and fall time all I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 9.2 | ns | |
| Fmax | Maximum frequency All I/Os except FT_c, FT_v, and TT_v | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 100 (5) | ns | |
| Fmax | Maximum frequency All I/Os except FT_c, FT_v, and TT_v | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 33 (5) | ns | |
| Fmax | Maximum frequency All I/Os except FT_c, FT_v, and TT_v | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 5 | ns | |
| Fmax | Maximum frequency All I/Os except FT_c, FT_v, and TT_v | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 133 (5) | ns | |
| Fmax | Maximum frequency All I/Os except FT_c, FT_v, and TT_v | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 40 (5) | ns | |
| Fmax | Maximum frequency All I/Os except FT_c, FT_v, and TT_v | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 5 | ns | |
| Fmax | Maximum frequency FT_v and TT_v I/Os | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 140 (5) | ns | |
| Fmax | Maximum frequency FT_v and TT_v I/Os | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 40 (5) | ns | |
| Fmax | Maximum frequency FT_v and TT_v I/Os | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 5 | ns | |
| 11 | Fmax | Maximum frequency FT_v and TT_v I/Os | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 166 (5) | ns |
| Fmax | Maximum frequency FT_v and TT_v I/Os | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 50 (5) | ns | |
| Fmax | Maximum frequency FT_v and TT_v I/Os | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 5 | ns | |
| t r /t f | Output rise and fall time All I/Os except FT_c, FT_v, and TT_v | C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | - | 3.3 (5) | ||
| t r /t f | Output rise and fall time All I/Os except FT_c, FT_v, and TT_v | C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V | - | 6.0 (5) | ||
| t r /t f | Output rise and fall time All I/Os except FT_c, FT_v, and TT_v | C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V | - | 13.3 | ||
| t r /t f | Output rise and fall time All I/Os except FT_c, FT_v, and TT_v | C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V | 2.0 (5) | |||
| t r /t f | Output rise and fall time All I/Os except FT_c, FT_v, and TT_v | C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V | 4.1 (5) | |||
| t r /t f | Output rise and fall time All I/Os except FT_c, FT_v, and TT_v | C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V | 9.2 |
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 30 , Table 31 and Table 32 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.
309
Table 30. Voltage characteristics (1)(2)
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DDX - V SS | External main supply voltage (including V DDSMPS , V DDA , V DDUSB , V BAT , V REF+ ) | -0.3 | 4.0 | V |
| V DDIOx (3) - V SS | I/O supply when HSLV = 0 | -0.3 | 4.0 | V |
| V DDIOx (3) - V SS | I/O supply when HSLV = 1 | -0.3 | 2.75 | V |
| V IN (4) | Input voltage on FT_xx pins except FT_c pins | V SS - 0.3 | Min (min (V DD ,V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0) (5)(6) | V |
| V IN (4) | Input voltage on FT_t pins in V BAT mode | V SS - 0.3 | Min (min (V BAT , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0) (5)(6) | V |
| V IN (4) | Input voltage on FT_c pins | V SS - 0.3 | 5.5 | V |
| V IN (4) | Input voltage on any other pins | V SS - 0.3 | 4.0 | V |
| V REF+ - V DDA | Allowed voltage difference for V REF+ > V DDA | - | 0.4 | V |
| \ | ∆ V DDx \ | Variations between different VDDx power pins of the same domain | - | |
| \ | V SSx -V SS \ | Variations between all the different ground pins (7) | - |
- The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
- VDDIO1 or V DDIO2 or V SW , V DDIO1 = V DD .
- VIN maximum must always be respected. Refer to Table 31 for the maximum allowed injected current values.
- To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
- This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
- Including VREF- pin.
Table 31. Current characteristics
| Symbol | Ratings | Max | Unit |
|---|---|---|---|
| ∑ IV DD | Total current into sum of all V DD power lines (source) (1) | 200 | mA |
| ∑ IV SS | Total current out of sum of all V SS ground lines (sink) (1) | 200 | mA |
| IV DD | Maximum current into each VDD power pin (source) (1) | 100 | mA |
| IV SS | Maximum current out of each VSS ground pin (sink) (1) | 100 | mA |
| I IO | Output current sunk by any I/O and control pin | 20 | mA |
| I IO | Output current sourced by any I/O and control pin | 20 | mA |
| ∑ I (PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 120 | mA |
| ∑ I (PIN) | Total output current sourced by sum of all I/Os and control pins (2) | 120 | mA |
| I INJ(PIN) (3)(4) | Injected current on FT_xx, TT_xx, RST pins | -5/+0 | mA |
| ∑ \ | I INJ(PIN) \ | Total injected current (sum of all I/Os and control pins) (5) |
Table 31. Current characteristics
- This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
- Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 30 for the minimum allowed input voltage values.
- When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) is the absolute sum of the negative injected currents (instantaneous values).
Table 32. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 140 | °C |
Table 32. Thermal characteristics
309
Thermal Information
The maximum chip-junction temperature, T J max, in degrees Celsius, can be calculated using the following equation:
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32U585AI | STMicroelectronics | — |
| STM32U585AII6 | STMicroelectronics | 169-UFBGA |
| STM32U585CI | STMicroelectronics | — |
| STM32U585OI | STMicroelectronics | — |
| STM32U585QI | STMicroelectronics | — |
| STM32U585RI | STMicroelectronics | — |
| STM32U585VI | STMicroelectronics | — |
| STM32U585XQ | STMicroelectronics | — |
| STM32U585ZI | STMicroelectronics | — |
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