Key Specifications

Parameter	Value
Additional Interfaces	CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
Additional Interfaces	CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
China RoHS	Compliant
Co-Processors/DSP	ARM® Cortex®-M4
Co-Processors/DSP	ARM® Cortex®-M4
Core Processor	ARM® Cortex®-A7
Display & Interface Controllers	HDMI-CEC, LCD
Display & Interface Controllers	HDMI-CEC, LCD
Ethernet	10/100Mbps, GbE
Ethernet	10/100Mbps, GbE
Graphics Acceleration	Yes
Graphics Acceleration	Yes
Lifecycle Status	Production (Last Updated: 5 months ago)
Max Supply Voltage	3.6 V
Min Supply Voltage	1.71 V
Mounting Type	Surface Mount
Number of A/D Converters	2
Number of Cores/Bus Width	2 Core, 32-Bit
Number of Cores/Bus Width	2 Core, 32-Bit
Number of D/A Converters	2
Number of I2C Channels	6
Number of SPI Channels	6
Number of Timers/Counters	2
Number of UART Channels	4
Number of USART Channels	4
Operating Temperature	-20°C ~ 105°C (TJ)
Package / Case	257-TFBGA
Packaging	Tray
RAM Controllers	DDR3, DDR3L, LPDDR2, LPDDR3
RAM Controllers	DDR3, DDR3L, LPDDR2, LPDDR3
REACH SVHC	Yes
RoHS	Compliant
Schedule B	8542310000
Security Features	ARM TZ
Security Features	ARM TZ
Clock Speed	209MHz, 800MHz
Standard Pack Qty	1104
Supplier Device Package	257-TFBGA (10x10)
Supplier Device Package	257-TFBGA (10x10)
USB	USB 2.0 (2), USB 2.0 OTG+ PHY (3)
USB	USB 2.0 (2), USB 2.0 OTG+ PHY (3)
Voltage - I/O	2.5V, 3.3V
Voltage - I/O	2.5V, 3.3V

Overview

Part: STM32MP157C/F — STMicroelectronics

Type: Arm® dual Cortex®-A7 + Cortex®-M4 MPU

Description: Dual-core Arm® Cortex®-A7 MPU running up to 800 MHz and a Cortex®-M4 MCU up to 209 MHz, featuring a 3D GPU, TFT/DSI display interfaces, extensive communication peripherals, advanced analog, and cryptographic hardware.

Operating Conditions:

Supply voltage: 1.71–3.6 V (I/Os and embedded regulators)
Operating temperature: -20 to +105 °C (suffix 1 version)
Cortex-A7 subsystem clock frequency: 0–800 MHz (STM32MP157F)
MCU AHB clock frequency: 0–209 MHz

Absolute Maximum Ratings:

Max supply voltage: 3.9 V (V DDX - V SSX)
Max continuous current: 440 mA (Total current into sum of all V DD power lines)
Max junction/storage temperature: 150 °C (Storage temperature range)

Key Specs:

Cortex-A7 frequency: Up to 800 MHz (STM32MP157F)
Cortex-M4 frequency: Up to 209 MHz
Internal SRAM: 708 Kbytes (256 KB AXI SYSRAM + 384 KB AHB SRAM + 64 KB AHB SRAM in Backup domain + 4 KB SRAM in Backup domain)
External DDR memory: Up to 1 Gbyte (LPDDR2/LPDDR3-1066, DDR3/DDR3L-1066)
ADC resolution: 16-bit max. (up to 3.6 Msps)
DAC resolution: 12-bit (1 MHz)
I/O ports: Up to 176 with interrupt capability
Low-power consumption: Down to 2 μA (Standby mode)

Features:

Dual-core Arm® Cortex®-A7 with NEON™ and TrustZone®
Arm® Cortex®-M4 with FPU/MPU
3D GPU: Vivante® - OpenGL® ES 2.0
Secure boot, TrustZone® peripherals, active tamper
Up to 37 communication peripherals including I2C, UART, SPI, SAI, SDMMC, CAN FD, USB 2.0 HS Host/OTG, Ethernet GMAC
LCD-TFT controller and MIPI® DSI 2 data lanes
Hardware acceleration: AES, TDES, HASH, HMAC, TRNG, CRC
Up to 29 timers and 3 watchdogs
DDR memory retention in Standby mode

Applications:

Package:

TFBGA257
LFBGA354
TFBA361
LFBGA448

Features

ARMv7-A architecture
32-Kbyte L1 instruction cache for each CPU
32-Kbyte L1 data cache for each CPU
256-Kbyte level2 cache
Arm ® + Thumb ® -2 instruction set
Arm ® TrustZone ® security technology
Arm ® NEON™ Advanced SIMD
DSP and SIMD extensions
VFPv4 floating-point
Hardware virtualization support
Embedded trace module (ETM)
Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts
Integrated generic timer (CNT)

Pin Configuration

Figure 5. STM32MP157C/FADxx TFBGA257 pinout

The above figure shows the package top view.

121

Figure 6. STM32MP157C/FABxx LFBGA354 pinout

The above figure shows the package top view.

Figure 7. STM32MP157C/FACxx TFBGA361 pinout

The above figure shows the package top view.

121

Figure 8. STM32MP157C/FAAxx LFBGA448 pinout

The above figure shows the package top view.

Table 6. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name	Unless otherwise specified, the pin function during and after reset is the same as the actual pin name	Unless otherwise specified, the pin function during and after reset is the same as the actual pin name
Pin type	S	Supply pin
Pin type	I	Input only pin
Pin type	O	Output only pin
Pin type	I/O	Input / output pin
Pin type	A	Analog or special level pin
I/O structure	FT(U/D/PD)	5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down)
I/O structure	TT	3.6 V tolerant I/O directly connected to DAC
I/O structure	DDR	1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface
I/O structure	DSI	1.2 V I/O for DSI interface
I/O structure	A	Analog signal
I/O structure	RST	Reset pin with weak pull-up resistor
I/O structure	Option for TT or FT I/Os	Option for TT or FT I/Os
I/O structure	_f (1)	I2C FM+ option
I/O structure	_a (2)	Analog option (supplied by VDDA for the analog part of the I/O)
I/O structure	_u (3)	USB option (supplied by VDD3V3_USBxx for the USB part of the I/O)
I/O structure	_h (4)	High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE)
I/O structure	_vh (5)	Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI, TRACE)
Notes	Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset	Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions	Functions selected through GPIOx_AFR registers	Functions selected through GPIOx_AFR registers
Additional functions	Functions directly selected/enabled through peripheral registers	Functions directly selected/enabled through peripheral registers

The related I/O structures in Table 7 are: FT_f, FT_favh, FT_fh, FT_fha, FT_uf
The related I/O structures in Table 7 are: FT_a, TT_a, FT_avh, FT_favh, FT_fha, FT_ha, TT_ha
The related I/O structures in Table 7 are: FT_u, FT_uf
The related I/O structures in Table 7 are: FT_h, FT_fh, FT_fha, FT_ha, TT_ha
The related I/O structures in Table 7 are: FT_vh, FT_avh, FT_favh

121

Table 7. STM32MP157C/F pin and ball definitions

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	-	A2	A2	PH5	I/O	FT_f	-	I2C2_SDA, SPI5_NSS, SAI4_SD_B, EVENTOUT	-
-	-	C2	B1	PH10	I/O	FT	-	TIM5_CH1, I2C4_SMBA, I2C1_SMBA,DCMI_D1,LCD_R4, EVENTOUT	-
-	-	B2	F5	PH12	I/O	FT_f	-	HDP2, TIM5_CH3, I2C4_SDA, I2C1_SDA, DCMI_D3, LCD_R6, EVENTOUT	-
-	-	D1	D3	PH13	I/O	FT	-	TIM8_CH1N, UART4_TX, FDCAN1_TX, LCD_G2, EVENTOUT	-
1E2	K6	1F3	M9	VDD	S	-	-	-	-
A1	A1	A1	A1	VSS	S	-	-	-	-
-	-	C3	C2	PH14	I/O	FT	-	TIM8_CH2N, UART4_RX, FDCAN1_RX, DCMI_D4, LCD_G3, EVENTOUT	-
-	-	B1	C1	PH15	I/O	FT	-	TIM8_CH3N, DCMI_D11, LCD_G4, EVENTOUT	-
-	-	-	H6	PJ8	I/O	FT_h	-	TRACED14, TIM1_CH3N, TIM8_CH1, UART8_TX, LCD_G1, EVENTOUT	-
-	-	-	D2	PI14	I/O	FT_h	-	TRACECLK, LCD_CLK, EVENTOUT	-
-	-	-	F3	PI15	I/O	FT	-	LCD_G2, LCD_R0, EVENTOUT	-
-	-	C1	D1	PI0	I/O	FT	-	TIM5_CH4,SPI2_NSS/I2S2_WS, DCMI_D13, LCD_G5, EVENTOUT	-
-	-	E3	E2	PI1	I/O	FT_h	-	TIM8_BKIN2, SPI2_SCK/I2S2_CK, DCMI_D8, LCD_G6, EVENTOUT	-
-	-	E2	E1	PI2	I/O	FT_h	-	TIM8_CH4, SPI2_MISO/I2S2_SDI,DCMI_D9, LCD_G7, EVENTOUT	-
1B3	E7	1A2	H9	VDDCORE	S	-	-	-	-
-	-	E1	E3	PI3	I/O	FT_h	-	TIM8_ETR, SPI2_MOSI/I2S2_SDO, DCMI_D10, EVENTOUT	-
-	-	E4	J6	PI4	I/O	FT	-	TIM8_BKIN, SAI2_MCLK_A, DCMI_D5, LCD_B4, EVENTOUT	-
-	-	F3	F2	PI5	I/O	FT	-	TIM8_CH1, SAI2_SCK_A, DCMI_VSYNC, LCD_B5, EVENTOUT	-
-	-	F4	G5	PI6	I/O	FT	-	TIM8_CH2, SAI2_SD_A, DCMI_D6, LCD_B6, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	-	F2	F1	PI7	I/O	FT	-	TIM8_CH3, SAI2_FS_A, DCMI_D7, LCD_B7, EVENTOUT	-
-	A19	A23	A19	VSS	S	-	-	-	-
-	-	G1	H5	PZ1	I/O	FT_fh	-	I2C6_SDA, I2C2_SDA, I2C5_SDA, SPI1_MISO/I2S1_SDI, I2C4_SDA, USART1_RX, SPI6_MISO, EVENTOUT	-
-	-	G4	F4	PZ3	I/O	FT_f	-	I2C6_SDA, I2C2_SDA, I2C5_SDA, SPI1_NSS/I2S1_WS, I2C4_SDA, USART1_CTS/USART1_NSS, SPI6_NSS, EVENTOUT	-
-	-	H4	J5	PI9	I/O	FT	-	HDP1, UART4_RX, FDCAN1_RX, LCD_VSYNC, EVENTOUT	-
-	-	G3	G2	PZ0	I/O	FT_fh	-	I2C6_SCL, I2C2_SCL, SPI1_SCK/I2S1_CK, USART1_CK, SPI6_SCK, EVENTOUT	-
-	-	J4	K5	PZ2	I/O	FT_fh	-	I2C6_SCL, I2C2_SCL, I2C5_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, USART1_TX, SPI6_MOSI, EVENTOUT	-
-	-	G2	G1	PZ4	I/O	FT_f	-	I2C6_SCL, I2C2_SCL, I2C5_SCL, I2C4_SCL, EVENTOUT	-
G1	B2	-	A22	VSS	S	-	-	-	-
D1	F1	K4	J4	PG12	I/O	FT_h	-	LPTIM1_IN1, SPI6_MISO, SAI4_CK2, USART6_RTS/USART6_DE, SPDIFRX_IN2, LCD_B4, SAI4_SCK_A,ETH1_PHY_INTN, FMC_NE4, LCD_B1, EVENTOUT	-
-	-	H2	H4	PZ5	I/O	FT_f	-	I2C6_SDA, I2C2_SDA, I2C5_SDA, I2C4_SDA, USART1_RTS/USART1_DE, EVENTOUT	-
-	E9	-	-	VDDCORE	S	-	-	-	-
-	-	H1	G3	PZ6	I/O	FT_f	-	I2C6_SCL, I2C2_SCL, USART1_CK, I2S1_MCK, I2C4_SMBA, USART1_RX, EVENTOUT	-
-	-	J3	H3	PZ7	I/O	FT_f	-	I2C6_SDA, I2C2_SDA, USART1_TX, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	-	-	H2	PI12	I/O	FT_h	-	TRACED0, HDP0, LCD_HSYNC, EVENTOUT	-
-	B6	C7	B2	VSS	S	-	-	-	-
-	-	-	H1	PI13	I/O	FT_h	-	TRACED1, HDP1, LCD_VSYNC, EVENTOUT	-
-	-	1A4	H11	VDDCORE	S	-	-	-	-
-	-	-	J3	PJ10	I/O	FT_h	-	TIM1_CH2N, TIM8_CH2, SPI5_MOSI, LCD_G3, EVENTOUT	-
-	-	-	K6	PJ11	I/O	FT_h	-	TIM1_CH2, TIM8_CH2N, SPI5_MISO, LCD_G4, EVENTOUT	-
-	-	-	J2	PJ0	I/O	FT_h	-	TRACED8, LCD_R7, LCD_R1, EVENTOUT	-
-	-	-	L6	PJ1	I/O	FT_h	-	TRACED9, LCD_R2, EVENTOUT	-
-	-	-	K4	PJ2	I/O	FT_h	-	TRACED10, DSI_TE, LCD_R3, EVENTOUT	-
-	L5	-	-	VDD	S	-	-	-	-
-	-	-	J1	PJ3	I/O	FT_h	-	TRACED11, LCD_R4, EVENTOUT	-
N1	C3	-	B19	VSS	S	-	-	-	-
-	-	-	K2	PJ4	I/O	FT_h	-	TRACED12, LCD_R5, EVENTOUT	-
1D3	E11	-	-	VDDCORE	S	-	-	-	-
-	-	-	K1	PJ5	I/O	FT_h	-	TRACED2, HDP2, LCD_R6, EVENTOUT	-
-	-	-	L5	PJ6	I/O	FT_h	-	TRACED3, HDP3, TIM8_CH2, LCD_R7, EVENTOUT	-
-	-	-	L4	PJ7	I/O	FT_h	-	TRACED13, TIM8_CH2N, LCD_G0, EVENTOUT	-
-	C17	C12	C3	VSS	S	-	-	-	-
1B1	E3	D2	L3	PD6	I/O	FT_ha	-	TIM16_CH1N, SAI1_D1, DFSDM1_CKIN4, DFSDM1_DATIN1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT	-
-	E13	-	H13	VDDCORE	S	-	-	-	-
-	-	-	L2	PJ9	I/O	FT_h	-	TRACED15, TIM1_CH3, TIM8_CH1N, UART8_RX, LCD_G2, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	J5	-	M6	VDD_PLL	S	-	-	-	-
-	J4	-	M5	VSS_PLL	S	-	-	-	-
1E1	F3	L3	M3	PD14	I/O	FT_a	-	TIM4_CH3, SAI3_MCLK_B, UART8_CTS, FMC_AD0/FMC_D0, EVENTOUT	-
1C2	G1	J2	L1	PD15	I/O	FT_a	-	TIM4_CH4, SAI3_MCLK_A, UART8_CTS, FMC_AD1/FMC_D1, LCD_R1, EVENTOUT	-
E1	F2	K3	M1	PD8	I/O	FT_a	-	DFSDM1_CKIN3, SAI3_SCK_B, USART3_TX, SPDIFRX_IN2, FMC_AD13/FMC_D13, LCD_B7, EVENTOUT	-
1C1	G3	K1	M2	PD9	I/O	FT_a	-	DFSDM1_DATIN3, SAI3_SD_B, USART3_RX, FMC_AD14/FMC_D14, DCMI_HSYNC, LCD_B0, EVENTOUT	-
-	-	-	N8	VDD	S	-	-	-	-
W1	D1	C21	C8	VSS	S	-	-	-	-
-	-	1A6	-	VDDCORE	S	-	-	-	-
1D1	H3	1F1	M4	VBAT	S	-	-	-	-
-	D4	-	C11	VSS	S	-	-	-	-
-	-	L4	N1	PI8	I/O	FT	(1)	EVENTOUT	RTC_OUT2/ RTC_LSCO, TAMP_IN2/ TAMP_OUT3, WKUP4
G3	K3	K2	N2	PC13	I/O	FT	(1)	EVENTOUT	RTC_OUT1/ RTC_TS/ RTC_LSCO, TAMP_IN1/ TAMP_OUT2/ TAMP_OUT3, WKUP3
F3	D5	D4	C19	VSS	S	-	-	-	-
F2	H2	L1	P2	PC15- OSC32_OUT	I/O	FT	(1)	EVENTOUT	OSC32_OUT
-	F4	-	H15	VDDCORE	S	-	-	-	-
1C4	F6	1B1	-	VDDCORE	S	-	-	-	-
G2	H1	L2	P1	PC14- OSC32_IN	I/O	FT	(1)	EVENTOUT	OSC32_IN

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
E2	J1	M3	R2	NRST	I/O	RST	-	-	-
J3	J2	M4	R1	NRST_CORE	I	RST	-	-	-
H3	K1	N1	N3	BOOT0	I	FTPD	-	-	-
K3	K4	N4	N4	BOOT1	I	FTPD	-	-	-
H1	L2	M2	P4	BOOT2	I	FTPD	-	-	-
H2	M1	P1	T1	PH0-OSC_IN	I/O	FT	-	EVENTOUT	OSC_IN
-	-	-	J8	VDDCORE	S	-	-	-	-
J2	M2	P2	T2	PH1- OSC_OUT	I/O	FT	-	EVENTOUT	OSC_OUT
-	D8	-	C20	VSS	S	-	-	-	-
M2	L1	R2	V1	PWR_ON	O	FT	-	-	PWR_ONLP
K1	P1	N3	U1	PWR_LP	O	FT	-	-	-
K2	N1	T3	U2	PDR_ON_ CORE	I	FT	-	-	-
L3	N2	R3	V2	PDR_ON	I	FT	-	-	-
-	L3	1G2	N5	VDD_ANA	S	-	-	-	-
-	L4	1G1	P5	VSS_ANA	S	-	-	-	-
L2	P2	N2	W3	PA13	I/O	FT_a	-	DBTRGO, DBTRGI, MCO1, UART4_TX, EVENTOUT	BOOTFAILN
L1	R1	T2	R3	PA14	I/O	FT_a	-	DBTRGO, DBTRGI, MCO2, EVENTOUT	-
-	-	P4	T3	PI11	I/O	FT	-	MCO1, I2S_CKIN, LCD_G6, EVENTOUT	WKUP5
-	-	T1	W1	PI10	I/O	FT	-	HDP0, USART3_CTS/USART3_NSS, ETH1_GMII_RX_ER/ ETH1_MII_RX_ER, LCD_HSYNC, EVENTOUT	-
-	L7	1G4	-	VDD	S	-	-	-	-
W5	E2	F21	-	VSS	S	-	-	-	-
-	F8	-	-	VDDCORE	S	-	-	-	-
1F1	M4	1H1	R5	VDDA	S	-	-	-	-
1F2	-	-	-	VDDA	S	-	-	-	-
M3	N3	R4	P6	VREF+	S	-	-	-	-
1G1	N4	1H2	R6	VSSA	S	-	-	-	-
-	P5	-	T6	VSSA	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	R5	-	U6	VSSA	S	-	-	-	-
-	M3	-	N6	VREF-	S	-	-	-	-
-	-	W4	W2	PH7	I/O	FT_fh	-	I2C3_SCL, SPI5_MISO, ETH1_GMII_RXD3/ ETH1_MII_RXD3/ ETH1_RGMII_RXD3, MDIOS_MDC, DCMI_D9, EVENTOUT	-
-	-	U1	V3	PF3	I/O	FT_vh	-	ETH1_GMII_TX_ER, FMC_A3, EVENTOUT	-
P3	T3	W2	U3	PC3	I/O	FT_ha	-	TRACECLK, DFSDM1_DATIN1, SPI2_MOSI/I2S2_SDO, ETH1_GMII_TX_CLK/ ETH1_MII_TX_CLK, EVENTOUT	ADC1_INP13, ADC1_INN12
-	-	T4	U4	PG3	I/O	FT_vh	-	TRACED3, TIM8_BKIN2, DFSDM1_CKIN1, ETH1_GMII_TXD7, FMC_A13, EVENTOUT	-
P1	T1	Y1	Y2	PE2	I/O	FT_favh	-	TRACECLK, SAI1_CK1, I2C4_SCL, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, ETH1_GMII_TXD3/ ETH1_MII_TXD3/ ETH1_RGMII_TXD3, FMC_A23, EVENTOUT	-
-	-	-	N10	VDD	S	-	-	-	-
-	E4	H3	D4	VSS	S	-	-	-	-
N2	P3	U2	T4	PA3	I/O	FT_a	-	TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, USART2_RX, LCD_B2, ETH1_GMII_COL/ ETH1_MII_COL, LCD_B5, EVENTOUT	ADC1_INP15, PVD_IN
P2	T2	Y2	Y1	PC2	I/O	FT_avh	-	DFSDM1_CKIN1, SPI2_MISO/I2S2_SDI, DFSDM1_CKOUT, ETH1_GMII_TXD2/ ETH1_MII_TXD2/ ETH1_RGMII_TXD2, DCMI_PIXCLK, EVENTOUT	ADC1_INP12, ADC1_INN11
-	-	V2	W4	PG2	I/O	FT_vh	-	TRACED2, MCO2, TIM8_BKIN, ETH1_GMII_TXD6, FMC_A12, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
R2	U1	AA1	AA2	PG14	I/O	FT_vh	-	TRACED1, LPTIM1_ETR, SPI6_MOSI, SAI4_D1, USART6_TX, QUADSPI_BK2_IO3, SAI4_SD_A, ETH1_GMII_TXD1/ ETH1_MII_TXD1/ ETH1_RGMII_TXD1/ ETH1_RMII_TXD1, FMC_A25, LCD_B0, EVENTOUT	-
-	-	W1	Y4	PG1	I/O	FT_vh	-	TRACED1, ETH1_GMII_TXD5, FMC_A11, EVENTOUT	-
R3	U2	AA2	AA1	PG13	I/O	FT_vh	-	TRACED0, LPTIM1_OUT, SAI1_CK2, SAI4_CK1, SPI6_SCK, SAI1_SCK_A, USART6_CTS/USART6_NSS, SAI4_MCLK_A, ETH1_GMII_TXD0/ ETH1_MII_TXD0/ ETH1_RGMII_TXD0/ ETH1_RMII_TXD0, FMC_A24, LCD_R0, EVENTOUT	-
-	-	U3	R4	ANA0	A	A	-	-	ADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1
N3	R3	AB3	AA3	PA0	I/O	FT_ha	-	TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, TIM15_BKIN, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH1_GMII_CRS/ ETH1_MII_CRS, EVENTOUT	ADC1_INP16, WKUP1
-	E5	-	E5	VSS	S	-	-	-	-
-	-	U4	T5	ANA1	A	A	-	-	ADC1_INP1, ADC2_INP1
T1	U4	AA4	V4	PA1	I/O	FT_ha	-	ETH_CLK, TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, USART2_RTS/USART2_DE, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, ETH1_GMII_RX_CLK/ ETH1_MII_RX_CLK/ ETH1_RGMII_RX_CLK/ ETH1_RMII_REF_CLK,LCD_R2, EVENTOUT	ADC1_INP17, ADC1_INN16

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
1H1	P4	V3	U5	PA5	I/O	TT_ha	-	TIM2_CH1/TIM2_ETR, TIM8_CH1N, SAI4_CK1, SPI1_SCK/I2S1_CK, SPI6_SCK, SAI4_MCLK_A, LCD_R4, EVENTOUT	ADC1_INP19, ADC1_INN18, ADC2_INP19, ADC2_INN18, DAC_OUT2
1J1	R4	V4	V6	PA4	I/O	TT_a	-	HDP0, TIM5_ETR, SAI4_D2, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, SAI4_FS_A, DCMI_HSYNC, LCD_VSYNC, EVENTOUT	ADC1_INP18, ADC2_INP18, DAC_OUT1
-	-	AC2	W5	PG0	I/O	FT_vh	-	TRACED0, DFSDM1_DATIN0, ETH1_GMII_TXD4, FMC_A10, EVENTOUT	-
U3	V1	AB1	Y5	PB11	I/O	FT_favh	-	TIM2_CH4, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, ETH1_GMII_TX_EN/ ETH1_MII_TX_EN/ ETH1_RGMII_TX_CTL/ ETH1_RMII_TX_EN, DSI_TE, LCD_G5, EVENTOUT	-
-	-	AB2	AB4	PG4	I/O	FT_vh	-	TIM1_BKIN2, ETH1_GMII_GTX_CLK/ ETH1_RGMII_GTX_CLK, FMC_A14, EVENTOUT	-
T3	W2	AC3	AB2	PA2	I/O	FT_ha	-	TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, USART2_TX, SAI2_SCK_B, SDMMC2_D0DIR, ETH1_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT	ADC1_INP14, WKUP2
1F3	M6	-	-	VDD	S	-	-	-	-
T2	V2	AA6	AB3	PC1	I/O	FT_ha	-	TRACED0, SAI1_D1, DFSDM1_DATIN0, DFSDM1_CKIN4, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, SDMMC2_CK, ETH1_MDC, MDIOS_MDC, EVENTOUT	ADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10, TAMP_IN3, WKUP6
A6	-	K21	E19	VSS	S	-	-	-	-
-	-	Y6	U8	PG5	I/O	FT	-	TIM1_ETR, ETH1_GMII_CLK125/ ETH1_RGMII_CLK125, FMC_A15, EVENTOUT	-
-	F10	1B3	J10	VDDCORE	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	-	AA3	Y6	PH3	I/O	FT_h	-	DFSDM1_CKIN4, QUADSPI_BK2_IO1, SAI2_MCLK_B, ETH1_GMII_COL/ ETH1_MII_COL, LCD_R1, EVENTOUT	-
U2	W3	AB6	AB5	PB0	I/O	FT_a	-	TIM1_CH2N, TIM3_CH3, TIM8_CH2N, DFSDM1_CKOUT, UART4_CTS, LCD_R3, ETH1_GMII_RXD2/ ETH1_MII_RXD2/ ETH1_RGMII_RXD2, MDIOS_MDIO, LCD_G1, EVENTOUT	ADC1_INP9, ADC1_INN5, ADC2_INP9, ADC2_INN5
-	-	Y4	W6	PF15	I/O	FT_fh	-	TRACED7, I2C4_SDA, I2C1_SDA, ETH1_GMII_RXD7, FMC_A9, EVENTOUT	-
U1	V3	AA7	AA5	PB1	I/O	FT_a	-	TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, ETH1_GMII_RXD3/ ETH1_MII_RXD3/ ETH1_RGMII_RXD3, MDIOS_MDC, LCD_G0, EVENTOUT	ADC1_INP5, ADC2_INP5
-	E6	-	F6	VSS	S	-	-	-	-
-	-	AC4	V7	PF14	I/O	FT_fha	-	TRACED6, DFSDM1_CKIN6, I2C4_SCL, I2C1_SCL, ETH1_GMII_RXD6, FMC_A8, EVENTOUT	ADC2_INP6, ADC2_INN2
-	-	Y5	W7	PF13	I/O	FT_ha	-	TRACED5, DFSDM1_DATIN6, I2C4_SMBA, I2C1_SMBA, DFSDM1_DATIN3, ETH1_GMII_RXD5, FMC_A7, EVENTOUT	ADC2_INP2
-	-	AB4	AB7	PH2	I/O	FT_h	-	LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH1_GMII_CRS/ ETH1_MII_CRS, LCD_R0, EVENTOUT	-
V1	V4	AB7	AA6	PC5	I/O	FT_a	-	SAI1_D3, DFSDM1_DATIN2, SAI4_D4, SAI1_D4, SPDIFRX_IN4, ETH1_GMII_RXD1/ ETH1_MII_RXD1/ ETH1_RGMII_RXD1/ ETH1_RMII_RXD1, SAI4_D3, EVENTOUT	ADC1_INP8, ADC1_INN4, ADC2_INP8, ADC2_INN4

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
V2	W4	AC7	AB6	PC4	I/O	FT_a	-	DFSDM1_CKIN2, I2S1_MCK, SPDIFRX_IN3, ETH1_GMII_RXD0/ ETH1_MII_RXD0/ ETH1_RGMII_RXD0/ ETH1_RMII_RXD0, EVENTOUT	ADC1_INP4, ADC2_INP4
-	M8	-	P9	VDD	S	-	-	-	-
1D2	E8	P3	F7	VSS	S	-	-	-	-
1J3	R7	1J2	U9	VDD	S	-	-	-	-
-	-	Y9	V8	PF12	I/O	FT_ha	-	TRACED4, ETH1_GMII_RXD4, FMC_A6, EVENTOUT	ADC1_INP6, ADC1_INN2
1E4	-	-	-	VDDCORE	S	-	-	-	-
W4	U5	Y10	W8	PF11	I/O	FT_ha	-	SPI5_MOSI, SAI2_SD_B, DCMI_D12, LCD_G5, EVENTOUT	ADC1_INP2
-	E10	-	F8	VSS	S	-	-	-	-
W2	T6	AB8	Y9	PA7	I/O	FT_ha	-	TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SAI4_D1, SPI1_MOSI/I2S1_SDO, SPI6_MOSI, TIM14_CH1, QUADSPI_CLK, ETH1_GMII_RX_DV/ ETH1_MII_RX_DV/ ETH1_RGMII_RX_CTL/ ETH1_RMII_CRS_DV, SAI4_SD_A, EVENTOUT	ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3
-	F12	-	J12	VDDCORE	S	-	-	-	-
W3	T5	AC8	W9	PA6	I/O	FT_ha	-	TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SAI4_CK2, SPI1_MISO/I2S1_SDI, SPI6_MISO, TIM13_CH1, MDIOS_MDC, SAI4_SCK_A, DCMI_PIXCLK, LCD_G2, EVENTOUT	ADC1_INP3, ADC2_INP3
-	-	1H3	-	VDD	S	-	-	-	-
U4	T7	AB5	U10	PC0	I/O	FT_ha	-	DFSDM1_CKIN0, LPTIM2_IN2, DFSDM1_DATIN4, SAI2_FS_B, QUADSPI_BK2_NCS, LCD_R5, EVENTOUT	ADC1_INP10, ADC2_INP10
1G2	E12	P21	F16	VSS	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
U5	W5	Y3	V9	PB10	I/O	FT_fha	-	TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, QUADSPI_BK1_NCS, ETH1_GMII_RX_ER/ ETH1_MII_RX_ER, LCD_G4, EVENTOUT	-
-	-	1B5	-	VDDCORE	S	-	-	-	-
V3	V5	AC5	AA7	PB12	I/O	FT_avh	-	TIM1_BKIN, I2C6_SMBA, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1,USART3_CK, USART3_RX, FDCAN2_RX, ETH1_GMII_TXD0/ ETH1_MII_TXD0/ ETH1_RGMII_TXD0/ ETH1_RMII_TXD0, UART5_RX, EVENTOUT	-
-	G5	-	J14	VDDCORE	S	-	-	-	-
1J2	T9	AA10	V10	PB13	I/O	FT_vh	-	TIM1_CH1N, DFSDM1_CKOUT, LPTIM2_OUT, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS/USART3_NSS, FDCAN2_TX, ETH1_GMII_TXD1/ ETH1_MII_TXD1/ ETH1_RGMII_TXD1/ ETH1_RMII_TXD1, UART5_TX,	-
-	E14	V21	F20	VSS	S	-	-	-	-
V5	T8	Y8	AA8	PB5	I/O	FT_vh	-	ETH_CLK, TIM17_BKIN, TIM3_CH2, SAI4_D1, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, SAI4_SD_A, ETH1_PPS_OUT, UART5_RX, DCMI_D10, LCD_G7, EVENTOUT	-
U6	V6	Y7	U11	PG11	I/O	FT_vh	-	TRACED11, USART1_TX, UART4_TX, SPDIFRX_IN1, ETH1_GMII_TX_EN/ ETH1_MII_TX_EN/ ETH1_RGMII_TX_CTL/ ETH1_RMII_TX_EN, DCMI_D3, LCD_B3, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
1B5	G7	1C2	-	VDDCORE	S	-	-	-	-
-	-	Y11	V11	PH6	I/O	FT_h	-	TIM12_CH1, I2C2_SMBA, SPI5_SCK, ETH1_GMII_RXD2/ ETH1_MII_RXD2/ ETH1_RGMII_RXD2, MDIOS_MDIO, DCMI_D8, EVENTOUT	-
1H2	E16	-	G4	VSS	S	-	-	-	-
V4	W6	AB10	AB8	PB8	I/O	FT_favh	-	HDP6, TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, SDMMC1_CKIN, I2C4_SCL, SDMMC2_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH1_GMII_TXD3/ ETH1_MII_TXD3/ ETH1_RGMII_TXD3, SDMMC1_D4, DCMI_D6, LCD_B6, EVENTOUT	-
-	-	-	K9	VDDCORE	S	-	-	-	-
V6	U7	AB9	Y8	PG8	I/O	FT_vh	-	TRACED15, TIM2_CH1/TIM2_ETR, ETH_CLK, TIM8_ETR, SPI6_NSS, SAI4_D2, USART6_RTS/USART6_DE, USART3_RTS/USART3_DE, SPDIFRX_IN3, SAI4_FS_A, ETH1_PPS_OUT, LCD_G7, EVENTOUT	-
-	N5	-	P11	VDD	S	-	-	-	-
U7	V7	AB11	AA9	PG10	I/O	FT_h	-	TRACED10, UART8_CTS, LCD_G3, SAI2_SD_B, QUADSPI_BK2_IO2, FMC_NE3, DCMI_D2, LCD_B2, EVENTOUT	-
-	F5	W3	-	VSS	S	-	-	-	-
1J4	W7	AA9	W11	PE9	I/O	FT_ha	-	TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE, QUADSPI_BK2_IO2, FMC_AD6/FMC_D6, EVENTOUT	-
-	G9	-	-	VDDCORE	S	-	-	-	-
V7	T10	AA11	W10	PE7	I/O	FT_h	-	TIM1_ETR, TIM3_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_AD4/FMC_D4, EVENTOUT	-
1C3	F7	-	G6	VSS	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
U8	V8	AC10	AB9	PD11	I/O	FT_h	-	LPTIM2_IN2, I2C4_SMBA, I2C1_SMBA, USART3_CTS/USART3_NSS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT	-
1D5	G11	1C4	-	VDDCORE	S	-	-	-	-
W7	W8	AB12	AA10	PF7	I/O	FT_ha	-	TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT	-
V8	U10	AC11	AB10	PF8	I/O	FT_ha	-	TRACED12, TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT	-
-	-	-	K11	VDDCORE	S	-	-	-	-
1J7	U9	Y12	V12	PF10	I/O	FT_h	-	TIM16_BKIN,SAI1_D3,SAI4_D4, SAI1_D4, QUADSPI_CLK, SAI4_D3, DCMI_D11, LCD_DE, EVENTOUT	-
-	F9	AA5	G8	VSS	S	-	-	-	-
U10	V9	AA13	AA11	PF6	I/O	FT_ha	-	TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, SAI4_SCK_B, EVENTOUT	-
-	H4	-	-	VDDCORE	S	-	-	-	-
U14	U11	Y18	W12	PD12	I/O	FT_fha	-	LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, I2C1_SCL, USART3_RTS/USART3_DE, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, EVENTOUT	-
-	F11	AA8	G10	VSS	S	-	-	-	-
V9	W9	AA14	AB11	PF9	I/O	FT_ha	-	TRACED13, TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT	-
-	H6	1C6	K13	VDDCORE	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
V11	W10	AC14	Y11	PG7	I/O	FT_h	-	TRACED5, SAI1_MCLK_A, USART6_CK, UART8_RTS/UART8_DE, QUADSPI_CLK, QUADSPI_BK2_IO3,DCMI_D13, LCD_CLK, EVENTOUT	-
1E3	F15	-	G12	VSS	S	-	-	-	-
1F5	-	-	-	VDDCORE	S	-	-	-	-
W11	T12	Y14	W13	PB6	I/O	FT_fha	-	TIM16_CH1N, TIM4_CH1, I2C1_SCL, CEC, I2C4_SCL, USART1_TX, FDCAN2_TX, QUADSPI_BK1_NCS, DFSDM1_DATIN5, UART5_TX, DCMI_D5, EVENTOUT	-
U12	T11	AC13	Y12	PE8	I/O	FT_h	-	TIM1_CH1N, DFSDM1_CKIN2, UART7_TX,QUADSPI_BK2_IO1, FMC_AD5/FMC_D5, EVENTOUT	-
V12	V10	Y15	W14	PE10	I/O	FT_ha	-	TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_AD7/FMC_D7, EVENTOUT	-
-	H8	1D1	K15	VDDCORE	S	-	-	-	-
V13	T13	Y16	V13	PB2	I/O	FT_ha	-	TRACED4, RTC_OUT2, SAI1_D1, DFSDM1_CKIN1, USART1_RX, I2S_CKIN, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, UART4_RX, QUADSPI_CLK, EVENTOUT	-
-	H10	-	-	VDDCORE	S	-	-	-	-
U13	U12	AA19	V14	PD13	I/O	FT_fha	-	LPTIM1_OUT, TIM4_CH2, I2C4_SDA, I2C1_SDA, I2S3_MCK, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, DSI_TE, EVENTOUT	-
-	N7	-	-	VDD	S	-	-	-	-
-	G2	AA12	G14	VSS	S	-	-	-	-
1J8	V16	AB18	AA17	USB_RREF	A	A	-	-	-
-	W12	AA15	AB13	VDD3V3_ USBHS	S	-	-	-	-
1H7	-	-	-	VDD3V3_ USB	S	-	-	-	-
V10	W13	AC16	AB14	USB_DP2	A	FT_u	-	-	USBH_HS_DP2, OTG_HS_DP

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
W10	V13	AB16	AA14	USB_DM2	A	FT_u	-	-	USBH_HS_DM2, OTG_HS_DM
-	U13	AA16	Y13	VSS_USBHS	S	-	-	-	-
-	-	-	Y14	VSS_USBHS	S	-	-	-	-
U11	T15	AB13	AA12	BYPASS_ REG1V8	I	FT	-	-	-
W8	T14	Y13	W15	PG9	I/O	FT_h	-	DBTRGO, USART6_RX, SPDIFRX_IN4, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE, DCMI_VSYNC, LCD_R1, EVENTOUT	-
1G3	-	1H5	R10	VDD	S	-	-	-	-
-	N9	-	-	VDD	S	-	-	-	-
1H5	V11	AB14	AB12	VDDA1V8_ REG	S	-	-	-	-
1H3	-	-	G17	VSS	S	-	-	-	-
1J6	W11	AB15	AB17	VDDA1V1_ REG	S	-	-	-	-
-	G4	AA21	H7	VSS	S	-	-	-	-
-	-	-	R12	VDD	S	-	-	-	-
-	P6	-	-	VDD	S	-	-	-	-
-	U14	-	Y15	VSS_USBHS	S	-	-	-	-
-	V12	-	AA13	VSS_USBHS	S	-	-	-	-
1D4	G6	AC1	J9	VSS	S	-	-	-	-
-	V15	-	AA16	VSS_USBHS	S	-	-	-	-
W14	W14	AB17	AB15	USB_DM1	A	FT_u	-	-	USBH_HS_DM1
V14	V14	AC17	AA15	USB_DP1	A	FT_u	-	-	USBH_HS_DP1
V15	U16	AB19	W16	PA12	I/O	FT_uf	-	TIM1_ETR, I2C6_SDA, I2C5_SDA, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, FDCAN1_TX, LCD_R5, EVENTOUT	OTG_FS_DP
-	G8	-	J11	VSS	S	-	-	-	-
-	-	-	L8	VDDCORE	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number				structure Pin functions	structure Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	Notes	Alternate functions	Additional functions
U15	V17	AA18	Y16	PA11	I/O	-	TIM1_CH4, I2C6_SCL, I2C5_SCL, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, LCD_R4, EVENTOUT	OTG_FS_DM
1C6	H12	1D3	-	VDDCORE	S	-	-	-
1F4	G10	AC23	-	VSS	S	-	-	-
-	W15	AA17	AB16	VDD3V3_ USBFS	S	-	-	-
V16	U15	AC19	V15	OTG_VBUS	A	-	-	OTG_FS_VBUS, OTG_HS_VBUS
U16	T16	Y17	Y17	PA10	I/O	-	TIM1_CH3,SPI3_NSS/I2S3_WS, USART1_RX, MDIOS_MDIO, SAI4_FS_B, DCMI_D1, LCD_B1, EVENTOUT	OTG_FS_ID, OTG_HS_ID
-	-	AB20	AB20	DDR_DQ27	I/O	-	-	-
1B9	E15	1A8	E18	VDDQ_DDR	S	-	-	-
-	-	AB21	AB21	DDR_DQ26	I/O	-	-	-
-	G12	-	J13	VSS	S	-	-	-
-	-	AC22	AA21	DDR_DQ28	I/O	-	-	-
1H4	G14	1A3	J17	VSS	S	-	-	-
-	-	AC21	AA20	DDR_DQ29	I/O	-	-	-
-	-	Y22	W20	DDR_DQ25	I/O	-	-	-
-	-	AB22	Y21	DDR_DQS3P	I/O	-	-	-
-	H5	-	J20	VSS	S	-	-	-
-	-	AB23	Y22	DDR_DQS3N	I/O	-	-	-
-	-	-	F17	VDDQ_DDR	S	-	-	-
-	-	AA20	AA22	DDR_DQM3	O	-	-	-
-	F14	1B7	-	VDDQ_DDR	S	-	-	-
-	-	AA22	W21	DDR_DQ31	I/O	-	-	-
-	H7	1A5	K3	VSS	S	-	-	-
-	-	AA23	W22	DDR_DQ30	I/O	-	-	-
U9	H9	1A7	K7	VSS	S	-	-	-
-	-	Y23	V22	DDR_DQ24	I/O	-	-	-
-	-	-	G16	VDDQ_DDR	S	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	-	-	L10	VDDCORE	S	-	-	-	-
W16	W16	AC20	AB19	DDR_VREF	A	A	-	-	-
-	H11	-	K10	VSS	S	-	-	-	-
W17	W18	W23	V20	DDR_DQ12	I/O	DDR	-	-	-
1C5	H13	1B2	K12	VSS	S	-	-	-	-
V17	W17	Y21	V21	DDR_DQ15	I/O	DDR	-	-	-
-	H15	-	K14	VSS	S	-	-	-	-
U17	V18	W22	U21	DDR_DQ14	I/O	DDR	-	-	-
W18	V19	W21	T20	DDR_DQ11	I/O	DDR	-	-	-
-	G15	1B9	H17	VDDQ_DDR	S	-	-	-	-
V19	U19	U22	T22	DDR_DQS1P	I/O	DDR	-	-	-
1E5	-	1B4	L9	VSS	S	-	-	-	-
U18	T19	U23	R22	DDR_DQS1N	I/O	DDR	-	-	-
V18	U18	V22	T21	DDR_DQM1	O	DDR	-	-	-
1D9	-	-	J16	VDDQ_DDR	S	-	-	-	-
T18	T18	T23	R20	DDR_DQ13	I/O	DDR	-	-	-
-	J3	1B6	-	VSS	S	-	-	-	-
U19	T17	U21	R21	DDR_DQ9	I/O	DDR	-	-	-
1G5	J6	-	L11	VSS	S	-	-	-	-
T19	R18	T22	P21	DDR_DQ10	I/O	DDR	-	-	-
-	H14	-	-	VDDQ_DDR	S	-	-	-	-
R18	P18	T21	N22	DDR_DQ8	I/O	DDR	-	-	-
-	J8	1B8	L13	VSS	S	-	-	-	-
1J5	J10	-	L17	VSS	S	-	-	-	-
1F8	N19	Y19	AA19	DDR_ATO	A	A	-	-	-
-	J7	-	-	VDDCORE	S	-	-	-	-
-	-	1C8	-	VDDQ_DDR	S	-	-	-	-
1G9	N16	W20	U19	DDR_A6	O	DDR	-	-	-
-	-	-	K17	VDDQ_DDR	S	-	-	-	-
T17	R17	Y20	U18	DDR_A8	O	DDR	-	-	-
-	J12	1C1	L19	VSS	S	-	-	-	-
R17	P17	V20	T18	DDR_A4	O	DDR	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number				Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	Notes	Alternate functions	Additional functions
1A6	J14	1C3	L20	VSS	S	-	-	-
P17	P19	T20	R19	DDR_CKE	O DDR	-	-	-
P18	N17	U20	R18	DDR_BA1	O	DDR -	-	-
-	J15	-	L16	VDDQ_DDR	S	-	-	-
N18	N18	R21	P18	DDR_A14	O	DDR -	-	-
-	K2	-	M7	VSS	S	-	-	-
N19	M18	R20	P19	DDR_A11	O	DDR -	-	-
-	K5	1C5	M10	VSS	S	-	-	-
1D6	K7	-	M12	VSS	S	-	-	-
M17	M19	R22	N18	DDR_A10	O	DDR -	-	-
-	J9	1D5	L12	VDDCORE	S	-	-	-
-	-	1D9	-	VDDQ_DDR	S	-	-	-
M18	L17	P23	N19	DDR_A12	O	DDR -	-	-
M19	M17	P22	M18	DDR_A1	O	DDR -	-	-
-	K9	1C7	M14	VSS	S	-	-	-
J19	K17	N20	M22	DDR_CASN	O	DDR -	-	-
1F6	K11	-	N9	VSS	S	-	-	-
J18	J17	M20	M21	DDR_WEN	O	DDR -	-	-
-	K14	-	M17	VDDQ_DDR	S	-	-	-
1E9	L18	N21	M20	DDR_RASN	O	DDR -	-	-
L17	L19	N22	N20	DDR_CLKP	O	DDR -	-	-
-	K13	1C9	-	VSS	S	-	-	-
K18	K19	N23	N21	DDR_CLKN	O S	DDR -	-	-
1F9	-	1E8	N16	VDDQ_DDR		-	-	-
1D8	K18	K20	L22	DDR_DTO0	O	DDR -	-	-
1C8	J19	L21	K21	DDR_DTO1	O	DDR -	-	-
L18	L16	P20	M19	DDR_A15	O	DDR -	-	-
1H6	-	1D2	N11	VSS	S	-	-	-
1E6	-	-	-	VDDCORE	S	-	-	-
-	K15	-	N13	VSS	S	-	-	-
J17	J18	M22	L18	DDR_CSN	O	DDR	-	-
H18		L22	L21	DDR_ODT		-
	H19				O	DDR -	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number				Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	Notes	Alternate functions	Additional functions
H17	J16	M21	K18	DDR_BA2	O	-	-	-
1C7	L6	1D4	N17	VSS	S	-	-	-
G18	H18	L20	K19	DDR_A0	O	-	-	-
-	L15	-	P17	VDDQ_DDR	S	-	-	-
G19	G19	L23	K20	DDR_BA0	O	-	-	-
E17	F17	F20	G18	DDR_A13	O	-	-	-
-	L8	-	P3	VSS	S	-	-	-
F17	G18	J20	J18	DDR_A2	O	-	-	-
1E7	L10	1D6	P7	VSS	S	-	-	-
F19	F19	K22	J19	DDR_A3	O	-	-	-
-	-	1F9	-	VDDQ_DDR	S	-	-	-
C16	G16	D20	F19	DDR_ RESETN	O	-	-	-
-	M14	-	R16	VDDQ_DDR	S	-	-	-
1C9	H17	H20	H19	DDR_A5	O	-	-	-
-	L12	1D8	P10	VSS	S	-	-	-
1A9	E17	E20	F18	DDR_A7	O	-	-	-
-	L14	-	P12	VSS	S	-	-	-
1A8	F18	K23	K22	DDR_ZQ	A	-	-	-
E18	G17	G20	H18	DDR_A9	O	-	-	-
1G7	M5	1E1	P14	VSS	S	-	-	-
-	J11	1D7	L14	VDDCORE	S	-	-	-
D18	E18	J21	J21	DDR_DQ4	I/O	-	-	-
-	M7	-	P20	VSS	S	-	-	-
D19	D17	J22	H20	DDR_DQ5	I/O	-	-	-
W13	M9	1E3	-	VSS	S	-	-	-
C18	D18	H21	H21	DDR_DQ2	I/O	-	-	-
-	-	-	T17	VDDQ_DDR	S	-	-	-
C19	D19	H22	H22	DDR_DQ6	I/O	-	-	-
-	-	1G8	-	VDDQ_DDR	S	-	-	-
B19	C19	G22	G22 R8	DDR_DQS0P VSS	I/O	-	-	-
-	M11	-			S	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number				Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	Notes	Alternate functions	Additional functions
B18	B19	G23	G21	DDR_DQS0N	I/O	DDR -	-	-
-	N15	-	-	VDDQ_DDR	S	-	-	-
C17	C18	H23	G20	DDR_DQM0	O	DDR -	-	-
1H9	-	-	U16	VDDQ_DDR	S	-	-	-
B17	B18	G21	G19	DDR_DQ7	I/O	DDR -	-	-
1B8	M13	1E5	R17	VSS	S	-	-	-
A18	A18	F22	F21	DDR_DQ1	I/O	DDR -	-	-
-	M15	1E7	T7	VSS	S	-	-	-
A17	A17	E22	E21	DDR_DQ0	I/O	DDR -	-	-
B16	B17	E21	E20	DDR_DQ3	I/O	DDR -	-	-
-	P14	1H9	V17	VDDQ_DDR	S	-	-	-
1H8	-	-	T9	VSS	S	-	-	-
-	J13	-	-	VDDCORE	S	-	-	-
-	-	E23	E22	DDR_DQ21	I/O	DDR -	-	-
-	N6	1E9	T11	VSS	S	-	-	-
-	-	D21	D20	DDR_DQ22	I/O	DDR -	-	-
C14	N8	-	T19	VSS	S	-	-	-
-	-	D22	D21	DDR_DQ17	I/O	DDR -	-	-
-	-	D23	D22	DDR_DQ18	I/O	DDR -	-	-
-	-	-	W18	VDDQ_DDR	S	-	-	-
-	-	C22	C21	DDR_DQS2P	I/O	DDR -	-	-
-	N10	1F2	U7	VSS	S	-	-	-
-	-	B23	B22	DDR_DQS2N	I/O	DDR -	-	-
-	R15	1J8	-	VDDQ_DDR	S	-	-	-
-	-	C23	C22	DDR_DQM2	O	DDR -	-	-
-	-	-	Y19	VDDQ_DDR	S	-	-	-
-	-	B22	B21	DDR_DQ16	I/O	DDR -	-	-
-	N12	1F4	U13	VSS	S	-	-	-
-	-	A22	A21	DDR_DQ23	I/O	DDR -	-	-
1J9	N14	-	U15	VSS	S	-	-	-
-	-	B21	B20	DDR_DQ19	I/O	DDR	-	-
-	-	A21	A20	DDR_DQ20	I/O	- DDR -	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number				Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	Notes	Alternate functions	Additional functions
-	-	1J4	-	VDD	S	-	-	-
-	P7	1F6	-	VSS	S	-	-	-
-	-	-	M11	VDDCORE	S	-	-	-
C15	D15	C20	E17	JTMS-SWDIO	I/O	-	-	-
A16	D16	B20	D17	JTCK-SWCLK	I	-	-	-
A15	D14	A19	E16	JTDO- TRACESWO	O	-	-	-
B15	D13	A20	D16	JTDI	I	-	-	-
1G6	K8	1E2	-	VDDCORE	S	-	-	-
B14	D12	B19	E15	NJTRST	I	-	-	-
-	G13	-	D18	VDD_PLL2	S	-	-	-
-	F13	-	D19	VSS_PLL2	S	-	-	-
1B6	B12	C14	B14	VDDA1V8_DSI	S	-	-	-
-	C12	C16	C14	VSS_DSI	S	-	-	-
-	C13	-	C15	VSS_DSI	S	-	-	-
A13	B15	B17	B17	DSI_D1P	A	-	-	-
B13	A15	A17	A17	DSI_D1N	A	-	-	-
1B7	A16	C17	A18	VDD1V2_DSI_ PHY	S	-	-	-
B12	A14	A16	A16	DSI_CKN	A	-	-	-
A12	B14	B16	B16	DSI_CKP	A	-	-	-
-	C14	-	C16	VSS_DSI	S	-	-	-
-	C15	-	C17	VSS_DSI	S	-	-	-
-	C16	-	C18	VSS_DSI	S	-	-	-
B11	B13	C15	B15	DSI_D0P	A	-	-	-
C12	A13	B15	A15	DSI_D0N	A	-	-	-
-	P8	-	T13	VDD	S	-	-	-
C13	A12	B18	A14	VDD_DSI	S	-	-	-
1A7	B16	C18	B18	VDD1V2_DSI_ REG	S	-	-	-
D17	P9	-	U17	VSS	S	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
C11	A11	D16	D15	PC11	I/O	FT_ha	-	TRACED3, DFSDM1_DATIN5, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SAI4_SCK_B, SDMMC1_D3, DCMI_D4, EVENTOUT	-
-	K10	-	-	VDDCORE	S	-	-	-	-
A10	B11	D19	F15	PE4	I/O	FT_h	-	TRACED1, SAI1_D2, DFSDM1_DATIN3,TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SDMMC2_CKIN, SDMMC1_CKIN, SDMMC2_D4, SDMMC1_D4, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT	-
-	-	-	M13	VDDCORE	S	-	-	-	-
A9	C11	D18	E14	PC8	I/O	FT_ha	-	TRACED0, TIM3_CH3, TIM8_CH3, UART4_TX, USART6_CK, UART5_RTS/UART5_DE, SDMMC1_D0, DCMI_D2, EVENTOUT	-
-	P11	1F8	U20	VSS	S	-	-	-	-
B10	D11	D15	F14	PC10	I/O	FT_ha	-	TRACED2, DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SAI4_MCLK_B, SDMMC1_D2, DCMI_D8, LCD_R2, EVENTOUT	-
1D7	K12	1E4	-	VDDCORE	S	-	-	-	-
B6	B9	B13	C13	PB4	I/O	FT_ha	-	TRACED8, TIM16_BKIN, TIM3_CH1, SAI4_CK2, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, SAI4_SCK_A, UART7_TX, EVENTOUT	-
B9	A10	D17	D14	PC9	I/O	FT_fh	-	TRACED1, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDMMC1_D1, DCMI_D3, LCD_B2, EVENTOUT	-
G17	P13	1G3	V5	VSS	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
C10	A9	B11	D13	PC7	I/O	FT_ha	-	HDP4, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, SDMMC2_D123DIR, SDMMC2_D7, SDMMC1_D7, DCMI_D1, LCD_G6, EVENTOUT	-
-	L9	-	M15	VDDCORE	S	-	-	-	-
A4	D10	B14	E13	PC6	I/O	FT_ha	-	HDP1, TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, SDMMC2_D0DIR,SDMMC2_D6, DSI_TE, SDMMC1_D6, DCMI_D0, LCD_HSYNC, EVENTOUT	-
-	-	A14	F13	PF2	I/O	FT_h	-	I2C2_SMBA, SDMMC2_D0DIR, SDMMC3_D0DIR, SDMMC1_D0DIR, FMC_A2, EVENTOUT	-
1A5	B10	D12	D12	PD2	I/O	FT_ha	-	TIM3_ETR, I2C5_SMBA, UART4_RX, UART5_RX, SDMMC1_CMD, DCMI_D11, EVENTOUT	-
1G4	P10	-	-	VDD	S	-	-	-	-
-	P15	-	V16	VSS	S	-	-	-	-
-	-	1E6	-	VDDCORE	S	-	-	-	-
B8	B8	A13	B13	PA8	I/O	FT_fh	-	MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI3_MOSI/I2S3_SDO, USART1_CK, SDMMC2_CKIN, SDMMC2_D4, OTG_FS_SOF/OTG_HS_SOF, SAI4_SD_B, UART7_RX, LCD_R6, EVENTOUT	-
1A4	C9	C13	A13	PB14	I/O	FT_h	-	TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/USART3_DE, SDMMC2_D0, EVENTOUT	-
1B4	C10	D13	E12	PC12	I/O	FT_h	-	TRACECLK, MCO2, SAI4_D3, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SAI4_SD_B, SDMMC1_CK, DCMI_D9, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
K17	R2	1G5	V18	VSS	S	-	-	-	-
C8	A8	B12	B12	PB15	I/O	FT_h	-	RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, DFSDM1_CKIN2, SDMMC2_D1, EVENTOUT	-
-	L11	-	N12	VDDCORE	S	-	-	-	-
B7	B7	C11	C12	PE5	I/O	FT_h	-	TRACED3, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SDMMC2_D0DIR, SDMMC1_D0DIR,SDMMC2_D6, SDMMC1_D6, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT	-
-	-	-	U12	VDD	S	-	-	-	-
C7	A7	A11	A12	PB3	I/O	FT_h	-	TRACED9, TIM2_CH2, SAI4_CK1, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, SAI4_MCLK_A, UART7_RX, EVENTOUT	-
-	R6	-	V19	VSS	S	-	-	-	-
B5	A6	A10	D11	PG6	I/O	FT_h	-	TRACED14, TIM17_BKIN, SDMMC2_CMD, DCMI_D12, LCD_R7, EVENTOUT	-
1F7	-	-	-	VDDCORE	S	-	-	-	-
A7	C6	D14	B11	PD3	I/O	FT_h	-	HDP5, DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS/USART2_NSS, SDMMC1_D123DIR, SDMMC2_D7, SDMMC2_D123DIR, SDMMC1_D7, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT	-
C9	D9	B10	F12	PB9	I/O	FT_fh	-	HDP7, TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC2_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, SDMMC1_CDIR, SDMMC1_D5, DCMI_D7, LCD_B7, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
B4	C7	C19	E11	PA15	I/O	FT_h	-	DBTRGI, TIM2_CH1/TIM2_ETR, SAI4_D2, SDMMC1_CDIR, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE, SDMMC2_D5, SDMMC2_CDIR, SDMMC1_D5, SAI4_FS_A, UART7_TX, LCD_R1, EVENTOUT	-
N17	-	1G7	W17	VSS	S	-	-	-	-
C6	C8	A8	A11	PA9	I/O	FT_h	-	TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, SDMMC2_CDIR, SDMMC2_D5, DCMI_D0,	-
A3	B5	D11	F11	PB7	I/O	FT_fh	-	LCD_R5, EVENTOUT TIM17_CH1N, TIM4_CH2, I2C1_SDA, I2C4_SDA, USART1_RX, SDMMC2_D1, DFSDM1_CKIN5, FMC_NL, DCMI_VSYNC, EVENTOUT	-
-	L13	1F5	N14	VDDCORE	S	-	-	-	-
A2	A4	B9	B10	PD1	I/O	FT_fh	-	I2C6_SCL, DFSDM1_DATIN6, I2C5_SCL, SAI3_SD_A, UART4_TX, FDCAN1_TX, SDMMC3_D0, DFSDM1_CKIN7, FMC_AD3/FMC_D3, EVENTOUT	-
-	R9	1J6	-	VDD	S	-	-	-	-
C5	A3	B8	C10	PD0	I/O	FT_fh	-	I2C6_SDA, DFSDM1_CKIN6, I2C5_SDA, SAI3_SCK_A, UART4_RX, FDCAN1_RX, SDMMC3_CMD, DFSDM1_DATIN7, FMC_AD2/FMC_D2, EVENTOUT	-
-	R8	-	W19	VSS	S	-	-	-	-
1A3	A5	C9	A10	PE3	I/O	FT_h	-	TRACED0, TIM15_BKIN, SAI1_SD_B, SDMMC2_CK, FMC_A19, EVENTOUT	-
C4	D7	A7	A9	PD5	I/O	FT_h	-	USART2_TX, SDMMC3_D2, FMC_NWE, EVENTOUT	-
B3	B4	D10	F10	PD7	I/O	FT_fh	-	TRACED6, DFSDM1_DATIN4, I2C2_SCL, DFSDM1_CKIN1, USART2_CK, SPDIFRX_IN1, SDMMC3_D3, FMC_NE1,	-
-	M10	-	-	VDDCORE	S	-	-	-	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
B1	A2	B7	D10	PG15	I/O	FT_fh	-	TRACED7, SAI1_D2, I2C2_SDA, SAI1_FS_A, USART6_CTS/USART6_NSS, SDMMC3_CK, DCMI_D13, EVENTOUT	-
B2	B3	C10	E9	PE6	I/O	FT_h	-	TRACED2, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SDMMC2_D0, SDMMC1_D2, SAI2_MCLK_B, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT	-
-	R10	1G9	Y3	VSS	S	-	-	-	-
-	-	D8	E10	PF0	I/O	FT_fh	-	I2C2_SDA, SDMMC3_D0, SDMMC3_CKIN, FMC_A0, EVENTOUT	-
-	-	-	P13	VDDCORE	S	-	-	-	-
-	-	A5	B9	PF1	I/O	FT_fh	-	I2C2_SCL, SDMMC3_CMD, SDMMC3_CDIR, FMC_A1, EVENTOUT	-
F18	R12	1H4	-	VSS	S	-	-	-	-
-	-	D9	F9	PF4	I/O	FT_h	-	USART2_RX, SDMMC3_D1, SDMMC3_D123DIR, FMC_A4, EVENTOUT	-
1E8	M12	1F7	-	VDDCORE	S	-	-	-	-
C3	D6	B6	C9	PD4	I/O	FT_h	-	SAI3_FS_A, USART2_RTS/USART2_DE, SDMMC3_D1, DFSDM1_CKIN0, FMC_NOE, EVENTOUT	-
-	-	-	U14	VDD	S	-	-	-	-
-	-	D7	D9	PF5	I/O	FT_h	-	USART2_TX, SDMMC3_D2, FMC_A5, EVENTOUT	-
-	R14	-	Y7	VSS	S	-	-	-	-
1A2	C5	B5	A8	PD10	I/O	FT_h	-	RTC_REFIN, TIM16_BKIN, DFSDM1_CKOUT, I2C5_SMBA, SPI3_MISO/I2S3_SDI, SAI3_FS_B, USART3_CK, FMC_AD15/FMC_D15, LCD_B3, EVENTOUT	-
-	N11	-	P15	VDDCORE	S	-	-	-	-
-	-	-	B8	PJ12	I/O	FT	-	LCD_G3, LCD_B0, EVENTOUT	-
-	-	-	A7	PJ13	I/O	FT	-	LCD_G4, LCD_B1, EVENTOUT	-
-	-	-	B7	PJ14	I/O	FT	-	LCD_B2, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
A19	R16	1H6	Y10	VSS	S	-	-	-	-
-	-	-	C7	PJ15	I/O	FT	-	LCD_B3, EVENTOUT	-
-	-	1G6	-	VDDCORE	S	-	-	-	-
-	-	-	D8	PK0	I/O	FT_h	-	TIM1_CH1N, TIM8_CH3, SPI5_SCK, LCD_G5, EVENTOUT	-
-	-	-	E7	PK1	I/O	FT_h	-	TRACED4, TIM1_CH1, HDP4, TIM8_CH3N, SPI5_NSS, LCD_G6, EVENTOUT	-
-	-	-	E8	PK2	I/O	FT_h	-	TRACED5, TIM1_BKIN, HDP5, TIM8_BKIN, LCD_G7, EVENTOUT	-
-	R11	-	-	VDD	S	-	-	-	-
-	T4	-	Y18	VSS	S	-	-	-	-
-	N13	-	R14	VDDCORE	S	-	-	-	-
-	-	-	B6	PK3	I/O	FT	-	LCD_B4, EVENTOUT	-
-	-	-	A6	PK4	I/O	FT	-	LCD_B5, EVENTOUT	-
-	-	-	C6	PK5	I/O	FT_h	-	TRACED6, HDP6, LCD_B6, EVENTOUT	-
K19	U3	1H8	Y20	VSS	S	-	-	-	-
-	-	-	A5	PK6	I/O	FT_h	-	TRACED7, HDP7, LCD_B7, EVENTOUT	-
1G8	P12	-	-	VDDCORE	S	-	-	-	-
-	-	-	B5	PK7	I/O	FT	-	LCD_DE, EVENTOUT	-
C2	C4	D6	C5	PE0	I/O	FT_h	-	LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR, SPI3_SCK/I2S3_CK, SAI4_MCLK_B, UART8_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT	-
1A1	B1	C8	D7	PE1	I/O	FT	-	LPTIM1_IN2, I2S2_MCK, SAI3_SD_B, UART8_TX, FMC_NBL1, DCMI_D3, EVENTOUT	-
-	U6	1J3	AA4	VSS	S	-	-	-	-
-	-	D5	D6	PH8	I/O	FT_f	-	TIM5_ETR, I2C3_SDA, DCMI_HSYNC, LCD_R2, EVENTOUT	-
-	-	1H7	T15	VDDCORE	S	-	-	-	-
-	-	C5	E6	PH9	I/O	FT	-	TIM12_CH2, I2C3_SMBA, DCMI_D0, LCD_R3, EVENTOUT	-

Table 7. STM32MP157C/F pin and ball definitions (continued)

Table 7. STM32MP157C/F pin and ball definitions (continued)

Pin Number	Pin Number	Pin Number	Pin Number					Pin functions	Pin functions
TFBGA257	LFBGA354	TFBGA361	LFBGA448	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
D2	C1	A4	D5	PE11	I/O	FT	-	TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS, USART6_CK, SAI2_SD_B, FMC_AD8/FMC_D8, DCMI_D4, LCD_G3, EVENTOUT	-
C1	D2	B4	E4	PE12	I/O	FT_h	-	TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK, SDMMC1_D0DIR, SAI2_SCK_B, FMC_AD9/FMC_D9, LCD_B4, EVENTOUT	-
E3	C2	A3	A4	PE13	I/O	FT_h	-	HDP2, TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_AD10/FMC_D10, DCMI_D6, LCD_DE, EVENTOUT	-
-	R13	-	-	VDDCORE	S	-	-	-	-
-	-	C4	B3	PH11	I/O	FT_f	-	TIM5_CH2, I2C4_SCL, I2C1_SCL, DCMI_D2, LCD_R5, EVENTOUT	-
R19	U8	-	AA18	VSS	S	-	-	-	-
-	U17	1J5	AB1	VSS	S	-	-	-	-
W19	W1	-	AB18	VSS	S	-	-	-	-
-	W19	1J7	AB22	VSS	S	-	-	-	-
1B2	D3	C6	B4	PE14	I/O	FT_h	-	TIM1_CH4, SPI4_MOSI, UART8_RTS/UART8_DE, SAI2_MCLK_B, SDMMC1_D123DIR, FMC_AD11/FMC_D11, LCD_G0, LCD_CLK, EVENTOUT	-
D3	E1	D3	C4	PE15	I/O	FT	-	HDP3,TIM1_BKIN, TIM15_BKIN, USART2_CTS/USART2_NSS, UART8_CTS, FMC_NCE2, FMC_AD12/FMC_D12, LCD_R7, EVENTOUT	-
-	-	B3	A3	PH4	I/O	FT_f	-	I2C2_SCL, LCD_G5, LCD_G4, EVENTOUT	-

IO supplied by VSW domain.

Table 7. STM32MP157C/F pin and ball definitions (continued)

121

Table 8. Alternate function AF0 to AF7 (1)

Table 8. Alternate function AF0 to AF7 (1)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PA0	-	TIM2_CH1/ TIM2_ETR	TIM5_CH1	TIM8_ETR	TIM15_BKIN	-	-	USART2_CTS/ USART2_NSS
	PA1	ETH_CLK	TIM2_CH2	TIM5_CH2	LPTIM3_OUT	TIM15_CH1N	-	-	USART2_RTS/ USART2_DE
	PA2	-	TIM2_CH3	TIM5_CH3	LPTIM4_OUT	TIM15_CH1	-	-	USART2_TX
	PA3	-	TIM2_CH4	TIM5_CH4	LPTIM5_OUT	TIM15_CH2	-	-	USART2_RX
	PA4	HDP0	-	TIM5_ETR	-	SAI4_D2	SPI1_NSS/ I2S1_WS	SPI3_NSS/ I2S3_WS	USART2_CK
	PA5	-	TIM2_CH1/ TIM2_ETR	-	TIM8_CH1N	SAI4_CK1	SPI1_SCK/I2S1 _CK	-	-
	PA6	-	TIM1_BKIN	TIM3_CH1	TIM8_BKIN	SAI4_CK2	SPI1_MISO/ I2S1_SDI	-	-
	PA7	-	TIM1_CH1N	TIM3_CH2	TIM8_CH1N	SAI4_D1	SPI1_MOSI/ I2S1_SDO	-	-
	PA8	MCO1	TIM1_CH1	-	TIM8_BKIN2	I2C3_SCL	SPI3_MOSI/ I2S3_SDO	-	USART1_CK
	PA9	-	TIM1_CH2	-	-	I2C3_SMBA	SPI2_SCK/ I2S2_CK	-	USART1_TX
	PA10	-	TIM1_CH3	-	-	-	SPI3_NSS/ I2S3_WS	-	USART1_RX
	PA11	-	TIM1_CH4	I2C6_SCL	-	I2C5_SCL	SPI2_NSS/ I2S2_WS	UART4_RX	USART1_CTS/ USART1_NSS
	PA12	-	TIM1_ETR	I2C6_SDA	-	I2C5_SDA	-	UART4_TX	USART1_RTS/ USART1_DE

Table 8. Alternate function AF0 to AF7 (1)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PA13	DBTRGO	DBTRGI	MCO1	-	-	-	-	-
	PA14	DBTRGO	DBTRGI	MCO2	-	-	-	-	-
	PA15	DBTRGI	TIM2_CH1/ TIM2_ETR	SAI4_D2	SDMMC1_ CDIR	CEC	SPI1_NSS/ I2S1_WS	SPI3_NSS/ I2S3_WS	SPI6_NSS
	PB0	-	TIM1_CH2N	TIM3_CH3	TIM8_CH2N	-	-	DFSDM1_ CKOUT	-
	PB1	-	TIM1_CH3N	TIM3_CH4	TIM8_CH3N	-	-	DFSDM1_ DATIN1	-
	PB2	TRACED4	RTC_OUT2	SAI1_D1	DFSDM1_ CKIN1	USART1_RX	I2S_CKIN	SAI1_SD_A	SPI3_MOSI/ I2S3_SDO
	PB3	TRACED9	TIM2_CH2	-	-	SAI4_CK1	SPI1_SCK/ I2S1_CK	SPI3_SCK/ I2S3_CK	-
	PB4	TRACED8	TIM16_BKIN	TIM3_CH1	-	SAI4_CK2	SPI1_MISO/ I2S1_SDI	SPI3_MISO/ I2S3_SDI	SPI2_NSS/ I2S2_WS
	PB5	ETH_CLK	TIM17_BKIN	TIM3_CH2	SAI4_D1	I2C1_SMBA	SPI1_MOSI/ I2S1_SDO	I2C4_SMBA	SPI3_MOSI/ I2S3_SDO
	PB6	-	TIM16_CH1N	TIM4_CH1	-	I2C1_SCL	CEC	I2C4_SCL	USART1_TX
	PB7	-	TIM17_CH1N	TIM4_CH2	-	I2C1_SDA	-	I2C4_SDA	USART1_RX
	PB8	HDP6	TIM16_CH1	TIM4_CH3	DFSDM1_ CKIN7	I2C1_SCL	SDMMC1_ CKIN	I2C4_SCL	SDMMC2_ CKIN
	PB9	HDP7	TIM17_CH1	TIM4_CH4	DFSDM1_ DATIN7	I2C1_SDA	SPI2_NSS/ I2S2_WS	I2C4_SDA	SDMMC2_ CDIR
	PB10	-	TIM2_CH3	-	LPTIM2_IN1	I2C2_SCL	SPI2_SCK/ I2S2_CK	DFSDM1_ DATIN7	USART3_TX

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PB11	-	TIM2_CH4	-	LPTIM2_ETR	I2C2_SDA	-	DFSDM1_ CKIN7	USART3_RX
	PB12	-	TIM1_BKIN	I2C6_SMBA	-	I2C2_SMBA	SPI2_NSS/ I2S2_WS	DFSDM1_ DATIN1	USART3_CK
	PB13	-	TIM1_CH1N	-	DFSDM1_ CKOUT	LPTIM2_OUT	SPI2_SCK/ I2S2_CK	DFSDM1_ CKIN1	USART3_CTS/ USART3_NSS
	PB14	-	TIM1_CH2N	TIM12_CH1	TIM8_CH2N	USART1_TX	SPI2_MISO/ I2S2_SDI	DFSDM1_ DATIN2	USART3_RTS/ USART3_DE
	PB15	RTC_REFIN	TIM1_CH3N	TIM12_CH2	TIM8_CH3N	USART1_RX	SPI2_MOSI/ I2S2_SDO	DFSDM1_ CKIN2	-
	PC0	-	-	-	DFSDM1_ CKIN0	LPTIM2_IN2	-	DFSDM1_ DATIN4	-
	PC1	TRACED0	-	SAI1_D1	DFSDM1_ DATIN0	DFSDM1_ CKIN4	SPI2_MOSI/ I2S2_SDO	SAI1_SD_A	-
	PC2	-	-	-	DFSDM1_ CKIN1	-	SPI2_MISO/ I2S2_SDI	DFSDM1_ CKOUT	-
	PC3	TRACECLK	-	-	DFSDM1_ DATIN1	-	SPI2_MOSI/ I2S2_SDO	-	-
	PC4	-	-	-	DFSDM1_ CKIN2	-	I2S1_MCK	-	-
	PC5	-	-	SAI1_D3	DFSDM1_ DATIN2	SAI4_D4	-	SAI1_D4	-
	PC6	HDP1	-	TIM3_CH1	TIM8_CH1	DFSDM1_ CKIN3	I2S2_MCK	-	USART6_TX

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PC7	HDP4	-	TIM3_CH2	TIM8_CH2	DFSDM1_ DATIN3	-	I2S3_MCK	USART6_RX
	PC8	TRACED0	-	TIM3_CH3	TIM8_CH3	-	-	UART4_TX	USART6_CK
	PC9	TRACED1	-	TIM3_CH4	TIM8_CH4	I2C3_SDA	I2S_CKIN	-	-
	PC10	TRACED2	-	-	DFSDM1_ CKIN5	-	-	SPI3_SCK/ I2S3_CK	USART3_TX
	PC11	TRACED3	-	-	DFSDM1_ DATIN5	-	-	SPI3_MISO/ I2S3_SDI	USART3_RX
	PC12	TRACECLK	MCO2	SAI4_D3	-	-	-	SPI3_MOSI/ I2S3_SDO	USART3_CK
	PC13	-	-	-	-	-	-	-	-
	PC14	-	-	-	-	-	-	-	-
	PC15	-	-	-	-	-	-	-	-
	PD0	-	-	I2C6_SDA	DFSDM1_ CKIN6	I2C5_SDA	-	SAI3_SCK_A	-
	PD1	-	-	I2C6_SCL	DFSDM1_ DATIN6	I2C5_SCL	-	SAI3_SD_A	-
	PD2	-	-	TIM3_ETR	-	I2C5_SMBA	-	UART4_RX	-
	PD3	HDP5	-	-	DFSDM1_ CKOUT	-	SPI2_SCK/ I2S2_CK	DFSDM1_ DATIN0	USART2_CTS/ USART2_NSS
	PD4	-	-	-	-	-	-	SAI3_FS_A	USART2_RTS/ USART2_DE
	PD5	-	-	-	-	-	-	-	USART2_TX

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PD6	-	TIM16_CH1N	SAI1_D1	DFSDM1_ CKIN4	DFSDM1_ DATIN1	SPI3_MOSI/ I2S3_SDO	SAI1_SD_A	USART2_RX
	PD7	TRACED6	-	-	DFSDM1_ DATIN4	I2C2_SCL	-	DFSDM1_ CKIN1	USART2_CK
	PD8	-	-	-	DFSDM1_ CKIN3	-	-	SAI3_SCK_B	USART3_TX
	PD9	-	-	-	DFSDM1_ DATIN3	-	-	SAI3_SD_B	USART3_RX
	PD10	RTC_REFIN	TIM16_BKIN	-	DFSDM1_ CKOUT	I2C5_SMBA	SPI3_MISO/ I2S3_SDI	SAI3_FS_B	USART3_CK
	PD11	-	-	-	LPTIM2_IN2	I2C4_SMBA	I2C1_SMBA	-	USART3_CTS/ USART3_NSS
	PD12	-	LPTIM1_IN1	TIM4_CH1	LPTIM2_IN1	I2C4_SCL	I2C1_SCL	-	USART3_RTS/ USART3_DE
	PD13	-	LPTIM1_OUT	TIM4_CH2	-	I2C4_SDA	I2C1_SDA	I2S3_MCK	-
	PD14	-	-	TIM4_CH3	-	-	-	SAI3_MCLK_B	-
	PD15	-	-	TIM4_CH4	-	-	-	SAI3_MCLK_A	-
	PE0	-	LPTIM1_ETR	TIM4_ETR	-	LPTIM2_ETR	SPI3_SCK/ I2S3_CK	SAI4_MCLK_B	-
Port E	PE1	-	LPTIM1_IN2	-	-	-	I2S2_MCK	SAI3_SD_B	-
Port E	PE2	TRACECLK	-	SAI1_CK1	-	I2C4_SCL	SPI4_SCK	SAI1_MCLK_A	-
Port E	PE3	TRACED0	-	-	-	TIM15_BKIN	-	SAI1_SD_B	-

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PE4	TRACED1	-	SAI1_D2	DFSDM1_ DATIN3	TIM15_CH1N	SPI4_NSS	SAI1_FS_A	SDMMC2_ CKIN
	PE5	TRACED3	-	SAI1_CK2	DFSDM1_ CKIN3	TIM15_CH1	SPI4_MISO	SAI1_SCK_A	SDMMC2_ D0DIR
	PE6	TRACED2	TIM1_BKIN2	SAI1_D1	-	TIM15_CH2	SPI4_MOSI	SAI1_SD_A	SDMMC2_D0
	PE7	-	TIM1_ETR	TIM3_ETR	DFSDM1_ DATIN2	-	-	-	UART7_RX
	PE8	-	TIM1_CH1N	-	DFSDM1_ CKIN2	-	-	-	UART7_TX
	PE9	-	TIM1_CH1	-	DFSDM1_ CKOUT	-	-	-	UART7_RTS/ UART7_DE
	PE10	-	TIM1_CH2N	-	DFSDM1_ DATIN4	-	-	-	UART7_CTS
	PE11	-	TIM1_CH2	-	DFSDM1_ CKIN4	-	SPI4_NSS	-	USART6_CK
	PE12	-	TIM1_CH3N	-	DFSDM1_ DATIN5	-	SPI4_SCK	-	-
	PE13	HDP2	TIM1_CH3	-	DFSDM1_ CKIN5	-	SPI4_MISO	-	-
	PE14	-	TIM1_CH4	-	-	-	SPI4_MOSI	-	-
	PE15	HDP3	TIM1_BKIN	-	-	TIM15_BKIN	-	-	USART2_CTS/ USART2_NSS
	PF0	-	-	-	-	I2C2_SDA	-	-	-
	PF1	-	-	-	-	I2C2_SCL	-	-	-

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PF2	-	-	-	-	I2C2_SMBA	-	-	-
	PF3	-	-	-	-	-	-	-	-
	PF4	-	-	-	-	-	-	-	USART2_RX
	PF5	-	-	-	-	-	-	-	USART2_TX
	PF6	-	TIM16_CH1	-	-	-	SPI5_NSS	SAI1_SD_B	UART7_RX
	PF7	-	TIM17_CH1	-	-	-	SPI5_SCK	SAI1_MCLK_B	UART7_TX
	PF8	TRACED12	TIM16_CH1N	-	-	-	SPI5_MISO	SAI1_SCK_B	UART7_RTS/ UART7_DE
	PF9	TRACED13	TIM17_CH1N	-	-	-	SPI5_MOSI	SAI1_FS_B	UART7_CTS
	PF10	-	TIM16_BKIN	SAI1_D3	SAI4_D4	-	-	SAI1_D4	-
	PF11	-	-	-	-	-	SPI5_MOSI	-	-
	PF12	TRACED4	-	-	-	-	-	-	-
	PF13	TRACED5	-	-	DFSDM1_ DATIN6	I2C4_SMBA	I2C1_SMBA	DFSDM1_ DATIN3	-
	PF14	TRACED6	-	-	DFSDM1_ CKIN6	I2C4_SCL	I2C1_SCL	-	-
	PF15	TRACED7	-	-	-	I2C4_SDA	I2C1_SDA	-	-
	PG0	TRACED0	-	-	DFSDM1_ DATIN0	-	-	-	-
	PG1	TRACED1	-	-	-	-	-	-	-
	PG2	TRACED2	MCO2	-	TIM8_BKIN	-	-	-	-

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PG3	TRACED3	-	-	TIM8_BKIN2	DFSDM1_ CKIN1	-	-	-
	PG4	-	TIM1_BKIN2	-	-	-	-	-	-
	PG5	-	TIM1_ETR	-	-	-	-	-	-
	PG6	TRACED14	TIM17_BKIN	-	-	-	-	-	-
	PG7	TRACED5	-	-	-	-	-	SAI1_MCLK_A	USART6_CK
	PG8	TRACED15	TIM2_CH1/ TIM2_ETR	ETH_CLK	TIM8_ETR	-	SPI6_NSS	SAI4_D2	USART6_RTS/ USART6_DE
	PG9	DBTRGO	-	-	-	-	-	-	USART6_RX
	PG10	TRACED10	-	-	-	-	-	-	-
	PG11	TRACED11	-	-	-	USART1_TX	-	UART4_TX	-
	PG12	-	LPTIM1_IN1	-	-	-	SPI6_MISO	SAI4_CK2	USART6_RTS/ USART6_DE
	PG13	TRACED0	LPTIM1_OUT	SAI1_CK2	-	SAI4_CK1	SPI6_SCK	SAI1_SCK_A	USART6_CTS/ USART6_NSS
	PG14	TRACED1	LPTIM1_ETR	-	-	-	SPI6_MOSI	SAI4_D1	USART6_TX
	PG15	TRACED7	-	SAI1_D2	-	I2C2_SDA	-	SAI1_FS_A	USART6_CTS/ USART6_NSS
	PH0	-	-	-	-	-	-	-	-
	PH1	-	-	-	-	-	-	-	-
	PH2	-	LPTIM1_IN2	-	-	-	-	-	-

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PH3	-	-	-	DFSDM1_ CKIN4	-	-	-	-
	PH4	-	-	-	-	I2C2_SCL	-	-	-
	PH5	-	-	-	-	I2C2_SDA	SPI5_NSS	-	-
	PH6	-	-	TIM12_CH1	-	I2C2_SMBA	SPI5_SCK	-	-
	PH7	-	-	-	-	I2C3_SCL	SPI5_MISO	-	-
	PH8	-	-	TIM5_ETR	-	I2C3_SDA	-	-	-
	PH9	-	-	TIM12_CH2	-	I2C3_SMBA	-	-	-
	PH10	-	-	TIM5_CH1	-	I2C4_SMBA	I2C1_SMBA	-	-
	PH11	-	-	TIM5_CH2	-	I2C4_SCL	I2C1_SCL	-	-
	PH12	HDP2	-	TIM5_CH3	-	I2C4_SDA	I2C1_SDA	-	-
	PH13	-	-	-	TIM8_CH1N	-	-	-	-
	PH14	-	-	-	TIM8_CH2N	-	-	-	-
	PH15	-	-	-	TIM8_CH3N	-	-	-	-
	PI0	-	-	TIM5_CH4	-	-	SPI2_NSS/ I2S2_WS	-	-
	PI1	-	-	-	TIM8_BKIN2	-	SPI2_SCK/ I2S2_CK	-	-
	PI2	-	-	-	TIM8_CH4	-	SPI2_MISO/ I2S2_SDI	-	-
	PI3	-	-	-	TIM8_ETR	-	SPI2_MOSI/ I2S2_SDO	-	-

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PI4	-	-	-	TIM8_BKIN	-	-	-	-
	PI5	-	-	-	TIM8_CH1	-	-	-	-
	PI6	-	-	-	TIM8_CH2	-	-	-	-
	PI7	-	-	-	TIM8_CH3	-	-	-	-
	PI8	-	-	-	-	-	-	-	-
	PI9	HDP1	-	-	-	-	-	-	-
	PI10	HDP0	-	-	-	-	-	-	-
	PI11	MCO1	-	-	-	-	I2S_CKIN	-	-
	PI12	TRACED0	-	HDP0	-	-	-	-	-
	PI13	TRACED1	-	HDP1	-	-	-	-	-
	PI14	TRACECLK	-	-	-	-	-	-	-
	PI15	-	-	-	-	-	-	-	-
	PJ0	TRACED8	-	-	-	-	-	-	-
	PJ1	TRACED9	-	-	-	-	-	-	-
	PJ2	TRACED10	-	-	-	-	-	-	-
	PJ3	TRACED11	-	-	-	-	-	-	-
	PJ4	TRACED12	-	-	-	-	-	-	-
	PJ5	TRACED2	-	HDP2	-	-	-	-	-
	PJ6	TRACED3	-	HDP3	TIM8_CH2	-	-	-	-
	PJ7	TRACED13	-	-	TIM8_CH2N	-	-	-	-

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PJ8	TRACED14	TIM1_CH3N	-	TIM8_CH1	-	-	-	-
	PJ9	TRACED15	TIM1_CH3	-	TIM8_CH1N	-	-	-	-
	PJ10	-	TIM1_CH2N	-	TIM8_CH2	-	SPI5_MOSI	-	-
	PJ11	-	TIM1_CH2	-	TIM8_CH2N	-	SPI5_MISO	-	-
	PJ12	-	-	-	-	-	-	-	-
	PJ13	-	-	-	-	-	-	-	-
	PJ14	-	-	-	-	-	-	-	-
	PJ15	-	-	-	-	-	-	-	-
	PK0	-	TIM1_CH1N	-	TIM8_CH3	-	SPI5_SCK	-	-
	PK1	TRACED4	TIM1_CH1	HDP4	TIM8_CH3N	-	SPI5_NSS	-	-
	PK2	TRACED5	TIM1_BKIN	HDP5	TIM8_BKIN	-	-	-	-
	PK3	-	-	-	-	-	-	-	-
	PK4	-	-	-	-	-	-	-	-
	PK5	TRACED6	-	HDP6	-	-	-	-	-
	PK6	TRACED7	-	HDP7	-	-	-	-	-
	PK7	-	-	-	-	-	-	-	-
	PZ0	-	-	I2C6_SCL	I2C2_SCL	-	SPI1_SCK/ I2S1_CK	-	USART1_CK
	PZ1	-	-	I2C6_SDA	I2C2_SDA	I2C5_SDA	SPI1_MISO/ I2S1_SDI	I2C4_SDA	USART1_RX

Table 8. Alternate function AF0 to AF7 (1) (continued)

Table 8. Alternate function AF0 to AF7 (1) (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
Port	Port	HDP/SYS/RTC	TIM1/2/16/17/ LPTIM1/SYS/ RTC	SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS	SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1	SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC	SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC	SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1	SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2
	PZ2	-	-	I2C6_SCL	I2C2_SCL	I2C5_SMBA	SPI1_MOSI/ I2S1_SDO	I2C4_SMBA	USART1_TX
	PZ3	-	-	I2C6_SDA	I2C2_SDA	I2C5_SDA	SPI1_NSS/ I2S1_WS	I2C4_SDA	USART1_CTS/ USART1_NSS
Port Z	PZ4	-	-	I2C6_SCL	I2C2_SCL	I2C5_SCL	-	I2C4_SCL	-
	PZ5	-	-	I2C6_SDA	I2C2_SDA	I2C5_SDA	-	I2C4_SDA	USART1_RTS/ USART1_DE
	PZ6	-	-	I2C6_SCL	I2C2_SCL	USART1_CK	I2S1_MCK	I2C4_SMBA	USART1_RX
	PZ7	-	-	I2C6_SDA	I2C2_SDA	-	-	-	USART1_TX

Refer to Table 9 for AF8 to AF15.

Table 9. Alternate function AF8 to AF15 (1)

Table 9. Alternate function AF8 to AF15 (1)

		AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	Port	SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX	FDCAN1/2/ TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX	SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS	DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1/ DSI	SAI4/UART5/ FMC/SDMMC1/ MDIOS	UART7/DCMI/ LCD/DSI/RNG	UART5/LCD	SYS
	PA0	UART4_TX	SDMMC2_CMD	SAI2_SD_B	ETH1_GMII_ CRS/ ETH1_MII_CRS	-	-	-	EVENTOUT
	PA1	UART4_RX	QUADSPI_ BK1_IO3	SAI2_MCLK_B	ETH1_GMII_RX CLK/ ETH1_MII_RX CLK/ ETH1_RGMII_ RX_CLK/ ETH1_RMII_ REF_CLK	-	-	LCD_R2	EVENTOUT
	PA2	SAI2_SCK_B	-	SDMMC2_ D0DIR	ETH1_MDIO	MDIOS_MDIO	-	LCD_R1	EVENTOUT
	PA3	-	LCD_B2	-	ETH1_GMII_ COL/ ETH1_MII_COL	-	-	LCD_B5	EVENTOUT
	PA4	SPI6_NSS	-	-	-	SAI4_FS_A	DCMI_HSYNC	LCD_VSYNC	EVENTOUT
	PA5	SPI6_SCK	-	-	-	SAI4_MCLK_A	-	LCD_R4	EVENTOUT
	PA6	SPI6_MISO	TIM13_CH1	-	MDIOS_MDC	SAI4_SCK_A	DCMI_PIXCLK	LCD_G2	EVENTOUT
	PA7	SPI6_MOSI	TIM14_CH1	QUADSPI_CLK	ETH1_GMII_RX DV/ ETH1_MII_RX DV/ ETH1_RGMII_ RX_CTL/ ETH1_RMII_ CRS_DV	SAI4_SD_A	-	-	EVENTOUT

Table 9. Alternate function AF8 to AF15 (1)

Table 9. Alternate function AF8 to AF15 (1) (continued)

		AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	Port	SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX	FDCAN1/2/ TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX	SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS	DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1/ DSI	SAI4/UART5/ FMC/SDMMC1/ MDIOS	UART7/DCMI/ LCD/DSI/RNG	UART5/LCD	SYS
	PA8	SDMMC2_ CKIN	SDMMC2_D4	OTG_FS_SOF/ OTG_HS_SOF	-	SAI4_SD_B	UART7_RX	LCD_R6	EVENTOUT
	PA9	SDMMC2_ CDIR	-	SDMMC2_D5	-	-	DCMI_D0	LCD_R5	EVENTOUT
	PA10	-	-	-	MDIOS_MDIO	SAI4_FS_B	DCMI_D1	LCD_B1	EVENTOUT
	PA11	-	FDCAN1_RX	-	-	-	-	LCD_R4	EVENTOUT
	PA12	SAI2_FS_B	FDCAN1_TX	-	-	-	-	LCD_R5	EVENTOUT
	PA13	UART4_TX	-	-	-	-	-	-	EVENTOUT
	PA14	-	-	-	-	-	-	-	EVENTOUT
	PA15	UART4_RTS/ UART4_DE	SDMMC2_D5	SDMMC2_ CDIR	SDMMC1_D5	SAI4_FS_A	UART7_TX	LCD_R1	EVENTOUT
	PB0	UART4_CTS	LCD_R3	-	ETH1_GMII_ RXD2/ ETH1_MII_ RXD2/ ETH1_RGMII_ RXD2	MDIOS_MDIO	-	LCD_G1	EVENTOUT
	PB1	-	LCD_R6	-	ETH1_GMII_ RXD3/ ETH1_MII_ RXD3/ ETH1_RGMII_ RXD3	MDIOS_MDC	-	LCD_G0	EVENTOUT
	PB2	UART4_RX	QUADSPI_CLK	-	-	-	-	-	EVENTOUT
	PB3	SPI6_SCK	SDMMC2_D2	-	-	SAI4_MCLK_A	UART7_RX	-	EVENTOUT

Table 9. Alternate function AF8 to AF15 (1) (continued)

Table 9. Alternate function AF8 to AF15 (1) (continued)

		AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	Port	SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX	FDCAN1/2/ TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX	SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS	DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1/ DSI	SAI4/UART5/ FMC/SDMMC1/ MDIOS	UART7/DCMI/ LCD/DSI/RNG	UART5/LCD	SYS
	PB4	SPI6_MISO	SDMMC2_D3	-	-	SAI4_SCK_A	UART7_TX	-	EVENTOUT
	PB5	SPI6_MOSI	FDCAN2_RX	SAI4_SD_A	ETH1_PPS_ OUT	UART5_RX	DCMI_D10	LCD_G7	EVENTOUT
	PB6	-	FDCAN2_TX	QUADSPI_BK1 _NCS	DFSDM1_ DATIN5	UART5_TX	DCMI_D5	-	EVENTOUT
	PB7	-	-	SDMMC2_D1	DFSDM1_ CKIN5	FMC_NL	DCMI_VSYNC	-	EVENTOUT
	PB8	UART4_RX	FDCAN1_RX	SDMMC2_D4	ETH1_GMII_ TXD3/ ETH1_MII_ TXD3/ ETH1_RGMII_ TXD3	SDMMC1_D4	DCMI_D6	LCD_B6	EVENTOUT
	PB9	UART4_TX	FDCAN1_TX	SDMMC2_D5	SDMMC1_CDI R	SDMMC1_D5	DCMI_D7	LCD_B7	EVENTOUT
	PB10	-	QUADSPI_ BK1_NCS	-	ETH1_GMII_ RX_ER/ ETH1_MII_ RX_ER	-	-	LCD_G4	EVENTOUT
	PB11	-	-	-	ETH1_GMII_ TX_EN/ ETH1_MII_ TX_EN/ ETH1_RGMII_ TX_CTL/ ETH1_RMII_ TX_EN	-	DSI_TE	LCD_G5	EVENTOUT

Table 9. Alternate function AF8 to AF15 (1) (continued)

Table 9. Alternate function AF8 to AF15 (1) (continued)

		AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	Port	SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX	FDCAN1/2/ TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX	SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS	DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1/ DSI	SAI4/UART5/ FMC/SDMMC1/ MDIOS	UART7/DCMI/ LCD/DSI/RNG	UART5/LCD	SYS
	PB12	USART3_RX	FDCAN2_RX	-	ETH1_GMII_ TXD0/ ETH1_MII_ TXD0/ ETH1_RGMII_ TXD0/ ETH1_RMII_ TXD0	-	-	UART5_RX	EVENTOUT
	PB13	-	FDCAN2_TX	-	ETH1_GMII_ TXD1/ ETH1_MII_ TXD1/ ETH1_RGMII_ TXD1/ ETH1_RMII_ TXD1	-	-	UART5_TX	EVENTOUT
	PB14	-	SDMMC2_D0	-	-	-	-	-	EVENTOUT
	PB15	-	SDMMC2_D1	-	-	-	-	-	EVENTOUT
	PC0	SAI2_FS_B	-	QUADSPI_BK2 _NCS	-	-	-	LCD_R5	EVENTOUT
	PC1	-	SDMMC2_CK	-	ETH1_MDC	MDIOS_MDC	-	-	EVENTOUT
	PC2	-	-	-	ETH1_GMII_ TXD2/ ETH1_MII_ TXD2/ ETH1_RGMII_ TXD2	-	DCMI_PIXCLK	-	EVENTOUT

Table 9. Alternate function AF8 to AF15 (1) (continued)

Table 9. Alternate function AF8 to AF15 (1) (continued)

		AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	Port	SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX	FDCAN1/2/ TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX	SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS	DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1/ DSI	SAI4/UART5/ FMC/SDMMC1/ MDIOS	UART7/DCMI/ LCD/DSI/RNG	UART5/LCD	SYS
	PC3	-	-	-	ETH1_GMII_ TX_CLK/ ETH1_MII_ TX_CLK	-	-	-	EVENTOUT
	PC4	-	SPDIFRX_IN3	-	ETH1_GMII_ RXD0/ ETH1_MII_ RXD0/ ETH1_RGMII_ RXD0/ ETH1_RMII_ RXD0	-	-	-	EVENTOUT
	PC5	-	SPDIFRX_IN4	-	ETH1_GMII_ RXD1/ ETH1_MII_ RXD1/ ETH1_RGMII_ RXD1/ ETH1_RMII_ RXD1	SAI4_D3	-	-	EVENTOUT
	PC6	SDMMC1_ D0DIR	SDMMC2_ D0DIR	SDMMC2_D6	DSI_TE	SDMMC1_D6	DCMI_D0	LCD_HSYNC	EVENTOUT
	PC7	SDMMC1_ D123DIR	SDMMC2_ D123DIR	SDMMC2_D7	-	SDMMC1_D7	DCMI_D1	LCD_G6	EVENTOUT
	PC8	UART5_RTS/ UART5_DE	-	-	-	SDMMC1_D0	DCMI_D2	-	EVENTOUT
	PC9	UART5_CTS	QUADSPI_BK1 _IO0	-	-	SDMMC1_D1	DCMI_D3	LCD_B2	EVENTOUT

Table 9. Alternate function AF8 to AF15 (1) (continued)

Electrical Characteristics

Unless otherwise specified, the parameters given in Table 76 are derived from tests performed under the ambient temperature, f pclk2 frequency and V DDA supply voltage conditions summarized in Table 13: General operating conditions .

Table 76. ADC characteristics (1)(2)

Symbol	Parameter	Conditions	Conditions	Min	Typ	Max	Unit
V DDA	Analog power supply	-	-	1.62	-	3.6	V
V REF+	Positive reference voltage	V DDA ≥ 2 V	V DDA ≥ 2 V	2	-	V DDA	V
V REF+	Positive reference voltage	V DDA < 2 V	V DDA < 2 V	V DDA	V DDA	V DDA	V
V REF-	Negative reference voltage	-	-	V SSA	V SSA	V SSA	V
f ADC	ADC clock frequency	2 V ≤ V DDA ≤3.3 V	BOOST=1	0.12	-	36	MHz
f ADC	ADC clock frequency	2 V ≤ V DDA ≤3.3 V	BOOST = 0	0.12	-	20	MHz

Table 76. ADC characteristics (1)(2)

Table 76. ADC characteristics (1)(2) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
f		16-bit resolution	-	-	3.60
f	Sampling rate for Fast	14-bit resolution	-	-	4.00
f	channels, BOOST = 1, f ADC = 36 MHz,	12-bit resolution	-	-	4.50
f	sampling time = 1.5 cycles	10-bit resolution	-	-	5.00
f		8-bit resolution	-	-	6.00
f	Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz, sampling time = 1.5 cycles	16-bit resolution	-	-	2.00
f	Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz, sampling time = 1.5 cycles	14-bit resolution	-	-	2.20
f	Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz, sampling time = 1.5 cycles	12-bit resolution	-	-	2.50
f	Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz, sampling time = 1.5 cycles	10-bit resolution	-	-	2.80
f	Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz, sampling time = 1.5 cycles	8-bit resolution	-	-	3.30
S	Sampling rate for Slow channels, BOOST = 1, f ADC = 28 MHz, sampling time = 2.5 cycles	16-bit resolution	-	-	2.55	MSPS
f	Sampling rate for Slow channels, BOOST = 1, f ADC = 28 MHz, sampling time = 2.5 cycles	14-bit resolution	-	-	2.80	MSPS
f	Sampling rate for Slow channels, BOOST = 1, f ADC = 28 MHz, sampling time = 2.5 cycles	12-bit resolution	-	-	3.11	MSPS
f	Sampling rate for Slow channels, BOOST = 1, f ADC = 28 MHz, sampling time = 2.5 cycles	10-bit resolution	-	-	3.50	MSPS
f	Sampling rate for Slow channels, BOOST = 1, f ADC = 28 MHz, sampling time = 2.5 cycles	8-bit resolution	-	-	4.00	MSPS
f		16-bit resolution	-	-	1.82
f	Sampling rate for Slow	14-bit resolution	-	-	2.00
f	channels, BOOST = 0, f ADC = 20 MHz,	12-bit resolution	-	-	2.22
f	sampling time = 2.5 cycles	10-bit resolution	-	-	2.50
f		8-bit resolution	-	-	2.86
f TRIG	External trigger frequency	f ADC = 36 MHz	-	-	3.6	MHz
f TRIG	External trigger frequency	16-bit resolution	-	-	10	1/f ADC
V AIN (3)	Conversion voltage range	-	0	-	V REF+
V CMIV	Common mode input voltage	-	V REF /2- 10%	V REF /2	V REF /2+ 10%	V
C ADC	Internal sample and hold capacitor	-	-	4	-	pF
t ADCREG_ STUP	ADC LDO startup time	-	-	5	10	μs
t STAB	ADC power-up time	LDO already started		1		1/f ADC

Table 76. ADC characteristics (1)(2) (continued)

237

Table 76. ADC characteristics (1)(2) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t CAL	Offset and linearity calibration time	-	16384	16384	16384	1/f ADC
t OFF_CAL	Offset calibration time	-	1280	1280	1280	1/f ADC
t LATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 00	1.5	2	2.5	1/f ADC
t LATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 01	-	-	2.5	1/f ADC
t LATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 10	-	-	2.5	1/f ADC
t LATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 11	-	-	2.25	1/f ADC
t LATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 00	2.5	3	3.5	1/f ADC
t LATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 01	-	-	3.5	1/f ADC
t LATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 10	-	-	3.5	1/f ADC
t LATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 11	-	-	3.25	1/f ADC
t S	Sampling time	-	1.5	-	810.5	1/f ADC
t CONV	Total conversion time (including sampling time)	N-bit resolution	t s + N/2 (4)	t s + N/2 (4)	t s + N/2 (4)	1/f ADC
I DDA(ADC)	ADC consumption from V DDA supply (differential)	F S = 3.6 Msps, BOOST = 1	-	1900	-	μA
I DDA(ADC)	ADC consumption from V DDA supply (differential)	F S = 1 Msps, BOOST = 0	-	460	-	μA
I DDA(REF)	ADC consumption from V REF+ (differential)	F S = 3.6 Msps, BOOST = 1	-	260	-	μA
I DDA(REF)	ADC consumption from V REF+ (differential)	F S = 1 Msps, BOOST = 0	-	140	-	μA
I DDA(ADC)	ADC consumption from V DDA supply (single-ended)	F S = 3.6 Msps, BOOST = 1	-	1700	-	μA
I DDA(ADC)	ADC consumption from V DDA supply (single-ended)	F S = 1 Msps, BOOST = 0	-	445	-	μA
I DDA(REF)	ADC consumption from V REF+ supply (single- ended)	F S = 3.6 Msps, BOOST = 1	-	160	-	μA
I DDA(REF)	ADC consumption from V REF+ supply (single- ended)	F S = 1 Msps, BOOST = 0	-	75	-	μA

Voltage BOOSTER on ADC switches must be used for V DDA < 2.4 V (switches inside IO).
Depending on the package, V REF- can be internally connected to V SSA .
9 to 818 cycles @ 14-bit mode.

Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V DDA = 1.6 V (1)

Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V DDA = 1.6 V (1)

Resolution (2)	RAIN (Ω)	Fast channels (3) (ns)	Slow channels (4) (ns)
16 bits	47 (5)	107	166
14 bits	47	90.8	144
14 bits	68	967	151
14 bits	100	108	157
14 bits	150	128	171
14 bits	220 (5)	161	192
12 bits	47	76.7	125
12 bits	68	81.5	127
12 bits	100	89.8	134
12 bits	150	107	146
12 bits	220	132	169
12 bits	330	177	205
12 bits	470	2.36	264
12 bits	680	329	345
12 bits	1000 (5)	462	488
10 bits	47	62.5	103
10 bits	68	66.2	106
10 bits	100	72.7	112
10 bits	150	85.4	121
10 bits	220	106	137
10 bits	330	140	168
10 bits	470	187	209
10 bits	680	258	279
10 bits	1000	367	381
10 bits	1500	537	552
10 bits	2200	776	786
10 bits	3300	1130	1140
10 bits	4700 (5)	1600	1600

237

Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V DDA = 1.6 V (1) (continued)

Resolution (2)	RAIN (Ω)	Fast channels (3) (ns)	Slow channels (4) (ns)
8 bits	47	48.7	82.4
8 bits	68	51.4	84.6
8 bits	100	56.4	88.7
8 bits	150	65.8	95.7
8 bits	220	80.4	108
8 bits	330	106	130
8 bits	470	139	160
8 bits	680	189	208
8 bits	1000	269	284
8 bits	1500	390	405
8 bits	2200	562	572
8 bits	3300	827	840
8 bits	4700	1170	1170
8 bits	6800	1670	1670
8 bits	10000	2440	2430
8 bits	15000	3660	3630
8 bits	2200 (5)	5360	5310

Guaranteed by design.
The tolerance is 8 LSB for 16-bit, 4 LSB for 14-bit, 2 LSB for 12-bit, 10-bit and 8-bit conversions.
On ADC1, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF11, PF12. On ADC2, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF13, PF14.
Slow channels are all ADC inputs except the fast channels.
Maximum external input impedance value authorized for the given resolution.

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics , Table 11: Current characteristics , and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 10. Voltage characteristics (1)

Symbols	Ratings	Min	Max	Unit
V DDX - V SSX	External main supply voltage (including V DD , V DD_ANA , V DD_PLL , V DD_DSI , V DDA , V DD3V3_USB , V BAT , V REF+ )	-0.3	3.9	V
V DDCORE - V SS	External core supply voltage	-0.3	1.5	V
V DDA_DDR - V SS	DDR IO supply voltage	-0.3	1.98	V
V DDA1V8 - V SS	1.8 V supply (including V DDA1V8_REG , V DDA1V8_DSI )	-0.3	3.9	V

Table 10. Voltage characteristics (1)

Table 10. Voltage characteristics (continued) (1)

Symbols	Ratings	Min	Max	Unit
V DDA1V2 - V SS	1.2 V supply (including V DDA1V2_DSI_REG , V DDA1V2_DSI_PHY )	-0.3	1.98	V
V IN (2)	Input voltage on FT_xxx pins	V SS - 0.3	Min(V DD , V DDA , V DD3V3_USB , V BAT ) +3.9 (3)(4)	V
V IN (2)	Input voltage on TT_xx pins	V SS - 0.3	3.9	V
V IN (2)	Input voltage on OTG_VBUS pin	V SS - 0.3	6.0 (5)	V
V IN (2)	Input voltage on USB/OTG_HS_DP/DM pins	V SS - 0.3	5.25	V
V IN (2)	Input voltage on OTG_FS_DP/DM pins	V SS - 0.3	5.5 (5)	V
V IN (2)	Input voltage on any other pins	V SS - 0.3	3.9	V
\	∆V DDX \		Variations between differentV DDX power pins of the same domain	-
\	V SSx -V SS \		Variations between all the different ground pins	-
V REF+ - V DDA	Allowed voltage difference for V REF+ > V DDA	-	0.4	V

All power (V DD , V DDA , V DD3V3_USB , V DDCORE , V BAT ) and ground (V SS , V SSA , V SSX ) pins must always be connected to the external/internal power supply, in the permitted range.
VIN maximum must always be respected. Refer to Table 51 for the maximum allowed injected current values.
This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.
Voltage should be also below Min(V DD , V DD3V3_USBFS ) + 3.9 V
All power (V DD , V DDA , V DD3V3_USB , V DDCORE ) and ground (V SS , V SSA , V SSX ) pins must always be connected to the external/internal power supply, in the permitted range.

Table 11. Current characteristics

Symbols	Ratings	Max	Unit
ΣIV DD	Total current into sum of all V DD power lines (source) (1)	440	mA
ΣIV SS	Total current out of sum of all V SS ground lines (sink) (1)	440	mA
IV DD	Maximum current into each V DD power pin (source) (1)	100	mA
IV SS	Maximum current out of each V SS ground pin (sink) (1)	100	mA
I IO	Output current sunk by any I/O and control pin	20	mA
ΣI (PIN)	Total output current sunk by sum of all I/Os and control pins (2)	140	mA
ΣI (PIN)	Total output current sourced by sum of all I/Os and control pins (2)	140	mA
I INJ(PIN) (3)(4)	Injected current on FT_xxx, TT_xx, NRST pins except PA4, PA5	-5/+0	mA
I INJ(PIN) (3)(4)	Injected current on PA4, PA5	-0/0	mA
ΣI INJ(PIN)	Total injected current (sum of all I/Os and control pins) (5)	±25	mA

This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins.
Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

237

A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage values.
When several inputs are submitted to a current injection, the maximum ∑I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 12. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature (suffix 1)	105	°C
T J	Maximum junction temperature (suffix 3)	125	°C

Thermal Information

Package thermal characteristics in Table 125 are specified with conditions as per JEDEC JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function of board thermal characteristics and other components on the board.

ΘJA :

Thermal resistance junction-ambient.

ΘJB :

Thermal resistance junction-board.

ΘJC :

Thermal resistance junction-top-case.

Θjb:

Thermal parameter junction-board.

Ψjt:

Thermal parameter junction-top-case.

Motherboard type: four layers, JEDEC 2S2P

Table 125. Thermal characteristics

Symbol	Parameter	Value	Value
Symbol	Parameter	Natural convection	1m/s (200 ft/mn)
	TFBGA257 - 257-ball 10x10mm 0.50/0.65 mm pitch	36.079	31.79
	TFBGA361 - 361-ball 12x12 mm0.50/0.65 mm pitch	35.151	30.953
	LFBGA354 - 354-ball 16x16 mm0.80mm pitch	34.145	30.121
	LFBGA448 - 448-ball 18x18 mm0.80mm pitch	28.545	24.797
	TFBGA257 - 257-ball 10x10mm 0.50/0.65 mmpitch	19.487	19.487
	TFBGA361 - 361-ball 12x12mm 0.50/0.65 mmpitch	20.555	20.555
	LFBGA354 - 354-ball 16x16 mm 0.80mm pitch	22.038	22.038
	LFBGA448 - 448-ball 18x18 mm 0.80mm pitch	17.409	17.409
	TFBGA257 - 257-ball 10x10mm 0.50/0.65 mmpitch	10.768	10.768
	TFBGA361 - 361-ball 12x12mm 0.50/0.65 mmpitch	10.049	10.049
	LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch	9.675	9.675
	TLFBGA448 - 448-ball 18x18 mm 0.80 mm pitch	8.439	8.439
	TFBGA257 - 257-ball 10x10 mm0.50/0.65 mm pitch	18.949	18.332
	TFBGA361 - 361-ball 12x12 mm0.50/0.65 mm pitch	20.002	19.398
	LFBGA354 - 354-ball 16x16 mm0.80mm pitch	21.456	20.894
	LFBGA448 - 448-ball 18x18 mm0.80mm pitch	16.946	16.574
	TFBGA257 - 257-ball 10x10mm 0.50/0.65 mmpitch	0.383	0.812
	TFBGA361 - 361-ball 12x12mm 0.50/0.65 mmpitch	0.354	0.735
	LFBGA354 - 354-ball 16x16 mm0.80 mmpitch	0.339	0.658
	LFBGA448 - 448-ball 18x18 mm0.80 mmpitch	0.297	0.542

Per JEDEC JESD51-12.
Per JEDEC JESD51-12.

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
STM32MP157	STMicroelectronics	—
STM32MP157C	STMicroelectronics	—
STM32MP157C/F	STMicroelectronics	—
STM32MP157C/FAAXX	STMicroelectronics	—
STM32MP157C/FABXX	STMicroelectronics	—
STM32MP157C/FADXX	STMicroelectronics	—
STM32MP157CAAXX	STMicroelectronics	—
STM32MP157CABXX	STMicroelectronics	—
STM32MP157CACXX	STMicroelectronics	—
STM32MP157CADXX	STMicroelectronics	—
STM32MP157F	STMicroelectronics	—
STM32MP157FAAXX	STMicroelectronics	—
STM32MP157FABXX	STMicroelectronics	—
STM32MP157FACXX	STMicroelectronics	—
STM32MP157FAD1	STMicroelectronics	257-TFBGA
STM32MP157FADXX	STMicroelectronics	—
STM32MP157FXX1	STMicroelectronics	—

STM32MP157C/FACXX

Key Specifications

Overview

Features

Pin Configuration

Electrical Characteristics

Absolute Maximum Ratings

Thermal Information

Package Information

Related Variants