STM32MP157FAD1

Part: STM32MP157C/F (STM32MP157FAD1) — STMicroelectronics

Type: Arm dual Cortex-A7 + Cortex-M4 Microprocessor (MPU)

Description: Dual-core 32-bit Cortex-A7 (up to 800 MHz on STM32MP157F) plus Cortex-M4 (up to 209 MHz) MPU with 3D GPU, TFT/DSI display, 37 communication peripherals, 29 timers, advanced analog and crypto, with 1.71–3.6 V I/O supply.

Operating Conditions:

• I/O and embedded regulator supply (VDD): 1.71–3.6 V (1.71–2.7 V when SYSCFG_IOCTRLSETR ≠ 0)
• Junction temperature (Suffix 1 version): -20 to 105 °C
• Cortex-A7 clock: up to 800 MHz (STM32MP157F), up to 650 MHz (STM32MP157C)
• VDDCORE: 1.30–1.38 V (run above 650 MHz), 1.18–1.25 V (run up to 650 MHz)

Absolute Maximum Ratings:

• Max external main supply voltage (VDDX - VSS): 3.9 V
• Max core supply voltage (VDDCORE - VSS): 1.5 V
• Max DDR IO supply voltage (VDDA_DDR - VSS): 1.98 V
• Max total current into all VDD lines: 440 mA
• Max current per VDD pin: 100 mA
• Max current sunk by any I/O pin: 20 mA

Key Specs:

• Cortex-A7 subsystem frequency: up to 800 MHz (STM32MP157F), 650 MHz (STM32MP157C)
• Cortex-M4 clock (Fmcu_ck): up to 209 MHz
• AXI/AHB5/AHB6 clock: up to 266 MHz
• VDDA (ADC with VREF > 2 V): 2–3.6 V
• VBAT: 1.2–3.6 V (1.4 V min if 64 KB retention SRAM used)
• VDD3V3_USBHS (when used): 3.07–3.6 V
• VDDQ_DDR: 1.425–1.575 V (DDR3), 1.283–1.45 V (DDR3L), 1.14–1.3 V (LPDDR2/LPDDR3)
• Standby current: down to 2 μA (no RTC, no LSE, no BKPSRAM, no RETRAM)

Features:

• Dual Cortex-A7 with 32 KB L1 I/D per core, 256 KB L2 cache, NEON and TrustZone
• Cortex-M4 with FPU/MPU, up to 209 MHz
• External DDR up to 1 GB (LPDDR2/LPDDR3-1066, DDR3/DDR3L-1066, 16/32-bit)
• 708 KB internal SRAM
• Vivante 3D GPU (OpenGL ES 2.0), LCD-TFT controller, MIPI DSI 2 lanes
• Up to 37 communication peripherals: 6 × I2C, 4 × UART + 4 × USART, 6 × SPI, 4 × SAI, 3 × SDMMC, 2 × CAN FD, USB 2.0 HS host/OTG, Gigabit Ethernet
• 2 × 16-bit ADCs, 2 × 12-bit DACs, DFSDM
• Up to 29 timers and 3 watchdogs
• Secure boot, TrustZone peripherals, active tamper, AES/TDES/HASH/RNG hardware crypto
• Up to 176 I/Os with interrupt capability
• Low-power modes: Sleep, Stop, Standby, with DDR retention in Standby
• 3072-bit fuses including 96-bit unique ID
• ECOPACK2 compliant

Applications:

Package:

• TFBGA257
• LFBGA354
• TFBGA361
• LFBGA448

• ARMv7-A architecture
• 32-Kbyte L1 instruction cache for each CPU
• 32-Kbyte L1 data cache for each CPU
• 256-Kbyte level2 cache
• Arm ® + Thumb ® -2 instruction set
• Arm ® TrustZone ® security technology
• Arm ® NEON™ Advanced SIMD
• DSP and SIMD extensions
• VFPv4 floating-point
• Hardware virtualization support
• Embedded trace module (ETM)
• Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts
• Integrated generic timer (CNT)

Unless otherwise specified, the parameters given in Table 76 are derived from tests performed under the ambient temperature, f pclk2 frequency and V DDA supply voltage conditions summarized in Table 13: General operating conditions .

Table 76. ADC characteristics (1)(2)

Table 76. ADC characteristics (1)(2)

Table 76. ADC characteristics (1)(2) (continued)

Table 76. ADC characteristics (1)(2) (continued)

237

Table 76. ADC characteristics (1)(2) (continued)

1. Voltage BOOSTER on ADC switches must be used for V DDA < 2.4 V (switches inside IO).
2. Depending on the package, V REF- can be internally connected to V SSA .
3. 9 to 818 cycles @ 14-bit mode.

Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V DDA = 1.6 V (1)

237

Table 77. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V DDA = 1.6 V (1) (continued)

1. The tolerance is 8 LSB for 16-bit, 4 LSB for 14-bit, 2 LSB for 12-bit, 10-bit and 8-bit conversions.
2. On ADC1, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF11, PF12. On ADC2, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF13, PF14.
3. Slow channels are all ADC inputs except the fast channels.
4. Maximum external input impedance value authorized for the given resolution.

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics , Table 11: Current characteristics , and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 10. Voltage characteristics (1)

Table 10. Voltage characteristics (1)

Table 10. Voltage characteristics (continued) (1)

1. All power (V DD , V DDA , V DD3V3_USB , V DDCORE , V BAT ) and ground (V SS , V SSA , V SSX ) pins must always be connected to the external/internal power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 51 for the maximum allowed injected current values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
4. To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.
5. Voltage should be also below Min(V DD , V DD3V3_USBFS ) + 3.9 V
6. All power (V DD , V DDA , V DD3V3_USB , V DDCORE ) and ground (V SS , V SSA , V SSX ) pins must always be connected to the external/internal power supply, in the permitted range.

Table 11. Current characteristics

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins.

2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

237

1. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage values.
2. When several inputs are submitted to a current injection, the maximum ∑I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 12. Thermal characteristics

Package thermal characteristics in Table 125 are specified with conditions as per JEDEC JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function of board thermal characteristics and other components on the board.

ΘJA :

Thermal resistance junction-ambient.

ΘJB :

Thermal resistance junction-board.

ΘJC :

Thermal resistance junction-top-case.

Θjb:

Thermal parameter junction-board.

Ψjt:

Thermal parameter junction-top-case.

Motherboard type: four layers, JEDEC 2S2P

Table 125. Thermal characteristics

1. Per JEDEC JESD51-12.
2. Per JEDEC JESD51-12.

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

Note: The datasheet section provided contains only the ordering scheme legend (Table 126 reference): "T = tape and reel" and "No character = tray or tube". The actual ordering code table listing STM32MP157FAD1 variants, package types, and temperature ranges is not included in the supplied text.