STM32L432KCU6

Part: STM32L432KB STM32L432KC

Type: Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU

Description: Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 256KB Flash, 64KB SRAM, USB FS, analog, audio.

Operating Conditions:

• Supply voltage: 1.71 V to 3.6 V
• Operating temperature: -40 °C to 125 °C
• Max CPU frequency: 80 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V (VDD, VDDIOx, VDDUSB, VDDA, VDDSDMMC, VDDQ)
• Max continuous current: 120 mA (Total current into VDD supply)
• Max storage temperature: -65 to +150 °C

Key Specs:

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, MPU, DSP instructions
• Performance: 100DMIPS, 1.25 DMIPS/MHz (Drystone 2.1), 273.55 CoreMark®
• Flash memory: Up to 256 KB single bank
• SRAM: 64 KB, including 16 KB with hardware parity check
• ADC: 1x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling
• DAC: 2x 12-bit output channels
• Run mode current: 84 μA/MHz
• Shutdown mode current: 8 nA

Features:

• FlexPowerControl with ultra-low-power modes
• Adaptive real-time accelerator (ART Accelerator™)
• Quad SPI memory interface
• USB 2.0 full-speed crystal less solution
• Rich analog peripherals: ADC, DAC, operational amplifier with PGA, comparators
• 14-channel DMA controller
• True random number generator

Package:

• UFQFPN32

• Ultra-low-power with FlexPowerControl

• -1.71 V to 3.6 V power supply

• --40 °C to 85/105/125 °C temperature range

• -8 nA Shutdown mode (2 wakeup pins)

• -28 nA Standby mode (2 wakeup pins)

• -280 nA Standby mode with RTC

• -1.0 μA Stop 2 mode, 1.28 μA with RTC

• -84 μA/MHz run mode

• -Batch acquisition mode (BAM)

• -4 μs wakeup from Stop mode

• -Brown out reset (BOR)

• -Interconnect matrix

• Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions

• Performance benchmark

• -1.25 DMIPS/MHz (Drystone 2.1)

• -273.55 CoreMark ® (3.42 CoreMark/MHz @ 80 MHz)

• Energy benchmark

• -176.7 ULPBench ® score

• Clock Sources

• -32 kHz crystal oscillator for RTC (LSE)

• -Internal 16 MHz factory-trimmed RC (±1%)

• -Internal low-power 32 kHz RC (±5%)

• -Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)

• -Internal 48 MHz with clock recovery

• -2 PLLs for system clock, USB, audio, ADC

• CRC calculation unit, 96-bit unique ID

• Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™

• All packages are ECOPACK2 ® compliant

Figure 5. STM32L432Kx UFQFPN32 pinout (1)

1. The above figure shows the package top view.
2. The related I/O structures in Table 14 are: FT_f, FT_fa.
3. The related I/O structures in Table 14 is: FT_u.
4. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a.

Table 13. Legend/abbreviations used in the pinout table

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Table 14. STM32L432xx pin definitions

Table 14. STM32L432xx pin definitions

Table 14. STM32L432xx pin definitions (continued)

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Table 14. STM32L432xx pin definitions (continued)

1. PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC14 to PC15 in output mode is limited:

• These GPIOs must not be used as current sources (e.g. to drive an LED).

• The speed should not exceed 2 MHz with a maximum load of 30 pF

1. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0394 reference manual.
2. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

Table 15. Alternate function AF0 to AF7 (1)

Table 15. Alternate function AF0 to AF7 (1)

Table 15. Alternate function AF0 to AF7 (1)

Table 15. Alternate function AF0 to AF7 (1) (continued)

Table 16. Alternate function AF8 to AF15 (1)

Table 16. Alternate function AF8 to AF15 (1)

Table 16. Alternate function AF8 to AF15 (1)

Table 16. Alternate function AF8 to AF15 (1) (continued)

The definition and values of input/output AC characteristics are given in Figure 19 and Table 59 , respectively.

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Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions .

Table 59. I/O AC characteristics (1)(2)

Table 59. I/O AC characteristics (1)(2)

Table 59. I/O AC characteristics (1)(2) (continued)

1. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
2. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

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Figure 19. I/O AC characteristics definition (1)

1. Refer to Table 59: I/O AC characteristics .

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics , Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 18. Voltage characteristics (1)

Table 18. Voltage characteristics (1)

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1. All main power (V DD , V DDA , V DDUSB ,) and ground (V SS , V SSA ) pins must always be connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
6. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
7. A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
8. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 19. Current characteristics

Table 20. Thermal characteristics

Table 20. Thermal characteristics

The maximum chip junction temperature (T J max) must never exceed the values given in Table 21: General operating conditions .

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.