STM32L432KC

STM32L432KB STM32L432KC

Overview

Part: STM32L432KB/KC

Type: Ultra-low-power Arm® Cortex®-M4 32-bit MCU

Key Specs:

  • Power supply: 1.71 V to 3.6 V
  • Temperature range: -40 °C to 85/105/125 °C
  • Core frequency: up to 80 MHz
  • Flash memory: Up to 256 KB
  • SRAM: 64 KB
  • DMIPS: 100 DMIPS
  • ADC: 1x 12-bit 5 Msps
  • DAC: 2x 12-bit output channels

Features:

  • Ultra-low-power with FlexPowerControl
  • Arm® 32-bit Cortex®-M4 CPU with FPU
  • Adaptive real-time accelerator (ART Accelerator™)
  • Up to 26 fast I/Os, most 5 V-tolerant
  • RTC with HW calendar, alarms and calibration
  • Up to 3 capacitive sensing channels
  • 11x timers
  • Quad SPI memory interface
  • Rich analog peripherals (independent supply)
  • 14x communication interfaces (USB 2.0 full-speed, SAI, I2C, USARTs, LPUART, SPIs, CAN, SWPMI, IRTIM)
  • 14-channel DMA controller
  • True random number generator
  • CRC calculation unit, 96-bit unique ID
  • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™

Applications:

  • null

Package:

  • UFQFPN32: dimensions not specified

Features

  • Ultra-low-power with FlexPowerControl
    • 1.71 V to 3.6 V power supply
    • -40 °C to 85/105/125 °C temperature range
    • 8 nA Shutdown mode (2 wakeup pins)
    • 28 nA Standby mode (2 wakeup pins)
    • 280 nA Standby mode with RTC
    • 1.0 μA Stop 2 mode, 1.28 μA with RTC
    • 84 μA/MHz run mode
    • Batch acquisition mode (BAM)
    • 4 μs wakeup from Stop mode
    • Brown out reset (BOR)
    • Interconnect matrix
  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions
  • Performance benchmark
    • 1.25 DMIPS/MHz (Drystone 2.1)
    • 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz)
  • Energy benchmark
    • 176.7 ULPBench® score
  • Clock Sources
    • 32 kHz crystal oscillator for RTC (LSE)
    • Internal 16 MHz factory-trimmed RC (±1%)
    • Internal low-power 32 kHz RC (±5%)
    • Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
    • Internal 48 MHz with clock recovery
    • 2 PLLs for system clock, USB, audio, ADC

Datasheet - production data

  • Up to 26 fast I/Os, most 5 V-tolerant
  • RTC with HW calendar, alarms and calibration
  • Up to 3 capacitive sensing channels
  • 11x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 2x 16 bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer
  • Memories
    • Up to 256 KB single bank Flash, proprietary code readout protection
    • 64 KB of SRAM including 16 KB with hardware parity check
    • Quad SPI memory interface
  • Rich analog peripherals (independent supply)
    • 1x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps
    • 2x 12-bit DAC output channels, low-power sample and hold
    • 1x operational amplifier with built-in PGA
    • 2x ultra-low-power comparators
  • 14x communication interfaces
    • USB 2.0 full-speed crystal less solution with LPM and BCD
    • 1x SAI (serial audio interface)
    • 2x I2C FM+(1 Mbit/s), SMBus/PMBus
    • 3x USARTs (ISO 7816, LIN, IrDA, modem)
    • 1x LPUART (Stop 2 wake-up)
    • 2x SPIs (and 1x Quad SPI)
    • CAN (2.0B Active)
    • SWPMI single wire protocol master I/F
    • IRTIM (Infrared interface)
  • 14-channel DMA controller
  • True random number generator

This is information on a product in full production.

• CRC calculation unit, 96-bit unique ID

  • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
  • All packages are ECOPACK2® compliant

Pin Configuration

Figure 5. STM32L432Kx UFQFPN32 pinout(1)

  1. The above figure shows the package top view.

NameAbbreviationDefinition
Pin nameUnless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin typeSSupply pin
IInput only pin
I/OInput / output pin
I/O structureFT5 V tolerant I/O
TT3.6 V tolerant I/O
RSTBidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
_

Table 13. Legend/abbreviations used in the pinout table

  1. The related I/O structures in Table 14 are: FT_f, FT_fa.

  2. The related I/O structures in Table 14 is: FT_u.

  3. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a.

Table 14. STM32L432xx pin definitions
-------------------------------------------

Pin NumberPin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
UFQFPN32
2PC14-OSC32_IN (PC14)I/OFT(1)
(2)		EVENTOUTOSC32_IN
3PC15-OSC32_OUT (PC15)I/OFT(1)
(2)		EVENTOUTOSC32_OUT
4NRSTI/ORST--
Pin
Number		Pin name
(function after
reset)		Pin typeI/O structureNotesPin functions
UFQFPN32Alternate functions
13PA7I/OFT_fa-TIM1_CH1N, I2C3_SCL,
SPI1_MOSI,
QUADSPI_BK1_IO2,
COMP2_OUT, EVENTOUT
14PB0I/OFT_a-TIM1_CH2N, SPI1_NSS,
USART3_CK,
QUADSPI_BK1_IO1,
COMP1_OUT, SAI1_EXTCLK,
EVENTOUT
15PB1I/OFT_a-TIM1_CH3N,
USART3_RTS_DE,
LPUART1_RTS_DE,
QUADSPI_BK1_IO0,
LPTIM2_IN1, EVENTOUT
16VSSS---
17VDDS---
18PA8I/OFT-MCO, TIM1_CH1,
USART1_CK, SWPMI1_IO,
SAI1_SCK_A, LPTIM2_OUT,
EVENTOUT
19PA9I/OFT_f-TIM1_CH2, I2C1_SCL,
USART1_TX, SAI1_FS_A,
TIM15_BKIN, EVENTOUT
20PA10I/OFT_f-TIM1_CH3, I2C1_SDA,
USART1_RX,
USB_CRS_SYNC,
SAI1_SD_A, EVENTOUT
21PA11I/OFT_u-TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, COMP1_OUT,
USART1_CTS, CAN1_RX,
USB_DM,
TIM1_BKIN2_COMP1,
EVENTOUT
22PA12I/OFT_u-TIM1_ETR, SPI1_MOSI,
USART1_RTS_DE,
CAN1_TX, USB_DP,
EVENTOUT
23PA13
(JTMS
SWDIO)		I/OFT(3)JTMS-SWDIO, IR_OUT,
USB_NOE, SWPMI1_TX,
SAI1_SD_B, EVENTOUT
Pin NumberPin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
UFQFPN32
2PC14-OSC32_IN (PC14)I/OFT(1)
(2)		EVENTOUTOSC32_IN
3PC15-OSC32_OUT (PC15)I/OFT(1)
(2)		EVENTOUTOSC32_OUT
4NRSTI/ORST--

  • The speed should not exceed 2 MHz with a maximum load of 30 pF

  • These GPIOs must not be used as current sources (e.g. to drive an LED).

  1. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0394 reference manual.

  2. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

STM32L432KB STM32L432KC Pinouts and pin description

(
1)
Ta
b
le
1
5.
A
l
te
te
fu
t
io
A
F
0
to
A
F
7
rn
a
nc
n
Pot
r
P
A
0
Po
t
A
r		P
A
1
P
A
2
P
A
3
P
A
4
P
A
5
P
A
6
P
A
7
P
A
8
9
P
A
P
A
1
0
P
A
1
1
P
A
1
2
P
A
1
3
P
A
1
4
P
A
1
5

DS11451 Rev 4 55/156

Pinouts and pin description
  • Po
  • P
    B
    7
    L
    P
    T
    I
    M
    1_
    I
    N
    2
    I
    2
    C
    1_
    S
    D
    A
    U
    S
    A
    R
    T
    -
    -
    -
    -
    -
  • P
    C
    1
    4
    -
    -
    -
    -
    -
    -
    -
    -
    Po
    C
    t
  • r
    C
    P
    1
    5
    -
    -
    -
    -
    -
    -
    -
    -
  • Po
    t
    H
    P
    H
    3
    r
    -
    -
    -
    -
    -
    -
    -
    -
STM32L432KB STM32L432KC
Pinouts and pin description
A
F
8
A
F
9
A
F
1
0
A
F
1
1
A
F
1
2
A
F
1
3
A
F
1
4
A
F
1
5
C
O
M
P
1
/
Po
t
r
2
/
1
/
T
I
M
T
I
M
5
L
P
U
A
R
T
1
C
A
N
1
/
T
S
C
U
S
B
/
Q
U
A
D
S
P
I
C
O
M
P
2
/
S
A
I
1
E
V
E
N
T
O
U
T
-
T
I
M
1
6
/
L
P
T
I
M
2
S
W
P
M
I
1
P
A
0
C
O
M
P
1_
O
U
T
S
A
I
1_
E
X
T
C
L
K
T
I
M
2_
E
T
R
E
V
E
N
T
O
U
T
-
-
-
-
C
O
P
A
1
T
I
M
1
5_
H
1
N
E
V
E
N
T
U
T
-
-
-
-
-
-
Q
I_ B
U
A
D
S
P
C
O
O
C
O
P
A
2
L
P
U
A
R
T
1_
T
X
M
P
2_
U
T
T
I
M
1
5_
H
1
E
V
E
N
T
U
T
-
-
-
K
1_
N
C
S
Q
S
C
S
C
C
O
P
A
3
L
P
U
A
R
T
1_
R
X
U
A
D
P
I_
L
K
A
I
1_
M
L
K_
A
T
I
M
1
5_
H
2
E
V
E
N
T
U
T
-
-
-
P
A
4
S
A
I
1_
F
S_
B
L
P
T
I
M
2_
O
U
T
E
V
E
N
T
O
U
T
-
-
-
-
-
P
A
5
L
P
T
I
M
2_
E
T
R
E
V
E
N
T
O
U
T
-
-
-
-
-
-
Q
I_ B
U
A
D
S
P
T
I
M
N_ C
1_
B
K
I
P
A
6
L
P
U
A
R
T
1_
C
T
S
T
I
M
1
6_
C
H
1
E
V
E
N
T
O
U
T
-
-
-
K
1_
I
O
3
O
M
P
2
Q
I_ B
U
A
D
S
P
P
A
7
C
O
M
P
2_
O
U
T
E
V
E
N
T
O
U
T
-
-
-
-
-
O
K
1_
I
2
Po
t
A
r
P
A
8
S
W
P
M
I
1_
I
O
S
A
I
1_
S
C
K_
A
L
P
T
I
M
2_
O
U
T
E
V
E
N
T
O
U
T
-
-
-
-
P
A
9
S
A
I
1_
F
S_
A
T
I
M
1
5_
B
K
I
N
E
V
E
N
T
O
U
T
-
-
-
-
-
U
S
S_ S
B_
C
R
P
A
1
0
S
A
I
1_
S
D_
A
E
V
E
N
T
O
U
T
-
-
-
-
-
Y
N
C
T
I
M
2_ C
1_
B
K
I
N
P
A
1
1
C
A
N
1_
R
X
U
S
B_
D
M
E
V
E
N
T
O
U
T
-
-
-
-
O
M
P
1
P
A
1
2
C
A
N
1_
T
X
U
S
B_
D
P
E
V
E
N
T
O
U
T
-
-
-
-
-
P
A
1
3
U
S
B_
N
O
E
S
W
P
M
I
1_
T
X
S
A
I
1_
S
D_
B
E
V
E
N
T
O
U
T
-
-
-
-
S
S
S_
O
P
A
1
4
W
P
M
I
1_
R
X
A
I
1_
F
B
E
V
E
N
T
U
T
-
-
-
-
-
S
W
P
M
I
S
C_
G
O
O
P
A
1
5
T
3_
I
1
E
V
E
N
T
U
T
-
-
-
-
-		(
1)
fu
Ta
b
le
1
6.
A
l
te
te
t
io
A
F
8
to
A
F
1
5
rn
a
nc
n

Po
t
r
P
U
A
L
P
B
0
-		R
T
1
C
A
N
1
/
T
S
C
-		U
S
B
/
Q
U
A
D
S
P
I		C
O
M
P
1
-/ C
/ S
O
M
P
2
W
P
M
I
1
Q
I_ B
U
A
D
S
P
K
1_
I
O
1		-C
O
M
P
1_
O
U
T
L
P
U
A
R
T
P
B
1
D
_		1_
R
T
S
-
E		Q
I_ B
U
A
D
S
P
O
K
1_
I
0		--
P
B
3
-
Po
t
B
r		----
P
B
4
-		T
S
C_
G
2_
I
O
1		---
P
B
5
-		S
C_
G
2_
O
2
T
I		--C
O
2_
O
M
P
U
T
P
B
6
-		T
S
C_
G
2_
I
O
3		---
P
B
7
-		T
S
C_
G
2_
I
O
4		---
P
C
1
4
-
Po
C
t		----
r
C
P
1
5
-		----
Po
t
H
P
H
3
r
-		----

58/156 DS11451 Rev 4

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 19 and Table 59, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

SpeedSymbolParameterConditionsMinMaxUnit
FmaxMaximum frequencyC=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V		-
-		5
1
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V		-
-
-		0.1
10
1.5		MHz
00C=10 pF, 1.08 V≤VDDIOx≤1.62 V-0.1
Output rise and fall timeC=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V		-
-		25
52		ns
Tr/TfC=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V		-
-
-
-		140
17
37
110
FmaxMaximum frequencyC=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V		-
-		25
10
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V		-
-
-		1
50
15		MHz
01C=10 pF, 1.08 V≤VDDIOx≤1.62 V-1
Tr/Tf
Output rise and fall time		C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V		-
-		9
16
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V		-
-
-
-
Table 59. I/O AC characteristics(1)(2)		40
4.5
9
21		ns
------------------------------------------------
------------------------------------------------

SpeedSymbolParameterConditionsMinMaxUnit
FmaxMaximum frequencyC=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V		-
-
-		50
25
5
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V		-
-
-		100(3)
37.5
5		MHz
10Output rise and fall timeC=50 pF, 2.7 V≤VDDIOx≤3.6 V-5.8
C=50 pF, 1.62 V≤VDDIOx≤2.7 V-11ns
Tr/TfC=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V		-
-
-
-
-
-		28
2.5
5
12
120(3)
50
C=30 pF, 1.08 V≤VDDIOx≤1.62 V-10MHz
FmaxMaximum frequencyC=10 pF, 2.7 V≤VDDIOx≤3.6 V-180(3)
11C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V		-
-		75
10
Tr/TfOutput rise and fall timeC=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V		-
-
-		3.3
6
16		ns
FmaxMaximum frequency-1MHz
Fm+TfOutput fall time(4)C=50 pF, 1.6 V≤VDDIOx≤3.6 V-5ns
Table 59. I/O AC characteristics(1)(2) (continued)
--------------------------------------------------------
--------------------------------------------------------

  1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFGCFGR1 register. Refer to the RM0394 reference manual for a description of GPIO Port configuration register.

  2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

  1. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

1. Refer to Table 59: I/O AC characteristics.

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

SymbolRatingsMinMaxUnit
VDDX - VSSExternal main supply voltage (including VDD, VDDA, VDDUSB)-0.34.0V
VIN(2)Input voltage on FT_xxx pinsVSS-0.3min (VDD, VDDA, VDDUSB) + 4.0(3)(4)V
Input voltage on TT_xx pinsVSS-0.34.0V
Input voltage on any other pinsVSS-0.34.0V
∆VDDxVariations between different VDDX power pins of the same domain-50mV
VSSx-VSSVariations between all the different ground pins(5)-50mV
SymbolRatingsMinMaxUnit
VDDX - VSSExternal main supply voltage (including VDD, VDDA, VDDUSB)-0.34.0V
VIN(2)Input voltage on FT_xxx pinsVSS-0.3min (VDD, VDDA, VDDUSB) + 4.0(3)(4)V
Input voltage on TT_xx pinsVSS-0.34.0V
Input voltage on any other pinsVSS-0.34.0V
Variations between different VDDX power pins of the same domain-50mV
Variations between all the different ground pins(5)-50mV

    1. All main power (VDD, VDDA, VDDUSB,) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
    1. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values.
    1. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
    1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
    1. Include VREF- pin.

SymbolRatingsMaxUnit
∑IVDDTotal current into sum of all VDD power lines (source)(1)140
∑IVSSTotal current out of sum of all VSS ground lines (sink)(1)140
IVDD(PIN)Maximum current into each VDD power pin (source)(1)100
IVSS(PIN)Maximum current out of each VSS ground pin (sink)(1)100
IIO(PIN)Output current sunk by any I/O and control pin except FT_f20
Output current sunk by any FT_f pin20
Output current sourced by any I/O and control pin20mA
∑IIO(PIN)Total output current sunk by sum of all I/Os and control pins(2)100
Total output current sourced by sum of all I/Os and control pins(2)100
IINJ(PIN)(3)Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5-5/+0(4)
Injected current on PA4, PA5-5/0
∑IINJ(PIN)Total injected current (sum of all I/Os and control pins)(5)
SymbolRatingsValueUnit
------------
TSTGStorage temperature range-65 to +150°C
TJMaximum junction temperature150°C

Table 19. Current characteristics

1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

  1. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
    1. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
    1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

SymbolRatingsValueUnit
TSTGStorage temperature range–65 to +150°C
TJMaximum junction temperature150°C

Thermal Information

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 21: General operating conditions.

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:mathsf{T}mathsf{J} mathsf{max} = mathsf{T}mathsf{A} mathsf{max} + (mathsf{P}mathsf{D} mathsf{max} × mathsf{G}mathsf{Jmathsf{A}})perp$

Where:

  • TA max is the maximum ambient temperature in °C,
  • ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
  • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
  • PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Table 85. Package thermal characteristics

SymbolParameterValueUnit
ΘJAThermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm / 0.5 mm pitch		39°C/W

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
STM32L432KB——
STM32L432KCU6——
STM32L432KX——
STM32L432XX——
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.

Get structured datasheet data via API

Get started free