STM32L152RC-A

STM32L15xQC STM32L15xRC-A STM32L15xVC-A STM32L15xZC

Overview

Part: STM32L15x family (Arm®-based Cortex®-M3 MCU)

Type: Ultra-low-power 32-bit MCU Arm®-based Cortex®-M3

Key Specs:

Power Supply: 1.65 V to 3.6 V
Temperature Range: -40°C to 105°C
Flash Memory: 256 Kbytes
SRAM: 32 Kbytes
EEPROM: 8 Kbytes
CPU Frequency: Up to 32 MHz
ADC Resolution: 12-bit, 1 Msps
DAC Channels: 2 channels, 12-bit
I/O Count: Up to 116 fast I/Os

Features:

Ultra-low-power platform
305 nA standby mode (3 wakeup pins)
0.475 μA stop mode (16 wakeup lines)
230 μA/MHz run mode
Arm® Cortex®-M3 32-bit CPU with Memory protection unit
Up to 23 capacitive sensing channels
CRC calculation unit, 96-bit unique ID
Low-power, ultrasafe BOR (brownout reset) with 5 selectable thresholds
Pre-programmed bootloader (USB and USART supported)
Serial wire debug, JTAG and trace
102 I/Os 5V tolerant
LCD driver (except STM32L151xC/C-A devices) up to 8x40 segments
2x operational amplifiers
2x ultra-low-power-comparators
DMA controller 12x channels
1x USB 2.0
3x USARTs
Up to 8x SPIs (2x I2S)
2x I2Cs (SMBus/PMBus)
11x timers (1x 32-bit, 6x 16-bit, 2x 16-bit basic, 2x watchdog)

Applications:

null

Package:

LQFP64
WLCSP64
LQFP100
UFBGA132
LQFP144

Features

Ultra-low-power platform
- 1.65 V to 3.6 V power supply
- -40°C to 105°C temperature range
- 305 nA standby mode (3 wakeup pins)
- 1.15 μA standby mode + RTC
- 0.475 μA stop mode (16 wakeup lines)
- 1.35 μA stop mode + RTC
- 11 μA Low-power run mode
- 230 μA/MHz run mode
- 10 nA ultra-low I/O leakage
- 8 μs wakeup time
Core: Arm® Cortex®-M3 32-bit CPU
- From 32 kHz up to 32 MHz max
- 1.25 DMIPS/MHz (Dhrystone 2.1)
- Memory protection unit
Up to 23 capacitive sensing channels
CRC calculation unit, 96-bit unique ID
Reset and supply management
- Low-power, ultrasafe BOR (brownout reset) with 5 selectable thresholds
- Ultra-low-power POR/PDR
- Programmable voltage detector (PVD)
Clock sources
- 1 to 24 MHz crystal oscillator
- 32 kHz oscillator for RTC with calibration
- High Speed Internal 16 MHz factorytrimmed RC (+/- 1%)
- Internal low-power 37 kHz RC
- Internal multispeed low-power 65 kHz to 4.2 MHz
- PLL for CPU clock and USB (48 MHz)
Pre-programmed bootloader
- USB and USART supported
Serial wire debug, JTAG and trace

Up to 116 fast I/Os (102 I/Os 5V tolerant), all mappable on 16 external interrupt vectors
Memories
- 256 Kbytes of Flash memory with ECC
- 32 Kbytes of RAM
- 8 Kbytes of true EEPROM with ECC
- 128-byte backup register
LCD driver (except STM32L151xC/C-A devices) up to 8x40 segments, contrast adjustment, blinking mode, step-up converter
Rich analog peripherals (down to 1.8V)
- 2x operational amplifiers
- 12-bit ADC 1 Msps up to 40 channels
- 12-bit DAC 2 ch with output buffers
- 2x ultra-low-power-comparators (window mode and wake up capability)
DMA controller 12x channels
9x peripheral communication interfaces
- 1x USB 2.0 (internal 48 MHz PLL)
- 3x USARTs
- Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
- 2x I2Cs (SMBus/PMBus)
11x timers: 1x 32-bit, 6x 16-bit with up to 4 IC/OC/PWM channels, 2x 16-bit basic timers, 2x watchdog timers (independent and window)

Table 1. Device summary

Reference	Part numbers
STM32L151QC	STM32L151QCH6
STM32L151RC-A	STM32L151RCT6A, STM32L151RCY6
STM32L151VC-A	STM32L151VCT6A
STM32L151ZC	STM32L151ZCT6
STM32L152QC	STM32L152QCH6
STM32L152RC-A	STM32L152RCT6A
STM32L152VC-A	STM32L152VCT6A
STM32L152ZC	STM32L152ZCT6

Pin Configuration

Figure 3. STM32L15xRC-A LQFP64 pinout

This figure shows the package top view.

Figure 4. STM32L15xRC WLCSP64 ballout

	1	2	3	4	5	6	7	8
A	VDD_2	PC10	PD2	PB3	PB5	BOOT0	VSS_3	VDD_3
B	VSS_2	PA14	PC11	PB4	PB6	PB9	PC15- OSC32_OUT	PC14- OSC32_IN
C	PA11	PA12	PA15	PC12	PB7	VLCD	NRST	PC13- WKUP2
D	PC9	PA9	PA10	PA13	PB8	PC2	PH1- OSC_OUT	PH0- OSC_IN
E	PC6	PC7	PC8	PA8	PA5	PA1	VSSA	PC0
F	PB15	PB14	PB11	PB1	VSS_4	PA0- WKUP1	PC3	PC1
G	PB13	PB12	PB10	PA7	PA6	VDD_4	PA3	VDDA
H	VDD_1	VSS_1	PB2	PB0	PC5	PC4	PA4	PA2
								MS31070V1

This figure shows the package top view.

Figure 5. STM32L15xVC-A LQFP100 pinout

This figure shows the package top view.

47/

Figure 6. STM32L15xQC UFBGA132 ballout

	1	2	3	4	5	6	7	8	9	10	11	12
Α	(PE3)	(PE1)	(PB8)	BOOTO	(PD7)	PD5	(PB4)	(PB3)	PA15	PA14	(PA13)	PA12
B	(PE4)	PE2	(PB9)	(PB7)	(PB6)	PD6	PD4	PD3	(PD1)	C12	PC10	PA11)
C	PC13 WKUP2	PE5	(PEO)	(VDD)3	(PB5)	G14	(G13)	PD2	PDO	PC11)	PH2	(PA10)
D	PC14- OSC32	VKUP3	(VSS)3	(PF2)	(PF1)	(PF0)	G12	(G10)	PG9	PA9	PA8	PC9
E	PC16- OSC32 OUT	(LCD	(VSS)6	(PF3)					PG5	PC8	PC7	PC6
F	PHO OSC IN	VSS)5	PF4	(PF5)		(SS)	VSS_0		PG3	PG4	(SS_)2	(SS)1
G	PH1 (OSC) OUT	VDD_5	PF6	(PF7)		VDD_9	VDD_10		(PG1)	PG2	(DD)2	(DD)1
H	(PC0)	(IRST)	(VDD)6	PF8					PG0	D15	PD14	PD13
J	(SSA)	PC1	PC2	PA4	(PA7)	PF9	PF12	(PF14)	(PF15)	PD12	PD11	PD10
K	OPAMP3 VINM	PC3	(PA2)	PA5	PC4	(PF11)	PF13	(PD9)	PD8	PB15	PB14	PB13
L	(REF)+	PAO- WKUP1	(PA3)	PA6	PC5	(PB2)	PE8	PE10	PE12	PB10	(PB11)	PB12
M	(DDA)	(PA1)	OPAMP1 VINM	OPAMP2 VINM	(PB0)	(PB1)	PE7	PE9	(PE11)	PE13	PE14	PE15

This figure shows the package top view.

V V V V V V V V V V V V V V V V V V V _____________________________________ {c} 44474747474747474747474747474747474747 108 V_{DD_2} 107 V_{SS_2} PE2 □ PE3 □ PE4 D 106 PH2 105 PA13 3 104 PA12 103 PA11 PE6-WKUP3 VLCD 🗖 PC13-WKUP2 DPC14-OSC32_IN D 102 PA10 101 PA9 100 PA8 99 PC9 PC15-OSC32_OUT PF0 10 PF1 | 11 PF2 | 12 98 E PC8 97 🗖 PC7 96 | PC6 95 | V_{DD_9} 94 | V_{SS_9} PF3 13 PF4 PF4 🗖 14 93 ( \begin{array}{c} \text{PG8} \ \text{PG8} \end{array} LQFP144 92 | PG7 91 | PG6 90 | PG5 89 F PG4 88 85 E PD14 84 | V_{DD_8} 84 D V_{DD_8} 83 D V_{SS_8} 82 D PD13 81 D PD12 80 D PD11 79 D PD10 78 D PD9 77 D PD8 PC3 🗖 29 V_SSA V_DDA D 76 PB15 75 PB14 33 34 PA1 D 74 PB13 73 PB12 35 36 {c} 33.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2 PA3 (SS.4 PA4 PA5 PA6 PA7 PA7 PA7 PA7 PB11 PF11 PF12 PE13 PE14 PE14 PE14 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 PE17 P MS18581V2

Figure 7. STM32L15xZC LQFP144 pinout

This figure shows the package top view.

47/

Table 7. Legend/abbreviations used in the pinout table

Na	me	Abbreviation	Definition
Pin r	name		e specified in brackets below the pin name, the pin function reset is the same as the actual pin name
		S	Supply pin
Pin	type	I	Input only pin
		I/O	Input / output pin
		FT	5 V tolerant I/O
I/O etr	ucture	TC	Standard 3.3 V I/O
1/0 511	ucture	B	Dedicated BOOT0 pin
		RST	Bidirectional reset pin with embedded weak pull-up resistor
No	tes	Unless otherwis and after reset	e specified by a note, all I/Os are set as floating inputs during
	Alternate functions	Functions select	ted through GPIOx_AFR registers
Pin functions	Additional functions	Functions directly selected/enabled through peripheral registers

	F	Pins							Pin function	ıs
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type ⁽¹⁾	I / O structure	Main function ⁽²⁾ (after reset)	Alternate functions	Additional functions
1	B2	1	-	-	PE2	I/O	FT	PE2	TIM3_ETR/LCD_SEG38/ TRACECLK	-
2	A1	2	-	-	PE3	I/O	FT	PE3	TIM3_CH1/LCD_SEG39/ TRACED0	-
3	B1	3	-	-	PE4	I/O	FT	PE4	TIM3_CH2/TRACED1	-
4	C2	4	-	-	PE5	I/O	FT	PE5	TIM9_CH1/TRACED2	-
5	D2	5	ı	ı	PE6- WKUP3	I/O	FT	PE6	TIM9_CH2/TRACED3	WKUP3/ RTC_TAMP3
6	E2	6	1	C6	V _LCD ⁽³⁾	S	-	V_LCD	-	-

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

		Pins							Pin functions
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type(1)	I / O structure	Main function(2) (after reset)	Alternate functions
7	C1	7	2	C8	PC13- WKUP2	I/O	FT	PC13	-
8	D1	8	3	B8	PC14- OSC32_IN(4)	I/O	TC	PC14	-
9	E1	9	4	B7	PC15- OSC32_OUT	I/O	TC	PC15	-
10	D6	-	-	-	PF0	I/O	FT	PF0	-
11	D5	-	-	-	PF1	I/O	FT	PF1	-
12	D4	-	-	-	PF2	I/O	FT	PF2	-
13	E4	-	-	-	PF3	I/O	FT	PF3	-
14	F3	-	-	-	PF4	I/O	FT	PF4	-
15	F4	-	-	-	PF5	I/O	FT	PF5	-
16	F2	10	-	-	VSS_5	S	-	VSS_5	-
17	G2	11	-	-	VDD_5	S	-	VDD_5	-
18	G3	-	-	-	PF6	I/O	FT	PF6	TIM5_CH1/TIM5_ETR
19	G4	-	-	-	PF7	I/O	FT	PF7	TIM5_CH2
20	H4	-	-	-	PF8	I/O	FT	PF8	TIM5_CH3
21	J6	-	-	-	PF9	I/O	FT	PF9	TIM5_CH4
22	-	-	-	-	PF10	I/O	FT	PF10	-
23	F1	12	5	D8	PH0- OSC_IN(5)	I/O	TC	PH0	-
24	G1	13	6	D7	PH1- OSC_OUT(5)	I/O	TC	PH1	-
25	H2	14	7	C7	NRST	I/O	RST	NRST	-
26	H1	15	8	E8	PC0	I/O	FT	PC0	LCD_SEG18

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

	F	Pins							Pin function	ns
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type ⁽¹⁾	I / O structure	Main function ⁽²⁾ (after reset)	Alternate functions	Additional functions
27	J2	16	9	F8	PC1	I/O	FT	PC1	LCD_SEG19	ADC_IN11/ COMP1_INP
28	-	17	10	D6	PC2	I/O	FT	PC2	LCD_SEG20	ADC_IN12/ COMP1_INP
-	J3	1	-	-	PC2	I/O	FT	PC2	LCD_SEG20	ADC_IN12/ COMP1_INP
-	K1	1	-	-		Ι	1		-	-
29	K2	18	11	F7	PC3	I/O	TC	PC3	LCD_SEG21	ADC_IN13/ COMP1_INP/
30	J1	19	12	E7	V_SSA	S	-	V_SSA	-	-
31	-	20	-	-	V _REF-	S	-	V _REF-	-	-
32	L1	21	-	-	V _REF+	S	-	V _REF+	-	-
33	M1	22	13	G8	V_DDA	S	-	V_DDA	-	-
34	L2	23	14	F6	PA0-WKUP1	I/O	FT	PA0	TIM2_CH1_ETR/ TIM5_CH1/ USART2_CTS	WKUP1/ RTC_TAMP2/ ADC_IN0/ COMP1_INP
35	M2	24	15	E6	PA1	I/O	FT	PA1	TIM2_CH2/TIM5_CH2/ USART2_RTS/ LCD_SEG0	ADC_IN1/ COMP1_INP/ OPAMP1_VINP
36	1	25	16	H8	PA2	I/O	FT	PA2	TIM2_CH3/TIM5_CH3/ TIM9_CH1/ USART2_TX/LCD_SEG1	ADC_IN2/ COMP1_INP/ OPAMP1_VINM
-	KЗ	1	ı	-	PA2	I/O	FT	PA2	TIM2_CH3/TIM5_CH3/ TIM9_CH1/ USART2_TX/LCD_SEG1	ADC_IN2/ COMP1_INP
-	M3	-	-	-	OPAMP1_VI NM	I	TC	OPAMP1_ VINM	-	-
37	L3	26	17	G7	PA3	I/O	TC	PA3	TIM2_CH4/TIM5_CH4/ TIM9_CH2/ USART2_RX/LCD_SEG2	ADC_IN3/ COMP1_INP/ OPAMP1_VOUT
38	-	27	18	F5	V _{SS_4}	S	-	V _{SS_4}	-	-

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

	F	Pins							Pin function	,
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type ⁽¹⁾	I / O structure	Main function ⁽²⁾ (after reset)	Alternate functions	Additional functions
39	-	28	19	G6	V _{DD_4}	S	-	V _{DD_4}	-	-
40	J4	29	20	H7	PA4	I/O	TC	PA4	SPI1_NSS/SPI3_NSS/ I2S3_WS/USART2_CK	ADC_IN4/ DAC_OUT1/ COMP1_INP
41	K4	30	21	E5	PA5	I/O	TC	PA5	TIM2_CH1_ETR/ SPI1_SCK	ADC_IN5/ DAC_OUT2/ COMP1_INP
42	L4	31	22	G5	PA6	I/O	FT	PA6	TIM3_CH1/TIM10_CH1/ SPI1_MISO/ LCD_SEG3	ADC_IN6/ COMP1_INP/ OPAMP2_VINP
43	1	32	23	G4	PA7	I/O	FT	PA7	TIM3_CH2/TIM11_CH1/ SPI1_MOSI/ LCD_SEG4	ADC_IN7/ COMP1_INP/ OPAMP2_VINM
-	J5	1	1	1	PA7	I/O	FT	PA7	TIM3_CH2/TIM11_CH1/ SPI1_MOSI/ LCD_SEG4	ADC_IN7/ COMP1_INP
-	M4	1	1	1	OPAMP2_VI NM	I	тc	OPAMP2_V INM	-	-
44	K5	33	24	H6	PC4	I/O	FT	PC4	LCD_SEG22	ADC_IN14/ COMP1_INP
45	L5	34	25	H5	PC5	I/O	FT	PC5	LCD_SEG23	ADC_IN15/ COMP1_INP
46	M5	35	26	H4	PB0	I/O	TC	PB0	TIM3_CH3/LCD_SEG5	ADC_IN8/ COMP1_INP/ OPAMP2_VOUT/ VREF_OUT
47	M6	36	27	F4	PB1	I/O	FT	PB1	TIM3_CH4/LCD_SEG6	ADC_IN9/ COMP1_INP/ VREF_OUT
48	L6	37	28	HЗ	PB2	I/O	FT	PB2/ BOOT1	BOOT1	ADC_IN0b
49	K6	-	ı	-	PF11	I/O	FT	PF11	-	ADC_IN1b
50	J7	-	-	_	PF12	I/O	FT	PF12	-	ADC_IN2b
51	E3	-	-	-	V _{SS_6}	S	-	V _{SS_6}	-	-
52	H3	-	-	-	V_DD₆	S	-	V_DD₆	-	-

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

		Pins							Pin functions
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type(1)	I / O structure	Main function(2) (after reset)	Alternate functions
53	K7	-	-	-	PF13	I/O	FT	PF13	-
54	J8	-	-	-	PF14	I/O	FT	PF14	-
55	J9	-	-	-	PF15	I/O	FT	PF15	-
56	H9	-	-	-	PG0	I/O	FT	PG0	-
57	G9	-	-	-	PG1	I/O	FT	PG1	-
58	M7	38	-	-	PE7	I/O	TC	PE7	-
59	L7	39	-	-	PE8	I/O	TC	PE8	-
60	M8	40	-	-	PE9	I/O	TC	PE9	TIM2_CH1_ETR
61	-	-	-	-	VSS_7	S	-	VSS_7	-
62	-	-	-	-	VDD_7	S	-	VDD_7	-
63	L8	41	-	-	PE10	I/O	TC	PE10	TIM2_CH2
64	M9	42	-	-	PE11	I/O	FT	PE11	TIM2_CH3
65	L9	43	-	-	PE12	I/O	FT	PE12	TIM2_CH4/SPI1_NSS
66	M10	44	-	-	PE13	I/O	FT	PE13	SPI1_SCK
67	M11	45	-	-	PE14	I/O	FT	PE14	SPI1_MISO
68	M12	46	-	-	PE15	I/O	FT	PE15	SPI1_MOSI
69	L10	47	29	G3	PB10	I/O	FT	PB10	TIM2_CH3/I2C2_SCL/ USART3_TX/ LCD_SEG10
70	L11	48	30	F3	PB11	I/O	FT	PB11	TIM2_CH4/ I2C2_SDA/ USART3_RX/ LCD_SEG11
71	F12	49	31	H2	VSS_1	S	-	VSS_1	-
72	G12	50	32	H1	VDD_1	S	-	VDD_1	-
73	L12	51	33	G2	PB12	I/O	FT	PB12	TIM10_CH1/I2C2_SMBA/ SPI2_NSS/ I2S2_WS/ USART3_CK/ LCD_SEG12

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

		Pins							Pin functions
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type(1)	I / O structure	Main function(2) (after reset)	Alternate functions
74	K12	52	34	G1	PB13	I/O	FT	PB13	TIM9_CH1/SPI2_SCK/ I2S2_CK/ USART3_CTS/ LCD_SEG13
75	K11	53	35	F2	PB14	I/O	FT	PB14	TIM9_CH2/SPI2_MISO/ USART3_RTS/ LCD_SEG14
76	K10	54	36	F1	PB15	I/O	FT	PB15	TIM11_CH1/SPI2_MOSI/ I2S2_SD/ LCD_SEG15
77	K9	55	-	-	PD8	I/O	FT	PD8	USART3_TX/LCD_SEG28
78	K8	56	-	-	PD9	I/O	FT	PD9	USART3_RX/LCD_SEG29
79	J12	57	-	-	PD10	I/O	FT	PD10	USART3_CK/LCD_SEG30
80	J11	58	-	-	PD11	I/O	FT	PD11	USART3_CTS/LCD_SEG31
81	J10	59	-	-	PD12	I/O	FT	PD12	TIM4_CH1/USART3_RTS/ LCD_SEG32
82	H12	60	-	-	PD13	I/O	FT	PD13	TIM4_CH2/LCD_SEG33
83	-	-	-	-	VSS_8	S	-	VSS_8	-
84	-	-	-	-	VDD_8	S	-	VDD_8	-
85	H11	61	-	-	PD14	I/O	FT	PD14	TIM4_CH3/LCD_SEG34
86	H10	62	-	-	PD15	I/O	FT	PD15	TIM4_CH4/LCD_SEG35
87	G10	-	-	-	PG2	I/O	FT	PG2	-
88	F9	-	-	-	PG3	I/O	FT	PG3	-
89	F10	-	-	-	PG4	I/O	FT	PG4	-
90	E9	-	-	-	PG5	I/O	FT	PG5	-
91	-	-	-	-	PG6	I/O	FT	PG6	-
92	-	-	-	-	PG7	I/O	FT	PG7	-
93	-	-	-	-	PG8	I/O	FT	PG8	-
94	F6	-	-	-	VSS_9	S	-	VSS_9	-
95	G6	-	-	-	VDD_9	S	-	VDD_9	-

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

		Pins							Pin functions
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type(1)	I / O structure	Main function(2) (after reset)	Alternate functions
96	E12	63	37	E1	PC6	I/O	FT	PC6	TIM3_CH1/I2S2_MCK/ LCD_SEG24
97	E11	64	38	E2	PC7	I/O	FT	PC7	TIM3_CH2/I2S3_MCK/ LCD_SEG25
98	E10	65	39	E3	PC8	I/O	FT	PC8	TIM3_CH3/LCD_SEG26
99	D12	66	40	D1	PC9	I/O	FT	PC9	TIM3_CH4/LCD_SEG27
100	D11	67	41	E4	PA8	I/O	FT	PA8	USART1_CK/MCO/ LCD_COM0
101	D10	68	42	D2	PA9	I/O	FT	PA9	USART1_TX / LCD_COM1
102	C12	69	43	D3	PA10	I/O	FT	PA10	USART1_RX / LCD_COM2
103	B12	70	44	C1	PA11	I/O	FT	PA11	USART1_CTS/ SPI1_MISO
104	A12	71	45	C2	PA12	I/O	FT	PA12	USART1_RTS/ SPI1_MOSI
105	A11	72	46	D4	PA13	I/O	FT	JTMS SWDIO	JTMS-SWDIO
106	C11	73	-	-	PH2	I/O	FT	PH2	-
107	F11	74	47	B1	VSS_2	S	-	VSS_2	-
108	G11	75	48	A1	VDD_2	S	-	VDD_2	-
109	A10	76	49	B2	PA14	I/O	FT	JTCK SWCLK	JTCK-SWCLK
110	A9	77	50	C3	PA15	I/O	FT	JTDI	TIM2_CH1_ETR/ SPI1_NSS/SPI3_NSS/ I2S3_WS/LCD_SEG17/ JTDI
111	B11	78	51	A2	PC10	I/O	FT	PC10	SPI3_SCK/I2S3_CK/ USART3_TX/ LCD_SEG28/LCD_SEG40/ LCD_COM4
112	C10	79	52	B3	PC11	I/O	FT	PC11	SPI3_MISO/USART3_RX/ LCD_SEG29/LCD_SEG41/ LCD_COM5

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

		Pins							Pin functions
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type(1)	I / O structure	Main function(2) (after reset)	Alternate functions
113	B10	80	53	C4	PC12	I/O	FT	PC12	SPI3_MOSI/I2S3_SD/ USART3_CK/LCD_SEG30/ LCD_SEG42/ LCD_COM6
114	C9	81	-	-	PD0	I/O	FT	PD0	TIM9_CH1/SPI2_NSS/ I2S2_WS
115	B9	82	-	-	PD1	I/O	FT	PD1	SPI2_SCK/I2S2_CK
116	C8	83	54	A3	PD2	I/O	FT	PD2	TIM3_ETR/LCD_SEG31/ LCD_SEG43/LCD_COM7
117	B8	84	-	-	PD3	I/O	FT	PD3	SPI2_MISO/USART2_CTS
118	B7	85	-	-	PD4	I/O	FT	PD4	SPI2_MOSI/I2S2_SD/ USART2_RTS/
119	A6	86	-	-	PD5	I/O	FT	PD5	USART2_TX
120	F7	-	-	-	VSS_10	S	-	VSS_10	-
121	G7	-	-	-	VDD_10	S	-	VDD_10	-
122	B6	87	-	-	PD6	I/O	FT	PD6	USART2_RX
123	A5	88	-	-	PD7	I/O	FT	PD7	TIM9_CH2/USART2_CK
124	D9	-	-	-	PG9	I/O	FT	PG9	-
125	D8	-	-	-	PG10	I/O	FT	PG10	-
126	-	-	-	-	PG11	I/O	FT	PG11	-
127	D7	-	-	-	PG12	I/O	FT	PG12	-
128	C7	-	-	-	PG13	I/O	FT	PG13	-
129	C6	-	-	-	PG14	I/O	FT	PG14	-
130	-	-	-	-	VSS_11	S	-	VSS_11	-
131	-	-	-	-	VDD_11	S	-	VDD_11	-
132	-	-	-	-	PG15	I/O	FT	PG15	-
133	A8	89	55	A4	PB3	I/O	FT	JTDO	TIM2_CH2/SPI1_SCK/ SPI3_SCK/ I2S3_CK/ LCD_SEG7/JTDO

Table 8. STM32L151xC/C-A and STM32L152xC/C-A pin definitions (continued)

		Pins							Pin functions
LQFP144	UFBGA132	LQFP100	LQFP64	WLCSP64	Pin name	Pin Type(1)	I / O structure	Main function(2) (after reset)	Alternate functions
134	A7	90	56	B4	PB4	I/O	FT	NJTRST	TIM3_CH1/SPI1_MISO/ SPI3_MISO/ LCD_SEG8/NJTRST
135	C5	91	57	A5	PB5	I/O	FT	PB5	TIM3_CH2/I2C1_SMBA/ SPI1_MOSI/ SPI3_MOSI/ I2S3_SD/LCD_SEG9
136	B5	92	58	B5	PB6	I/O	FT	PB6	TIM4_CH1/I2C1_SCL/ USART1_TX/
137	B4	93	59	C5	PB7	I/O	FT	PB7	TIM4_CH2/I2C1_SDA/ USART1_RX
138	A4	94	60	A6	BOOT0	I	B	BOOT0	-
139	A3	95	61	D5	PB8	I/O	FT	PB8	TIM4_CH3/TIM10_CH1/ I2C1_SCL/ LCD_SEG16
140	B3	96	62	B6	PB9	I/O	FT	PB9	TIM4_CH4/ TIM11_CH1/I2C1_SDA/ LCD_COM3
141	C3	97	-	-	PE0	I/O	FT	PE0	TIM4_ETR/TIM10_CH1/ LCD_SEG36
142	A2	98	-	-	PE1	I/O	FT	PE1	TIM11_CH1/LCD_SEG37
143	D3	99	63	A7	VSS_3	S	-	VSS_3	-
144	C4	100	64	A8	VDD_3	S	-	VDD_3	-

^1. I = input, O = output, S = supply.

^2. Function availability depends on the chosen device.

^3. Applicable to STM32L152xD devices only. In STM32L151xD devices, this pin should be connected to VDD.

^4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).

^5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO function.

				Ta b	le 9. A l te	fu te rn a	t io in nc n	/o t tp t p u u u
						D ig i l a l ta te	fu te rn a	ion be t nc n um
	A F I O 0	A F I O 1	A F I O 2	A F I O 3	A F I O 4	A F I O 5	A F I O 6	A F I O 7
Po t n r am e						A l	te te fu rn a	t ion nc
	S Y S T E M	T I M 2	T I M 3 / 4 / 5	T / 1 I M 9 / 0 1 1	I 2 C 1 / 2	S P I 1 / 2	S P I 3	U S A R T 1 / 2 / 3
BO OT 0	BO OT 0	-	-	-	-	-	-	-
NR ST	NR ST	-	-	-	-	-	-	-
PA 0-W KU P1	-	TIM 2_ CH 1_ ET	R T IM5 CH 1 _	-	-	-	-	US AR T2_ CT S
PA 1	-	TIM 2_ CH 2	TIM 5_ CH 2	-	-	-	-	US AR T2_ RT S
PA 2	-	TIM 2_ CH 3	TIM 5_ CH	3 T IM9 CH 1 _	-	-	-	US AR T2_ TX
3 PA	-	2_ CH TIM 4	CH TIM 5_	IM9 CH 2 4 T _	-	-	-	US T2_ AR RX
PA4	-	-	-	-	-	SP I1_ NS S	SP S I2S I3_ NS 3_ WS	US AR T2_ CK
PA 5	-	TIM 2_ CH 1_ ET R	-	-	-	SP I1_ SC K	-	-
PA 6	-	-	TIM 3_ CH	1 T IM1 0_ CH 1	-	SP I1_ MIS O	-	-
PA 7	-	-	TIM 3_ CH	2 T IM1 1_ CH 1	-	SP I1_ MO SI	-	-
PA 8	MC O	-	-	-	-	-	-	US CK AR T1_
PA 9	-	-	-	-	-	-	-	US AR T1_ TX
PA 10	-	-	-	-	-	-	-	US AR T1_ RX
PA 11	-	-	-	-	-	SP I1_ MIS O	-	US AR T1_ CT S

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 18 and Table 44, respectively.

Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 13.

Table 44. I/O AC characteristics(1)

OSPEEDRx [1:0] bit value(1)	Symbol	Parameter	Conditions	Min	Max(2)	Unit
		Maximum frequency(3)	CL = 50 pF, VDD = 2.7 V to 3.6 V	-	400
	fmax(IO)out		CL = 50 pF, VDD = 1.65 V to 2.7 V	-	400	kHz
00	tf(IO)out		CL = 50 pF, VDD = 2.7 V to 3.6 V	-	625
	tr(IO)out	Output rise and fall time	CL = 50 pF, VDD = 1.65 V to 2.7 V	-	625	ns
		Maximum frequency(3)	CL = 50 pF, VDD = 2.7 V to 3.6 V	-	2
	fmax(IO)out		CL = 50 pF, VDD = 1.65 V to 2.7 V	-	1	MHz
01	tf(IO)out tr(IO)out	CL = 50 pF, VDD = 2.7 V to 3.6 V Output rise and fall time CL = 50 pF, VDD = 1.65 V to 2.7 V		-	125
				-	250	ns
			CL = 50 pF, VDD = 2.7 V to 3.6 V	-	10
	Fmax(IO)out	Maximum frequency(3)	CL = 50 pF, VDD = 1.65 V to 2.7 V	-	2	MHz
10	tf(IO)out		CL = 50 pF, VDD = 2.7 V to 3.6 V	-	25	ns
	tr(IO)out	Output rise and fall time	CL = 50 pF, VDD = 1.65 V to 2.7 V	-	125
			CL = 30 pF, VDD = 2.7 V to 3.6 V	-	50
	Fmax(IO)out	Maximum frequency(3)	CL = 50 pF, VDD = 1.65 V to 2.7 V	-	8	MHz
11	tf(IO)out		CL = 30 pF, VDD = 2.7 V to 3.6 V	-	5
	tr(IO)out	Output rise and fall time	CL = 50 pF, VDD = 1.65 V to 2.7 V	-	30
-	tEXTIpw	Pulse width of external signals detected by the EXTI controller	-	8	-	ns

^2. Guaranteed by design.

^3. The maximum frequency is defined in Figure 18.

Figure 18. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics, Table 11: Current characteristics, and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD–VSS	External main supply voltage (1) (including VDDA and VDD)	–0.3	4.0
VIN(2)	Input voltage on five-volt tolerant pin	VSS - 0.3	VDD+4.0	V
	Input voltage on any other pin	VSS - 0.3	4.0
ΔVDDx	Variations between different VDD power pins	-	50
VSSX - VSS	Variations between all different ground pins(3)	-	50	mV

VREF+ –VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V

Table 11. Current characteristics

(human body model) see Section 6.3.11 -

Table 10. Voltage characteristics

Electrostatic discharge voltage

VESD(HBM)

Symbol Ratings Max. Unit

Symbol	Ratings	Max.	Unit
IVDD(Σ)	Total current into sum of all VDD_x power lines (source)(1)	100
(2) IVSS(Σ)	Total current out of sum of all VSS_x ground lines (sink)(1)	100
IVDD(PIN)	Maximum current into each VDD_x power pin (source)(1)	70
IVSS(PIN)	Maximum current out of each VSS_x ground pin (sink)(1)	-70
	Output current sunk by any I/O and control pin	25
IIO	Output current sourced by any I/O and control pin	- 25	mA
	Total output current sunk by sum of all IOs and control pins(2)	60
ΣIIO(PIN)	Total output current sourced by sum of all IOs and control pins(2)	-60
	Injected current on five-volt tolerant I/O(4), RST and B pins	-5/+0
IINJ(PIN) (3)	Injected current on any other pin (5)	± 5
ΣIINJ(PIN)	Total injected current (sum of all I/O and control pins)(6)	± 25

^1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

^2. VIN maximum must always be respected. Refer to Table 11 for maximum allowed injected current values.

^3. Include VREF- pin.

^2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

^3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.

Positive current injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN) must never be exceeded. Refer to Table 10 for maximum allowed input voltage values.
1. A positive injection is induced by V_IN > V_DD while a negative injection is induced by V_IN < V_SS. I_INJ(PIN) must never be exceeded. Refer to Table 10: Voltage characteristics for the maximum allowed input voltage values.
1. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 12. Thermal characteristics

Symbol	Ratings	Value	Unit
T _STG	Storage temperature range	-65 to +150	°C
T _J	Maximum junction temperature	150	°C

Thermal Information

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max × ΘJA)

Where:

TA max is the maximum ambient temperature in °C,
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$P_I/O max = sum (V_OL × I_OL) + sum ((V_DD - V_OH) × I_OH),$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol	Parameter	Value	Unit
	Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch	40
	Thermal resistance junction-ambient UFBGA132 - 7 x 7 mm	60
ΘJA	Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch	43	°C/W
	Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch	46
	Thermal resistance junction-ambient WLCSP64 - 0.400 mm pitch	46

Figure 46. Thermal resistance suffix 6

7.6.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
SMTWEM2515STR		SMD
STM32L151QC	—	—
STM32L151RC-A	—	—
STM32L151VC-A	—	—
STM32L151ZC	—	—
STM32L152QC	—	—
STM32L152VC-A	—	—
STM32L152ZC	—	—
STM32L15X	—	—

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