STM32L011F4

The access line ultra-low-power STM32L011x3/4 family incorporates the high-performance Arm ® Cortex ® -M0+ 32-bit RISC core operating at a 32 MHz frequency, high-speed embedded memories (up to 16 Kbytes of Flash program memory, 512 bytes of data EEPROM and 2 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.

The STM32L011x3/4 devices provide high power efficiency for a wide range of performance. It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes.

The STM32L011x3/4 devices offer several analog features, one 12-bit ADC with hardware oversampling, two ultra-low-power comparators, several timers, one low-power timer (LPTIM), three general-purpose 16-bit timers, one RTC and one SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock.

Moreover, the STM32L011x3/4 devices embed standard and advanced communication interfaces: one I2C, one SPI, one USART, and a low-power UART (LPUART).

The STM32L011x3/4 also include a real-time clock and a set of backup registers that remain powered in Standby mode.

The ultra-low-power STM32L011x3/4 devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications.

• Ultra-low-power platform
• -1.65 V to 3.6 V power supply
• --40 to 125 °C temperature range
• -0.23 μA Standby mode (2 wakeup pins)
• -0.29 μA Stop mode (16 wakeup lines)
• -0.54 μA Stop mode + RTC + 2 KB RAM retention
• -Down to 76 μA/MHz in Run mode
• -5 μs wakeup time (from Flash memory)
• -41 μA 12-bit ADC conversion at 10 ksps
• Core: Arm ® 32-bit Cortex ® -M0+
• -From 32 kHz to 32 MHz max.
• -0.95 DMIPS/MHz
• Reset and supply management
• -Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds
• -Ultralow power POR/PDR
• -Programmable voltage detector (PVD)
• Clock sources
• -0 to 32 MHz external clock
• -32 kHz oscillator for RTC with calibration
• -High speed internal 16 MHz factory-trimmed RC (+/- 1%)
• -Internal low-power 37 kHz RC
• -Internal multispeed low-power 65 kHz to 4.2 MHz RC
• -PLL for CPU clock
• Pre-programmed bootloader
• -USART, SPI supported
• Development support
• -Serial wire debug supported
• Up to 28 fast I/Os (23 I/Os 5V tolerant)
• Memories
• -Up to 16 KB Flash memory with ECC
• -2 KB RAM
• -512 B of data EEPROM with ECC
• -20-byte backup register
• -Sector protection against R/W operation

Figure 3. STM32L011x3/4 LQFP32 pinout

1. The above figure shows the package top view.
2. The above figure shows the package top view.

Figure 4. STM32L011x3/4 UFQFPN32 pinout

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Figure 5. STM32L011x3/4 WLCSP25 pinout

1. The above figure shows the package top view.
2. The above figure shows the package top view.

Figure 6. STM32L011x3/4 UFQFPN28 pinout

Figure 7. STM32L011x3/4 UFQFPN20 pinout

1. The above figure shows the package top view.
2. The above figure shows the package top view.

Figure 8. STM32L011x3/4 TSSOP20 pinout

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Figure 9. STM32L011x3/4 TSSOP14 pinout

1. The above figure shows the package top view.

Table 12. Legend/abbreviations used in the pinout table

Table 13. Pin definitions

Table 13. Pin definitions

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Table 13. Pin definitions (continued)

Table 13. Pin definitions (continued)

Table 13. Pin definitions (continued)

Table 13. Pin definitions (continued)

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Table 13. Pin definitions (continued)

1. VSS pins are connected to the exposed pad (see Figure 35: UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline ).
2. Device reset input/internal reset output (active low).
3. Analog power supply.
4. On TSSOP14 package, V DDA is internally connected to V DD .
5. Digital and analog ground.
6. Digital power supply.
7. PA14 pin on TSSOP14 package acts as an output pin when the embedded bootloader is active (SPI1_MISO). On empty devices (devices from factory), the bootloader is active due to the empty check mechanism (refer to RM0377 reference manual). PA14 pin also acts as SWCLK. When programming devices in TSSOP14 for the first time, it is necessary to use the "connect under reset" method and the SWD interface to disable the bootloader by driving this PA14/SWCLK pin.

Table 14. Alternate functions

Table 14. Alternate functions

Table 14. Alternate functions

Table 14. Alternate functions (continued)

The definition and values of input/output AC characteristics are given in Figure 25 and Table 52 , respectively.

Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 18 .

Table 52. I/O AC characteristics (1)(2)

1. BOOT0/PB9 maximum input frequency is 10 kHz (1.65 V < V DD < 2.7 V) and 5 MHz (2.7 V < V DD < 3.6 V).
2. Guaranteed by design. Not tested in production.
3. The maximum frequency is defined in Figure 25 .

Figure 25. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics , Table 16: Current characteristics , and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand.

Table 15. Voltage characteristics

Table 16. Current characteristics

Table 16. Current characteristics

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
2. These values apply only to STM32L011GxUx part number (UFQFPN28 package).
3. This current consumption must be correctly distributed over all I/Os and control pins. In particular, it must be located the closest possible to the couple of supply and ground, and distributed on both sides.
4. Positive current injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 15 for maximum allowed input voltage values.
5. A positive injection is induced by V IN > V DD while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 15: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 17. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max × Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at http://www.st.com. ECOPACK ® is an ST trademark.