STM32G071CXT

Part: STM32G071x8/xB

Type: Arm Cortex-M0+ 32-bit MCU

Description: 32-bit Arm Cortex-M0+ MCU with CPU frequency up to 64 MHz, up to 128 KB Flash memory, 36 KB SRAM, and a 1.7 V to 3.6 V operating voltage range.

Operating Conditions:

• Supply voltage: 1.7 V to 3.6 V
• Operating temperature: -40°C to 125°C
• Max CPU frequency: 64 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V (VDD, VDDIOx, VDDA)
• Max junction/storage temperature: 125 °C (Junction), 150 °C (Storage)

Key Specs:

• Core: Arm 32-bit Cortex-M0+ CPU
• Flash memory: Up to 128 Kbytes
• SRAM: 36 Kbytes (32 Kbytes with HW parity check)
• ADC: 12-bit, 0.4 μs, up to 16 external channels, 0 to 3.6V conversion range
• DAC: Two 12-bit DACs
• I2C interfaces: Two, supporting Fast-mode Plus (1 Mbit/s)
• USARTs: Four, with master/slave synchronous SPI
• SPIs: Two (32 Mbit/s) with 4- to 16-bit programmable bitframe

Features:

• CRC calculation unit
• Power-on/Power-down reset (POR/PDR)
• Programmable Brownout reset (BOR)
• Low-power modes: Sleep, Stop, Standby, Shutdown
• VBAT supply for RTC and backup registers
• Up to 60 fast I/Os, multiple 5 V-tolerant I/Os
• 7-channel DMA controller
• Two fast low-power analog comparators
• 14 timers (two 128 MHz capable)
• Calendar RTC with alarm and periodic wakeup
• One low-power UART
• HDMI CEC interface
• USB Type-C Power Delivery controller
• Serial wire debug (SWD)
• 96-bit unique ID

Applications:

Package:

• WLCSP25
• UFQFPN28
• LQFP32
• UFQFPN32
• LQFP48
• UFQFPN48
• LQFP64
• UFBGA64

• Includes ST state-of-the-art patented technology
• Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 64 MHz
• -40°C to 85°C/105°C/125°C operating temperature
• Memories
• -36 Kbytes of SRAM (32 Kbytes with HW parity check)
• -Up to 128 Kbytes of flash memory with protection and securable area
• CRC calculation unit
• Reset and power management
• -Power-on/Power-down reset (POR/PDR)
• -Voltage range: 1.7 V to 3.6 V
• -Programmable Brownout reset (BOR)
• -Low-power modes:
• -Programmable voltage detector (PVD)
• Sleep, Stop, Standby, Shutdown
• -VBAT supply for RTC and backup registers
• Clock management
• -32 kHz crystal oscillator with calibration
• -4 to 48 MHz crystal oscillator
• -Internal 16 MHz RC with PLL option (±1 %)
• -Internal 32 kHz RC oscillator (±5 %)
• Up to 60 fast I/Os
• -Multiple 5 V-tolerant I/Os
• -All mappable on external interrupt vectors
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 16 ext. channels)
• -Conversion range: 0 to 3.6V
• -Up to 16-bit with hardware oversampling
• Two 12-bit DACs, low-power sample-and-hold
• Two fast low-power analog comparators, with programmable input and output, rail-to-rail
• 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown

The devices housed in 28-pin and 32-pin packages come in two variants - 'GP' and 'N' (the latter with ordering code having N behind the temperature range digit). Refer to Table 2: Features and peripheral counts for differences.

Figure 3. STM32G071Ex WLCSP25 ballout

Figure 4. STM32G071GxU UFQFPN28 pinout

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Figure 5. STM32G071KxT LQFP32 pinout

Figure 6. STM32G071KxU UFQFPN32 pinout

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Figure 7. STM32G071CxT LQFP48 pinout

Figure 8. STM32G071CxU UFQFPN48 pinout

Figure 9. STM32G071RxT LQFP64 pinout

Figure 10. STM32G071RxI UFBGA64 ballout

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Table 11. Terms and symbols used in Pin assignment and description table

Table 12. Pin assignment and description

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

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Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

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Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

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Table 12. Pin assignment and description (continued)

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

• These GPIOs must not be used as current sources (for example to drive a LED).
• The speed should not exceed 2 MHz with a maximum load of 30 pF

1. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
2. RST I/O structure when the PF2-NRST pin is configured as reset (input or input/output mode), FT I/O structure when the PF2-NRST pin is configured as GPIO.
3. Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2, depending on the voltage level on PA9/PC6, PA10/PB0, PD1, and PD3, respectively. In order to disable this resistor, strobe the UCPDx_STROBE bit of the SYSCFG_CFGR1 register during start-up sequence.
4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Table 13. Port A alternate function mapping

Table 13. Port A alternate function mapping

Table 13. Port A alternate function mapping

Table 14. Port B alternate function mapping

Table 14. Port B alternate function mapping

Table 15. Port C alternate function mapping

Table 15. Port C alternate function mapping

Stresses above the absolute maximum ratings listed in Table 18 , Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to V SS .

Table 18. Voltage characteristics

1. Refer to Table 19 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. When an FT_a pin is used by an analog peripheral such as ADC, the maximum V IN is 4 V.

Table 19. Current characteristics

Table 19. Current characteristics

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Table 19. Current characteristics (continued)

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
2. On these I/Os, any current injection disturbs the analog performances of the device.
3. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

The operating junction temperature T J must never exceed the maximum given in Table 21: General operating conditions .

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:T _ { J } ( max ) = T _ { A } ( max ) + P _ { D } ( max ) × Θ _ { J A }$

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.