STM32G071CBT6

Part: STM32G071x8/xB

Type: ARM Cortex-M0+ 32-bit MCU

Key Specs:

• Core frequency: up to 64 MHz
• Flash memory: Up to 128 Kbytes
• SRAM: 36 Kbytes
• Voltage range: 1.7 V to 3.6 V
• Operating temperature: -40°C to 85°C/105°C/125°C
• ADC resolution: 12-bit
• ADC conversion time: 0.4 μs
• SPI speed: 32 Mbit/s

Features:

• Core: Arm® 32-bit Cortex®-M0+ CPU
• Memories: Up to 128 Kbytes of flash memory with protection and securable area, 36 Kbytes of SRAM (32 Kbytes with HW parity check)
• CRC calculation unit
• Reset and power management: Power-on/Power-down reset (POR/PDR), Programmable Brownout reset (BOR), Programmable voltage detector (PVD), Low-power modes (Sleep, Stop, Standby, Shutdown), VBAT supply for RTC and backup registers
• Clock management: 4 to 48 MHz crystal oscillator, 32 kHz crystal oscillator with calibration, Internal 16 MHz RC with PLL option (±1 %), Internal 32 kHz RC oscillator (±5 %)
• Up to 60 fast I/Os, multiple 5 V-tolerant I/Os
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 16 ext. channels), up to 16-bit with hardware oversampling, conversion range: 0 to 3.6V
• Two 12-bit DACs, low-power sample-and-hold
• Two fast low-power analog comparators, with programmable input and output, rail-to-rail
• 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16-bit general-purpose, two basic 16-bit, two low-power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown
• Communication interfaces: Two I2C-bus interfaces (Fast-mode Plus, SMBus/PMBus, wakeup from Stop mode), Four USARTs (master/slave synchronous SPI, ISO7816, LIN, IrDA, auto baud rate detection, wakeup feature), One low-power UART, Two SPIs (32 Mbit/s, 4- to 16-bit programmable bitframe, one multiplexed with I2S interface), HDMI CEC interface
• USB Type-C™ Power Delivery controller
• Development support: serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK 2 compliant

Applications:

• null

Package:

• null

• Includes ST state-of-the-art patented technology
• Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 64 MHz
• -40°C to 85°C/105°C/125°C operating temperature
• Memories
  • Up to 128 Kbytes of flash memory with protection and securable area
  • 36 Kbytes of SRAM (32 Kbytes with HW parity check)
• CRC calculation unit
• Reset and power management
  • Voltage range: 1.7 V to 3.6 V
  • Power-on/Power-down reset (POR/PDR)
  • Programmable Brownout reset (BOR)
  • Programmable voltage detector (PVD)
  • Low-power modes: Sleep, Stop, Standby, Shutdown
  • V_BAT supply for RTC and backup registers
• Clock management
  • 4 to 48 MHz crystal oscillator
  • 32 kHz crystal oscillator with calibration
  • Internal 16 MHz RC with PLL option (±1 %)
  • Internal 32 kHz RC oscillator (±5 %)
• Up to 60 fast I/Os
  • All mappable on external interrupt vectors
  • Multiple 5 V-tolerant I/Os
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 16 ext. channels)
  • Up to 16-bit with hardware oversampling
  • Conversion range: 0 to 3.6V
• Two 12-bit DACs, low-power sample-and-hold
• Two fast low-power analog comparators, with programmable input and output, rail-to-rail
• 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown

• Communication interfaces
  • Two I²C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
  • Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
  • One low-power UART
  • Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I²S interface; four extra SPIs through USARTs
  • HDMI CEC interface, wakeup on header
• USB Type-C™ Power Delivery controller
• Development support: serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK 2 compliant

Table 1. Device summary

Reference	Part number
STM32G071x8	STM32G071C8, STM32G071G8, STM32G071K8, STM32G071R8
STM32G071xB	STM32G071CB, STM32G071EB, STM32G071GB, STM32G071KB, STM32G071RB

Contents STM32G071x8/xB

The devices housed in 28-pin and 32-pin packages come in two variants - "GP" and "N" (the latter with ordering code having N behind the temperature range digit). Refer to Table 2: Features and peripheral counts for differences.

Figure 3. STM32G071Ex WLCSP25 ballout

Figure 4. STM32G071GxU UFQFPN28 pinout

Figure 5. STM32G071KxT LQFP32 pinout

Figure 6. STM32G071KxU UFQFPN32 pinout

MSv39711V3 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF2-NRST PF0-OSC_IN PF1-OSC_OUT PA0 PA1 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view LQFP48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24

Figure 7. STM32G071CxT LQFP48 pinout

MSv39710V3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 PB12 PC11 PC12 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF2-NRST PF0-OSC_IN PF1-OSC_OUT PC0 PC1 PC2 PC3 PC8 PA15 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PD9 PD8 PC7 PC6 PA9 PA8 PB15 PB14 PB13 Top view PC10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC9 LQFP64 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 47 63 62 61 59 57 56 54 51 49 17 18 19 20 21 23 24 25 26 27 28 29 30 31

Figure 9. STM32G071RxT LQFP64 pinout

Table 11. Terms and symbols used in Pin assignment and description table

| | Column | Symbol | Definition | |--------------------------------------|------------------------|------------------------------------------------------------------|----------------------------------------------------------------------------------------------|--|--|--|--|--|--| | | Pin name | parenthesis under the pin name. | Terminal name corresponds to its by-default function at reset, unless otherwise specified in | | | | S | Supply pin | | | Pin type | I | Input only pin | | | | I/O | Input / output pin | | | | FT | 5 V tolerant I/O | | | | TT | 3.6 V tolerant I/O | | | | RST | Reset pin with embedded weak pull-up resistor | | | I/O structure | Options for TT or FT I/Os | | | | _f | I/O, Fm+ capable | | | | _a
I/O, with analog switch function | | | | _c | I/O, USB Type-C PD capable | | | | _d | I/O, USB Type-C PD Dead Battery function | | | Note | | Upon reset, all I/Os are set as analog inputs, unless otherwise specified. | | Pin | Alternate
functions | Functions selected through GPIOx_AFR registers | | functions
Additional
functions | | Functions directly selected/enabled through peripheral registers | Table 12. Pin assignment and description

| | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|--------|------------------------------------------|------------------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | - | - | - | - | - | A1 | 1 | PC11 | I/O | FT | - | USART3_RX, USART4_RX,
TIM1_CH4 | - | | - | - | - | - | - | - | B2 | 2 | PC12 | I/O | FT | - | LPTIM1_IN1,
UCPD1_FRSTX,
TIM14_CH1 | - | | - | - | - | - | - | 1 | C2 | 3 | PC13 | I/O | FT | (1)(2) | TIM1_BKIN | TAMP_IN1,RTC_TS,
RTC_OUT1,WKUP2 |

Table 12. Pin assignment and description (continued)

| | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|--------|-----------------------------------------------------------------------------------------------|---------------------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | - | - | - | - | 2 | C1 | 4 | PC14-
OSC32_IN
(PC14) | I/O | FT | (1)(2) | TIM1_BKIN2 | OSC32_IN | | A5 | 1 | 1 | 2 | 2 | - | - | - | PC14-
OSC32_IN
(PC14) | I/O | FT | (1)(2) | TIM1_BKIN2 | OSC32_IN,OSC_IN | | B5 | 2 | 2 | 3 | 3 | 3 | B1 | 5 | PC15-
OSC32_OUT
(PC15) | I/O | FT | (1)(2) | OSC32_EN, OSC_EN,
TIM15_BKIN | OSC32_OUT | | - | - | - | - | - | 4 | D3 | 6 | VBAT | S | - | - | - | - | | - | - | - | - | - | 5 | D2 | 7 | VREF+ | S | - | - | - | VREF_OUT | | C5 | 3 | 3 | 4 | 4 | 6 | D1 | 8 | VDD/VDDA | S | - | - | - | - | | D5 | 4 | 4 | 5 | 5 | 7 | E1 | 9 | VSS/VSSA | S | - | - | - | - | | - | - | - | - | - | 8 | F1 | 10 | PF0-OSC_IN
(PF0) | I/O | FT | - | TIM14_CH1 | OSC_IN | | - | - | - | - | - | 9 | G1 | 11 | PF1-
OSC_OUT
(PF1) | I/O | FT | - | OSC_EN, TIM15_CH1N | OSC_OUT | | E5 | 5 | 5 | 6 | 6 | 10 | E2 | 12 | PF2 - NRST | I/O | RST, FT | (3) | MCO | NRST | | - | - | - | - | - | - | E3 | 13 | PC0 | I/O | FT | - | LPTIM1_IN1,
LPUART1_RX, LPTIM2_IN1 | - | | - | - | - | - | - | - | F2 | 14 | PC1 | I/O | FT | - | LPTIM1_OUT,
LPUART1_TX, TIM15_CH1 | - | | - | - | - | - | - | - | G2 | 15 | PC2 | I/O | FT | - | LPTIM1_IN2, SPI2_MISO,
TIM15_CH2 | - | | - | - | - | - | - | - | H1 | 16 | PC3 | I/O | FT | - | LPTIM1_ETR, SPI2_MOSI,
LPTIM2_ETR | - | | C4 | 6 | 6 | 7 | 7 | 11 | H2 | 17 | PA0 | I/O | FT_a | - | SPI2_SCK, USART2_CTS,
TIM2_CH1_ETR,
USART4_TX, LPTIM1_OUT,
UCPD2_FRSTX,
COMP1_OUT | COMP1_INM, ADC_IN0,
TAMP_IN2,WKUP1 |

Table 12. Pin assignment and description (continued)

| | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|------|------------------------------------------------------------------------------------------------------|----------------------------------------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | D4 | 7 | 7 | 8 | 8 | 12 | H3 | 18 | PA1 | I/O | FT_a | - | SPI1_SCK/I2S1_CK,
USART2_RTS_DE_CK,
TIM2_CH2, USART4_RX,
TIM15_CH1N, I2C1_SMBA,
EVENTOUT | COMP1_INP, ADC_IN1 | | E4 | 8 | 8 | 9 | 9 | 13 | G3 | 19 | PA2 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD,
USART2_TX, TIM2_CH3,
UCPD1_FRSTX,
TIM15_CH1, LPUART1_TX,
COMP2_OUT | COMP2_INM, ADC_IN2,
WKUP4,LSCO | | C3 | 9 | 9 | 10 | 10 | 14 | F3 | 20 | PA3 | I/O | FT_a | - | SPI2_MISO, USART2_RX,
TIM2_CH4,
UCPD2_FRSTX,
TIM15_CH2, LPUART1_RX,
EVENTOUT | COMP2_INP, ADC_IN3 | | - | - | - | - | - | 15 | H4 | 21 | PA4 | I/O | TT_a | - | SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
LPTIM2_OUT,
UCPD2_FRSTX,
EVENTOUT | ADC_IN4, DAC_OUT1,
RTC_OUT2 | | D3 | 10 | 10 | 11 | 11 | - | - | - | PA4 | I/O | TT_a | - | SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
LPTIM2_OUT,
UCPD2_FRSTX,
EVENTOUT | ADC_IN4, DAC_OUT1,
TAMP_IN1,RTC_TS,
RTC_OUT1,WKUP2 | | E3 | 11 | 11 | 12 | 12 | 16 | G4 | 22 | PA5 | I/O | TT_a | - | SPI1_SCK/I2S1_CK, CEC,
TIM2_CH1_ETR,
USART3_TX, LPTIM2_ETR,
UCPD1_FRSTX,
EVENTOUT | ADC_IN5, DAC_OUT2 | | C2 | 12 | 12 | 13 | 13 | 17 | F4 | 23 | PA6 | I/O | FT_a | - | SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
USART3_CTS, TIM16_CH1,
LPUART1_CTS,
COMP1_OUT | ADC_IN6 | | D2 | 13 | 13 | 14 | 14 | 18 | E4 | 24 | PA7 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM1_CH1N,
TIM14_CH1, TIM17_CH1,
UCPD1_FRSTX,
COMP2_OUT | ADC_IN7 | | - | - | - | - | - | - | H5 | 25 | PC4 | I/O | FT_a | - | USART3_TX, USART1_TX,
TIM2_CH1_ETR | COMP1_INM,
ADC_IN17 |

Table 12. Pin assignment and description (continued)

| | | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|------|-------------------------------------------------------------------------------------------------------|-------------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | - | - | - | - | - | H6 | 26 | PC5 | I/O | FT_a | - | USART3_RX, USART1_RX,
TIM2_CH2 | COMP1_INP,
ADC_IN18, WKUP5 | | E2 | 14 | - | 15 | 15 | 19 | F5 | 27 | PB0 | I/O | FT_a | - | SPI1_NSS/I2S1_WS,
TIM3_CH3, TIM1_CH2N,
USART3_RX, LPTIM1_OUT,
UCPD1_FRSTX,
COMP1_OUT | ADC_IN8 | | - | - | 14 | - | - | - | - | - | PB0 | I/O | FT_da | (4) | SPI1_NSS/I2S1_WS,
TIM3_CH3, TIM1_CH2N,
USART3_RX, LPTIM1_OUT,
UCPD1_FRSTX,
COMP1_OUT | UCPD1_DBCC2,
ADC_IN8 | | E1 | 15 | - | 16 | 16 | 20 | G5 | 28 | PB1 | I/O | FT_a | - | TIM14_CH1, TIM3_CH4,
TIM1_CH3N,
USART3_RTS_DE_CK,
LPTIM2_IN1,
LPUART1_RTS_DE,
EVENTOUT | COMP1_INM, ADC_IN9 | | - | - | - | 17 | - | 21 | H7 | 29 | PB2 | I/O | FT_a | - | SPI2_MISO, USART3_TX,
LPTIM1_OUT, EVENTOUT | COMP1_INP, ADC_IN10 | | - | - | - | - | - | 22 | G6 | 30 | PB10 | I/O | FT_fa | - | CEC, LPUART1_RX,
TIM2_CH3, USART3_TX,
SPI2_SCK, I2C2_SCL,
COMP1_OUT | ADC_IN11 | | - | - | - | - | - | 23 | H8 | 31 | PB11 | I/O | FT_fa | - | SPI2_MOSI, LPUART1_TX,
TIM2_CH4, USART3_RX,
I2C2_SDA, COMP2_OUT | ADC_IN15 | | - | - | - | - | - | 24 | G7 | 32 | PB12 | I/O | FT_a | - | SPI2_NSS,
LPUART1_RTS_DE,
TIM1_BKIN, TIM15_BKIN,
UCPD2_FRSTX,
EVENTOUT | ADC_IN16 | | - | - | - | - | - | 25 | G8 | 33 | PB13 | I/O | FT_f | - | SPI2_SCK, LPUART1_CTS,
TIM1_CH1N,
USART3_CTS,
TIM15_CH1N, I2C2_SCL,
EVENTOUT | - |

Table 12. Pin assignment and description (continued)

| | | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|------|---------------------------------------------------------------------------------------------------|--------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | - | - | - | - | 26 | F6 | 34 | PB14 | I/O | FT_f | - | SPI2_MISO,
UCPD1_FRSTX,
TIM1_CH2N,
USART3_RTS_DE_CK,
TIM15_CH1, I2C2_SDA,
EVENTOUT | - | | - | - | 15 | - | 17 | 27 | F7 | 35 | PB15 | I/O | FT_c | (4) | SPI2_MOSI, TIM1_CH3N,
TIM15_CH1N, TIM15_CH2,
EVENTOUT | UCPD1_CC2,
RTC_REFIN, | | D1 | 16 | 16 | 18 | 18 | 28 | F8 | 36 | PA8 | I/O | FT_c | (4) | MCO, SPI2_NSS,
TIM1_CH1, LPTIM2_OUT,
EVENTOUT | UCPD1_CC1 | | - | - | - | 19 | 19 | 29 | E6 | 37 | PA9 | I/O | FT_fd | (4) | MCO, USART1_TX,
TIM1_CH2, SPI2_MISO,
TIM15_BKIN, I2C1_SCL,
EVENTOUT | UCPD1_DBCC1 | | - | 17 | - | 20 | 20 | 30 | E7 | 38 | PC6 | I/O | FT | - | UCPD1_FRSTX,
TIM3_CH1, TIM2_CH3 | - | | - | - | 17 | - | - | - | - | - | PC6 | I/O | FT_d | (4) | UCPD1_FRSTX,
TIM3_CH1, TIM2_CH3 | UCPD1_DBCC1 | | - | - | - | - | - | 31 | E5 | 39 | PC7 | I/O | FT | - | UCPD2_FRSTX,
TIM3_CH2, TIM2_CH4 | - | | - | - | - | - | - | - | E8 | 40 | PD8 | I/O | FT | - | USART3_TX,
SPI1_SCK/I2S1_CK,
LPTIM1_OUT | - | | - | - | - | - | - | - | D8 | 41 | PD9 | I/O | FT | - | USART3_RX,
SPI1_NSS/I2S1_WS,
TIM1_BKIN2 | - | | - | - | - | 21 | 21 | 32 | D6 | 42 | PA10 | I/O | FT_fd | (4) | SPI2_MOSI, USART1_RX,
TIM1_CH3, TIM17_BKIN,
I2C1_SDA, EVENTOUT | UCPD1_DBCC2 | | C1 | 18 | 18 | 22 | 22 | 33 | C8 | 43 | PA11
PA9 | I/O | FT_f | - | SPI1_MISO/I2S1_MCK,
USART1_CTS, TIM1_CH4,
TIM1_BKIN2, I2C2_SCL,
COMP1_OUT | - | | B1 | 19 | 19 | 23 | 23 | 34 | B8 | 44 | PA12
PA10 | I/O | FT_f | - | SPI1_MOSI/I2S1_SD,
USART1_RTS_DE_CK,
TIM1_ETR, I2S_CKIN,
I2C2_SDA, COMP2_OUT | - |

Table 12. Pin assignment and description (continued)

| | | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|------|--------------------------------------------------------------------------------------------------------|-------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | B2 | 20 | 20 | 24 | 24 | 35 | D7 | 45 | PA13 | I/O | FT | (6) | SWDIO, IR_OUT,
EVENTOUT | - | | A2 | 21 | 21 | 25 | 25 | 36 | C7 | 46 | PA14-BOOT0 | I/O | FT | (6) | SWCLK, USART2_TX,
EVENTOUT | BOOT0 | | A1 | 22 | - | 26 | - | 37 | C6 | 47 | PA15 | I/O | FT | - | SPI1_NSS/I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
USART4_RTS_DE_CK,
USART3_RTS_DE_CK,
EVENTOUT | - | | - | - | - | - | - | - | A8 | 48 | PC8 | I/O | FT | - | UCPD2_FRSTX,
TIM3_CH3, TIM1_CH1 | - | | - | - | - | - | - | - | B7 | 49 | PC9 | I/O | FT | - | I2S_CKIN, TIM3_CH4,
TIM1_CH2 | - | | - | - | 22 | - | 26 | 38 | A7 | 50 | PD0 | I/O | FT_c | (4) | EVENTOUT, SPI2_NSS,
TIM16_CH1 | UCPD2_CC1 | | - | - | 23 | - | 27 | 39 | B6 | 51 | PD1 | I/O | FT_d | (4) | EVENTOUT, SPI2_SCK,
TIM17_CH1 | UCPD2_DBCC1 | | - | - | 24 | - | 28 | 40 | A6 | 52 | PD2 | I/O | FT_c | (4) | USART3_RTS_DE_CK,
TIM3_ETR, TIM1_CH1N | UCPD2_CC2 | | - | - | 25 | - | 29 | 41 | D5 | 53 | PD3 | I/O | FT_d | (4) | USART2_CTS, SPI2_MISO,
TIM1_CH2N | UCPD2_DBCC2 | | - | - | - | - | - | - | C5 | 54 | PD4 | I/O | FT | - | USART2_RTS_DE_CK,
SPI2_MOSI, TIM1_CH3N | - | | - | - | - | - | - | - | B5 | 55 | PD5 | I/O | FT | - | USART2_TX,
SPI1_MISO/I2S1_MCK,
TIM1_BKIN | - | | - | - | - | - | - | - | A5 | 56 | PD6 | I/O | FT | - | USART2_RX,
SPI1_MOSI/I2S1_SD,
LPTIM2_OUT | - | | - | 23 | - | 27 | - | 42 | B4 | 57 | PB3 | I/O | FT_a | - | SPI1_SCK/I2S1_CK,
TIM1_CH2, TIM2_CH2,
USART1_RTS_DE_CK,
EVENTOUT | COMP2_INM | | - | 24 | - | 28 | - | 43 | C4 | 58 | PB4 | I/O | FT_a | - | SPI1_MISO/I2S1_MCK,
TIM3_CH1, USART1_CTS,
TIM17_BKIN, EVENTOUT | COMP2_INP |

Table 12. Pin assignment and description (continued)

| | | | | Pin number | |---------|---------------|--------------|------------------------|-----------------------|-------------------|---------|--------|--------------------------------------|----------|---------------|------|------------------------------------------------------------------------------------------|-------------------------| | WLCSP25 | UFQFPN28 - GP | UFQFPN28 - N | LQFP32 / UFQFPN32 - GP | LQFP32 / UFQFPN32 - N | LQFP48 / UFQFPN48 | UFBGA64 | LQFP64 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | A3 | 25 | - | 29 | - | 44 | D4 | 59 | PB5 | I/O | FT | - | SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM16_BKIN,
LPTIM1_IN1, I2C1_SMBA,
COMP2_OUT | WKUP6 | | B3 | 26 | 26 | 30 | 30 | 45 | A4 | 60 | PB6 | I/O | FT_fa | - | USART1_TX, TIM1_CH3,
TIM16_CH1N, SPI2_MISO,
LPTIM1_ETR, I2C1_SCL,
EVENTOUT | COMP2_INP | | A4 | 27 | 27 | 31 | 31 | 46 | A3 | 61 | PB7 | I/O | FT_fa | - | USART1_RX, SPI2_MOSI,
TIM17_CH1N,
USART4_CTS,
LPTIM1_IN2, I2C1_SDA,
EVENTOUT | COMP2_INM, PVD_IN | | B4 | 28 | 28 | 32 | 32 | 47 | B3 | 62 | PB8 | I/O | FT_f | - | CEC, SPI2_SCK,
TIM16_CH1, USART3_TX,
TIM15_BKIN, I2C1_SCL,
EVENTOUT | - | | - | - | - | 1 | 1 | 48 | C3 | 63 | PB9 | I/O | FT_f | - | IR_OUT, UCPD2_FRSTX,
TIM17_CH1, USART3_RX,
SPI2_NSS, I2C1_SDA,
EVENTOUT | - | | - | - | - | - | - | - | A2 | 64 | PC10 | I/O | FT | - | USART3_TX, USART4_TX,
TIM1_CH3 | - |

• 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
  • The speed should not exceed 2 MHz with a maximum load of 30 pF
  • These GPIOs must not be used as current sources (for example to drive a LED).
• 2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
• 1. RST I/O structure when the PF2-NRST pin is configured as reset (input or input/output mode), FT I/O structure when the PF2-NRST pin is configured as GPIO.
• 4. Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2, depending on the voltage level on PA9/PC6, PA10/PB0, PD1, and PD3, respectively. In order to disable this resistor, strobe the UCPDx_STROBE bit of the SYSCFG_CFGR1 register during start-up sequence.
• 5. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
• 6. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Table 13. Port A alternate function mapping

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
0 P A	S 2_ S C P I K	S 2_ C S U A R T T	2_ C 1_ T I M H E T R	-	S U A R T 4_ T X	1_ O L P T I M U T	C 2_ S U P D F R T X	C O 1_ O M P U T
P A 1	S / I P I 1_ S C K 2 S 1_ C K	U S A R T 2_ R T S D E_ C K _	T I M 2_ C H 2	-	U S A R T 4_ R X	T I M 1 5_ C H 1 N	I 2 C 1_ S M B A	E V E N T O U T
P A 2	S P / I I 1_ M O S I 2 S 1_ S D	U S A R T 2_ T X	T I M 2_ C H 3	-	U C P D 1_ F R S T X	T I M 1 C H 1 5_	L P U A R T 1_ T X	C O M P 2_ O U T
P A 3	S P I 2_ M I S O	U S A R T 2_ R X	T I M 2_ C H 4	-	U C P D 2_ F R S T X	T I M 1 5_ C H 2	L P U A R T 1_ R X	E V E N T O U T
P A 4	S / I P I 1_ N S S S S 2 1_ W	S P I 2_ M O S I	-	-	T I M 1 4_ C H 1	L P T I M 2_ O U T	U C P D 2_ F R S T X	E V E N T O U T
P A 5	S / I P I 1_ S C K 2 S 1_ C K	C E C	T I M 2_ C H 1_ E T R	-	U S A R T 3_ T X	L P T I M 2_ E T R	U C P D 1_ F R S T X	E V E N T O U T
6 P A	S / I P I 1_ M I S O 2 S 1_ M C K	3_ C 1 T I M H	1_ T I M B K I N	-	S 3_ C S U A R T T	1 6_ C 1 T I M H	1_ C S L P U A R T T	C O 1_ O M P U T
P A 7	S P / I I 1_ M O S I 2 S 1_ S D	T I M 3_ C H 2	T I M 1_ C H 1 N	-	T I M 1 4_ C H 1	T I M 1 7_ C H 1	U C P D 1_ F R S T X	C O M P 2_ O U T
P A 8	C O M	S S S P I 2_ N	C T I M 1_ H 1	-	-	O L P T I M 2_ U T	-	O E V E N T U T
P A 9	M C O	U S A R T 1_ T X	T I M 1_ C H 2	-	S P I 2_ M I S O	T I M 1 5_ B K I N	I 2 C 1_ S C L	E V E N T O U T
P A 1 0	S P I 2_ M O S I	U S A R T 1_ R X	T I M 1_ C H 3	-	-	T I M 1 7_ B K I N	I 2 C 1_ S D A	E V E N T O U T
P A 1 1	S / I P I 1_ M I S O S C 2 1_ M K	U S A R T 1_ C T S	T I M 1_ C H 4	-	-	T I M 1_ B K I N 2	I 2 C 2_ S C L	C O M P 1_ O U T
P A 1 2	S P / I I 1_ M O S I 2 S 1_ S D	U S A R T 1_ R T S D E_ C K _	T I M 1_ E T R	-	-	I 2 S_ C K I N	I 2 C 2_ S D A	C O M P 2_ O U T
P A 1 3	S W D I O	I R_ O U T	-	-	-	-	-	E V E N T O U T
P A 1 4	S C W L K	S U A R T 2_ T X	-	-	-	-	-	O E V E N T U T
P A 1 5	S / I P I 1_ N S S 2 S 1_ W S	U S A R T 2_ R X	T I M 2_ C H 1_ E T R	-	U S A R T 4_ R T S D E_ C K _	U S A R T 3_ R T S D E_ C K _	-	E V E N T O U T

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1 | A
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2 | A
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3 | A
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4 | A
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5 | A
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6 | A
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7 | | | P
B
0 | S
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2
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S | C
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3_
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3 | C
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2
N | - | S
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A
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3_
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1 | T
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N | - | U
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1 | - | - | S
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1_
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1
7_
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K
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5 | S
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T | | DS12232 Rev 5 | P
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7 | U
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1_
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D
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0
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C
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3
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3_
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A
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2_
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C
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2_
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1_
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2_
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4 | - | U
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A
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3_
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2
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2_
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2_
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B
1
2 | S
P
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S
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1_
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I
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1_
B
K
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1
5_
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C
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C
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P
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1
T
I
M
H
N | - | S
3_
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C
1
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5_
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C
2_
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C
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V
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T
U
T | | | P
B
1
4 | S
P
I
2_
M
I
S
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C
P
D
1_
F
R
S
T
X | T
I
M
1_
C
H
2
N | - | U
S
A
R
T
3_
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T
S
D
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K
_ | T
I
M
1
5_
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H
1 | I
2
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2_
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D
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V
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N
T
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U
T | | | P
B
1
5 | S
P
I
2_
M
O
S
I | - | T
I
M
1_
C
H
3
N | - | T
I
M
1
C
H
1
N
5_ | T
I
M
1
C
H
2
5_ | - | E
V
E
N
T
O
U
T | Table 15. Port C alternate function mapping

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
P C 0	L P T I M 1_ I N 1	L P U A R T 1_ R X	L P T I M 2_ I N 1	-	-	-	-	-
P C 1	L P T I M 1_ O U T	L P U A R T 1_ T X	T I M 1 5_ C H 1	-	-	-	-	-
P C 2	L P T I M 1_ I N 2	S P I 2_ M I S O	T I M 1 C H 2 5_	-	-	-	-	-
C P 3	L P T I M 1_ E T R	S O S P I 2_ M I	L P T I M 2_ E T R	-	-	-	-	-
P C 4	U S A R T 3_ T X	U S A R T 1_ T X	T I M 2_ C H 1_ E T R	-	-	-	-	-
P C 5	U S A R T 3_ R X	U S A R T 1_ R X	T I M 2_ C H 2	-	-	-	-	-
P C 6	U C P D 1_ F R S T X	T I M 3_ C H 1	T I M 2_ C H 3	-	-	-	-	-
P C 7	U C P D 2_ F R S T X	T I M 3_ C H 2	T I M 2_ C H 4	-	-	-	-	-
C P 8	C S U P D 2_ F R T X	C T I M 3_ H 3	C T I M 1_ H 1	-	-	-	-	-
P C 9	I 2 S_ C K I N	T I M 3_ C H 4	T I M 1_ C H 2	-	-	-	-	-
P C 1 0	U S A R T 3_ T X	U S A R T 4_ T X	T I M 1_ C H 3	-	-	-	-	-
P C 1 1	U S A R T 3_ R X	U S A R T 4_ R X	T I M 1_ C H 4	-	-	-	-	-
P C 1 2	L P T I M 1_ I N 1	U C P D 1_ F R S T X	T I M 1 4_ C H 1	-	-	-	-	-
C P 1 3	-	-	T I M 1_ B K I N	-	-	-	-	-
P C 1 4	-	-	T I M 1_ B K I N 2	-	-	-	-	-
P C 1 5	O S C 3 2_ E N	O S C_ E N	T I M 1 5_ B K I N	-	-	-	-	-

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g | |--------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------|-----------------------------------------------------------------------------|--------------------------------------------|-------------|-------------|-------------|-------------|-------------| | Po
t
r | A
F
0 | A
F
1 | A
F
2 | A
F
3 | A
F
4 | A
F
5 | A
F
6 | A
F
7 | | P
D
0 | E
V
E
N
T
O
U
T | S
P
I
2_
N
S
S | T
I
M
1
6_
C
H
1 | - | - | - | - | - | | 1
P
D | O
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V
E
N
T
U
T | S
2_
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C
P
I
K | 1
C
1
T
I
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7_
H | - | - | - | - | - | | P
D
2 | U
S
A
R
T
3_
R
T
S
D
E_
C
K
_ | T
I
M
3_
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T
R | T
I
M
1_
C
H
1
N | - | - | - | - | - | | P
D
3 | U
S
A
R
T
2_
C
T
S | S
P
I
2_
M
I
S
O | T
I
M
1_
C
H
2
N | - | - | - | - | - | | P
D
4 | S
2_
S
U
A
R
T
R
T
D
E_
C
K
_ | S
O
S
P
I
2_
M
I | C
T
I
M
1_
H
3
N | - | - | - | - | - | | P
D
5 | U
S
A
R
T
2_
T
X | S
/ I
P
I
1_
M
I
S
O
S
C
2
1_
M
K | T
I
M
1_
B
K
I
N | - | - | - | - | - | | P
D
6 | U
S
A
R
T
2_
R
X | S
P
/ I
I
1_
M
O
S
I
2
S
1_
S
D | L
P
T
I
M
2_
O
U
T | - | - | - | - | - | | 8
P
D | S
3_
U
A
R
T
T
X | S
/ I
P
I
1_
S
C
K
2
S
1_
C
K | 1_
O
L
P
T
I
M
U
T | - | - | - | - | - | | P
D
9 | U
S
A
R
T
3_
R
X | S
/ I
P
I
1_
N
S
S
2
S
1_
W
S | T
I
M
1_
B
K
I
N
2 | - | - | - | - | - |

Table 17. Port F alternate function mapping

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
0 P F	-	-	1 C 1 T I M 4_ H	-	-	-	-	-
P F 1	O S C_ E N	-	T I M 1 5_ C H 1 N	-	-	-	-	-
P F 2	M C O	-	-	-	-	-	-	-

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

5.1.6 Power supply scheme

Figure 13. Power supply scheme

• 1. Internally connected to VDDA on devices without VREF+ pin.
• 1. Only required when VREFBUF is used.

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

5.1.7 Current consumption measurement

Figure 14. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to VSS.

Table 18. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD	External supply voltage	-0.3	4.0	V
VBAT	External supply voltage on VBAT pin	-0.3	4.0	V
VREF+	External voltage on VREF+ pin	-0.3	Min(VDD + 0.4, 4.0)	V
	Input voltage on FT_xx pins except FT_c	-0.3	VDD + 4.0(2)(3)
VIN(1)	Input voltage on FT_c pins	-0.3	5.5	V
	Input voltage on any other pin	-0.3	4.0

• 1. Refer to Table 19 for the maximum allowed injected current values.
• 1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
• 1. When an FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.

Table 19. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)(1)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)(2)	100	mA
	Output current sunk by any I/O and control pin except FT_f	15
IIO(PIN)	Output current sunk by any FT_f pin	20	mA
	Output current sourced by any I/O and control pin	15
Symbol	Ratings	Max	Unit
--------------	------------------------------------------------------------------	------------	------
	Total output current sunk by sum of all I/Os and control pins	80
∑IIO(PIN)	Total output current sourced by sum of all I/Os and control pins	80	mA
IINJ(PIN)(2)	Injected current on a FT_xx pin	-5 / NA(3)
	Injected current on a TT_a pin(4)	-5 / 0	mA
∑ IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	25	mA
Table 19. Current characteristics (continued)

• 1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.
• 2. A positive injection is induced by VIN > VDDIO1 while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
• 1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
• 1. On these I/Os, any current injection disturbs the analog performances of the device.
• 1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

| Symbol | Ratings | Value | Unit | |--------|------------------------------|-------------|------|--|--|--|--|--|--|--| | TSTG | Storage temperature range | -65 to +150 | °C | | TJ | Maximum junction temperature | 150 | °C | Table 20. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 21. General operating conditions

| Symbol | Parameter | Conditions | Min | Max | Unit | |--------|------------------------------|-------------------------------|--------|------------------------|------|--| | fHCLK | Internal AHB clock frequency | - | 0 | 64 | | fPCLK | Internal APB clock frequency | - | 0 | 64 | MHz | | VDD | Standard operating voltage | - | 1.7(1) | 3.6 | V | | | | For ADC and COMP
operation | 1.62 | 3.6 | | VDDA | Analog supply voltage | For DAC operation | 1.8 | 3.6 | V | | | | For VREFBUF operation | 2.4 | 3.6 | | VBAT | Backup operating voltage | - | 1.55 | 3.6 | V | | | | All except: RST, TT_xx, FT_c | -0.3 | Min(VDD + 3.6, 5.5)(2) | | | | RST | -0.3 | VDD + 0.3 | | VIN | I/O input voltage | TT_xx | -0.3 | VDDA + 0.3 | V | | | | FT_c | -0.3 | 5.0(2) |

Symbol	Parameter	Conditions	Min	Max	Unit
TA		Suffix 6(4)	-40	85
	Ambient temperature(3)	(4) Suffix 7	-40	105	°C
		Suffix 3(4)	-40	125
		Suffix 6(4)	-40	105
TJ	Junction temperature	(4) Suffix 7	-40	125	°C
		Suffix 3(4)	-40	130
Table 21. General operating conditions (continued)

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21.

Table 22. Operating conditions at power-up / power-down

Symbol	Parameter	Conditions	Min	Max	Unit
		VDD rising	-	∞	µs/V
tVDD	VDD slew rate	VDD falling; ULPEN = 0	10	∞
		VDD falling; ULPEN = 1	100	∞	ms/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21: General operating conditions.

Table 23. Embedded reset and power control block characteristics

Symbol	Parameter	Conditions(1)	Min	Typ	Max	Unit
tRSTTEMPO(2)	POR temporization when VDD crosses VPOR	VDD rising	-	250	400	μs
VPOR(2)	Power-on reset threshold	-	1.62	1.66	1.70	V
VPDR(2)	Power-down reset threshold	-	1.60	1.64	1.69	V
	Brownout reset threshold 1	VDD rising	2.05	2.10	2.18	V
VBOR1		VDD falling	1.95	2.00	2.08
	Brownout reset threshold 2	VDD rising	2.20	2.31	2.38	V
VBOR2		VDD falling	2.10	2.21	2.28
		VDD rising	2.50	2.62	2.68
VBOR3	Brownout reset threshold 3	VDD falling	2.40	2.52	2.58	V

^1. When RESET is released functionality is guaranteed down to VPDR min.

^2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.

^3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.10: Thermal characteristics.

^4. Temperature range digit in the order code. See Section 7: Ordering information.

Table 23. Embedded reset and power control block characteristics (continued)

Symbol	Parameter	Conditions(1)	Min	Typ	Max	Unit
		VDD rising	2.80	2.91	3.00
VBOR4	Brownout reset threshold 4	VDD falling	2.70	2.81	2.90	V
	Programmable voltage detector threshold 0	VDD rising	2.05	2.15	2.22	V
VPVD0		VDD falling	1.95	2.05	2.12
	PVD threshold 1	VDD rising	2.20	2.30	2.37	V
VPVD1		VDD falling	2.10	2.20	2.27
	PVD threshold 2	VDD rising	2.35	2.46	2.54
VPVD2		VDD falling	2.25	2.36	2.44	V
		VDD rising	2.50	2.62	2.70
VPVD3	PVD threshold 3	VDD falling	2.40	2.52	2.60	V
	PVD threshold 4	VDD rising	2.65	2.74	2.87	V
VPVD4		VDD falling	2.55	2.64	2.77
	PVD threshold 5	VDD rising	2.80	2.91	3.03
VPVD5		VDD falling	2.70	2.81	2.93	V
	PVD threshold 6	VDD rising	2.90	3.01	3.14
VPVD6		VDD falling	2.80	2.91	3.04	V
Vhyst_POR_PDR	Hysteresis of VPOR and VPDR	Hysteresis in continuous mode	-	20	-	mV
		Hysteresis in other mode	-	30	-
Vhyst_BOR_PVD	Hysteresis of VBORx and VPVDx	-	-	100	-	mV
IDD(BOR_PVD)(2)	BOR and PVD consumption	-	-	1.1	1.6	µA

^1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

5.3.4 Embedded voltage reference

The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Table 24. Embedded internal voltage reference

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltage	-40°C < TJ < 130°C	1.182	1.212	1.232	V
(1) tS_vrefint	ADC sampling time when reading the internal reference voltage	-	4(2)	-	-	µs
tstart_vrefint	Start time of reference voltage buffer when ADC is enable	-	-	8	12(2)	µs

^2. Specified by design. Not tested in production.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
IDD(VREFINTBUF)	VREFINT buffer consumption from VDD when converted by ADC	-	-	12.5	20(2)	µA
∆VREFINT	Internal reference voltage spread over the temperature range	VDD = 3 V	-	5	7.5(2)	mV
TCoeff_vrefint	Temperature coefficient	-	-	30	50(2)	ppm/°C
ACoeff	Long term stability	1000 hours, T = 25 °C	-	300	1000(2)	ppm
VDDCoeff	Voltage coefficient	3.0 V < VDD < 3.6 V	-	250	1200(2)	ppm/V
VREFINT_DIV1	1/4 reference voltage		24	25	26
VREFINT_DIV2	1/2 reference voltage	-	49	50	51	% VREFINT
VREFINT_DIV3	3/4 reference voltage		74	75	76
Table 24. Embedded internal voltage reference (continued)

^2. Specified by design. Not tested in production.

Figure 15. VREFINT vs. temperature

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 14: Current consumption measurement scheme.

^1. The shortest sampling time can be determined in the application by multiple iterations.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number, depending on the f_HCLK frequency (refer to the table "Number of wait states according to CPU clock (HCLK) frequency" available in the RM0444 reference manual).
• When the peripherals are enabled f_PCLK = f_HCLK
• For flash memory and shared peripherals f_PCLK = f_HCLK = f_HCLKS

Unless otherwise stated, values given in Table 25 through Table 33 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Table 25. Current consumption in Run and Low-power run modes at different die temperatures

| | | Cond | litions | | | Typ | | | Max ⁽¹⁾ | ) | |----------------------|------------|-------------------------------------------------------------|-------------------|------------------------------|----------|----------|-----------|----------|--------------------|-----------|------| | Symbol | Parameter | General | f _HCLK | Fetch
from ⁽²⁾ | 25
°C | 85
°C | 125
°C | 25
°C | 85
°C | 130
°C | Unit | | | | | 64 MHz | | 6.3 | 6.4 | 6.8 | 6.7 | 7.0 | 7.7 | | | | | 56 MHz | | 5.5 | 5.7 | 5.9 | 5.9 | 6.3 | 6.8 | | | | | 48 MHz | Flash | 5.0 | 5.1 | 5.4 | 5.2 | 5.7 | 6.3 | | | | Dance 4: | 32 MHz | memory | 3.5 | 3.6 | 3.8 | 4.0 | 4.3 | 4.7 | | | | Range 1;
PLL enabled; | 24 MHz | | 2.8 | 2.9 | 3.1 | 3.1 | 3.6 | 4.0 | | | | f _HCLK = f _{HSE_bypass} | 16 MHz | | 1.8 | 1.9 | 2.1 | 2.1 | 2.5 | 3.0 | | | | (≤16 MHz),
f _HCLK = f _PLLRCLK | 64 MHz | | 6.0 | 6.2 | 6.4 | 6.3 | 6.6 | 7.0 | | | | THCLK = TPLLRCLK
(>16 MHz);
(3) | 56 MHz | MHz | 5.3 | 5.5 | 5.7 | 5.6 | 5.8 | 6.2 | | | Supply | | 48 MHz
32 MHz | 4.7 | 4.8 | 5.0 | 5.0 | 5.2 | 5.6 | | I _DD(Run) | current in | | | 3.3 | 3.4 | 3.5 | 3.5 | 3.8 | 4.1 | mA | | | Run mode | | 24 MHz | MHz | 2.6 | 2.7 | 2.9 | 2.8 | 3.1 | 3.4 | | | | | 16 MHz | | 1.7 | 1.7 | 1.9 | 1.9 | 2.1 | 2.7 | | | | | 16 MHz | | 1.4 | 1.5 | 1.7 | 1.7 | 2.0 | 2.6 | | | | Range 2; | 8 MHz | Flash
memory | 0.8 | 0.9 | 1.0 | 1.2 | 1.3 | 1.8 | | | | PLL enabled; | 2 MHz | | 0.3 | 0.3 | 0.5 | 0.5 | 0.8 | 1.4 | | | | fHCLK = fHSE_bypass (≤16 MHz), fHCLK = fPLLRCLK (>16 MHz); | 16 MHz | | 1.4 | 1.4 | 1.6 | 1.6 | 1.8 | 2.2 | | | | | 8 MHz | SDAM | 0.7 | 0.8 | 1.0 | 1.1 | 1.2 | 1.6 | | | | | SRAM - | 0.4 | 0.5 | 0.6 | 0.7 | 0.9 | 1.5 | | | | | 2 MHz | | 0.3 | 0.3 | 0.5 | 0.5 | 0.8 | 1.2 | Table 25. Current consumption in Run and Low-power run modes at different die temperatures (continued)

| | | at amerent | ч. c c cp | | (00:::: | | / | |------------------------|----------------------|------------------------------------------------------------|-------------------|------------------------------|----------|----------|-----------|----------|--------------------|-----------|------| | | | Cond | litions | | | Typ | | | Max ⁽¹⁾ | ) | | Symbol | Parameter | General | f _HCLK | Fetch
from ⁽²⁾ | 25
°C | 85
°C | 125
°C | 25
°C | 85
°C | 130
°C | Unit | | | | | 2 MHz | | 220 | 255 | 420 | 530 | 795 | 1255 | | | | | 1 MHz | | 105 | 155 | 320 | 505 | 770 | 1200 | | | | | 500 kHz | Flash
memory | 67 | 105 | 265 | 465 | 700 | 1110 | | | Cumply | PLL disabled; | 125 kHz | | 26 | 66 | 230 | 450 | 520 | 1045 | | | Supply
current in | f _HCLK = f _HSE
bypass (> 32 kHz), | , 32 kHz | 17 | 56 | 220 | 375 | 475 | 1035 | | I _DD(LPRun) | Low-power run mode | f _HCLK = f _LSE | 2 MHz | 199 | 231 | 380 | 485 | 700 | 1220 | μA | | | Tull Illoue | bypass (= 32 kHz); (3) | 1 MHz | | 95 | 140 | 290 | 430 | 660 | 1140 | | | | | 500 kHz | SRAM | 61 | 95 | 240 | 365 | 625 | 1100 | | | | | 125 kHz | | 24 | 59 | 225 | 335 | 440 | 970 | | | | | 32 kHz | | 15 | 55 | 220 | 325 | 355 | 940 | ^1. Based on characterization results, not tested in production.

^2. Prefetch and cache enabled when fetching from flash memory. Code compiled with high optimization for space in SRAM.

^3. $V_{DD}$ = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

Table 26. Typical current consumption in Run and Low-power run modes, depending on code executed

| | | | onditions | | Typ | | Typ | |------------------------|--------------------|-------------------------------------------------------------------------------|-----------------------------|------------------------------|------------|--------|-------|------------|-----|--| | Symbol | Parameter | General | Code | Fetch
from ⁽¹⁾ | 25 °C | Unit | 25 °C | Unit | | | | | Reduced code ⁽³⁾ | | 6.4 | | 100 | | | | | Coremark | ] | 6.2 | | 97 | | | | | Dhrystone 2.1 | Flash
memory | 5.9 | | 92 | | | | Range 1; | Fibonacci | | 4.6 | | 71 | | | | f _HCLK = f _PLLRCLK = | While(1) loop | | 4.6 | | 71 | | | | 64 MHz;
(2) | Reduced code ⁽³⁾ | | 6.2 | | 96 | | | | | Coremark | | 6.2 | | 97 | | | | | Dhrystone 2.1 | SRAM | 6.0 | | 93 | | | | | | | 6.2 | | 96 | | l | Supply current in | | While(1) loop | | 4.8 | mA | 75 | μΑ/MHz | | I _DD(Run) | Run mode | | Reduced code ⁽³⁾ | | 1.5 | ШA | 94 | μΑνίνιι ιΖ | | | | | Coremark | ] | 1.5 | | 94 | | | | | Dhrystone 2.1 Flash memory | | memory 1.5 | | 91 | | | | Range 2; | Fibonacci | ] | 1.1 | | 69 | | | | f _HCLK = f _HSl16 =
16 MHz, | While(1) loop | | 1.1 | | 69 | | | | PLL disabled, | Reduced code ⁽³⁾ | | 1.5 | | 91 | | | | (2) | Coremark | | 1.4 | | 88 | | | | | Dhrystone 2.1 | SRAM | 1.4 | | 84 | | | | | Fibonacci | | 1.5 | | 91 | | | | | While(1) loop | | 1.1 | | 69 | | | | | Reduced code ⁽³⁾ | | 380 | | 190 | | | | | Coremark | ] | 395 | | 198 | | | | | Dhrystone 2.1 | Flash
memory | 405 | | 203 | | | Supply | f -f /0- | Fibonacci | memory | memory | memory | 385 | | 193 | | l | current in | f _HCLK = f _HSI16 /8 =
2 MHz;
PLL disabled,
(2) | While(1) loop | | 400 | uA | 200 | uA/MHz | | I _DD(LPRun) | Low-power run mode | | Reduced code ⁽³⁾ | | 250 | uA | 125 | uA/WII IZ | | | Tarrinode | | Coremark 245 | 245 | 245 | | | 123 | | | | | Dhrystone 2.1 | | | | 120 | | | | | Fibonacci | | | 125 | | | | | While(1) loop | | 230 | | 115 | ^1. Prefetch and cache enabled when fetching from flash memory. Code compiled with high optimization for space in SRAM.

LY/

^2. $V_{DD} = 3.3 \text{ V}$ , all peripherals disabled, cache enabled, prefetch disabled for execution in flash memory and enabled in SRAM

3. Reduced code used for characterization results provided in Table 25.

Table 27. Current consumption in Sleep and Low-power sleep modes

| | | Conditions | | | | Typ | | | Max(1) | |--------------|-------------------------|------------------------------------------------------------------------------------------|--------------------------|---------|----------|----------|-----------|----------|----------|-----------|------|-----|----| | Symbol | Parameter | General | Voltage
scaling | fHCLK | 25
°C | 85
°C | 125
°C | 25
°C | 85
°C | 130
°C | Unit | | | | | | 64 MHz | 1.8 | 1.9 | 2.1 | 1.8 | 2.1 | 2.9 | | | | | | 56 MHz | 1.6 | 1.7 | 1.9 | 1.7 | 1.9 | 2.8 | | | | Flash memory enabled;
fHCLK = fHSE bypass | | 48 MHz | 1.4 | 1.5 | 1.7 | 1.6 | 1.7 | 2.7 | | | Supply | (≤16 MHz; PLL | Range 1 | 32 MHz | 1.0 | 1.1 | 1.3 | 1.2 | 1.3 | 2.3 | | IDD(Sleep) | current in
Sleep | disabled),
fHCLK = fPLLRCLK
(>16 MHz; PLL
enabled);
All peripherals disabled | | | | 24 MHz | 0.8 | 0.9 | 1.1 | 1.0 | 1.1 | 1.9 | mA | | | mode | | | 16 MHz | 0.5 | 0.6 | 0.8 | 0.6 | 0.7 | 1.7 | | | | | | 16 MHz | 0.4 | 0.5 | 0.7 | 0.5 | 0.6 | 1.4 | | | | | Range 2 | 8 MHz | 0.3 | 0.3 | 0.5 | 0.3 | 0.5 | 1.2 | | | | | | 2 MHz | 0.1 | 0.2 | 0.4 | 0.2 | 0.4 | 1.1 | | | | | | 2 MHz | 60 | 99 | 265 | 150 | 360 | 1110 | | | Supply | Flash memory disabled;
PLL disabled; | | 1 MHz | 33 | 75 | 240 | 130 | 330 | 1010 | | IDD(LPSleep) | current in
Low-power | fHCLK = fHSE bypass (> 32 kHz),
fHCLK = fLSE bypass (= 32 kHz); | | 500 kHz | 25 | 64 | 230 | 125 | 250 | 870 | µA | | | sleep mode | | All peripherals disabled | | | 125 kHz | 16 | 55 | 220 | 110 | 235 | 715 | | | | | | 32 kHz | 14 | 53 | 215 | 110 | 225 | 645 | ^1. Based on characterization results, not tested in production.

Table 28. Current consumption in Stop 0 mode

| Symbol | Parameter | | Conditions | | Typ | | | Max(1) | | Unit | |-------------|----------------------|------------|------------|------|------|-------|------|--------|-------|------|-----|-----|--| | | | HSI kernel | VDD | 25°C | 85°C | 125°C | 25°C | 85°C | 130°C | | | | | 1.8 V | 275 | 305 | 430 | 330 | 425 | 750 | | | | | 2.4 V | 280 | 310 | 435 | 330 | 450 | 850 | | | | Enabled | 3 V | 280 | 315 | 435 | 350 | 490 | 950 | | | Supply
current in | | 3.6 V | 285 | 315 | 440 | 375 | 500 | 1020 | | IDD(Stop 0) | Stop 0 | | 1.8 V | 95 | 140 | 270 | 120 | 180 | 490 | µA | | | mode | | | | | 2.4 V | 100 | 145 | 275 | 125 | 220 | 610 | | | | Disabled | 3 V | 100 | 145 | 280 | 125 | 240 | 720 | | | | | 3.6 V | 105 | 150 | 285 | 130 | 250 | 840 | ^1. Based on characterization results, not tested in production.

Table 29. Current consumption in Stop 1 mode

| | | | Conditions | | | Typ | | | Max(1) | |-------------|----------------------|-----------------|------------|-------|------|------|-------|------|--------|-------|------|--|---------|-----|-----|----|-----|----|-----|-----|----| | Symbol | Parameter | Flash
memory | RTC(2) | VDD | 25°C | 85°C | 125°C | 25°C | 85°C | 130°C | Unit | | | | | | 1.8 V | 3.2 | 32 | 150 | 8 | 100 | 480 | | | | | | 2.4 V | 3.3 | 32 | 150 | 10 | 120 | 535 | | | | | Disabled | 3 V | 3.4 | 33 | 155 | 15 | 135 | 620 | | | | Not | | 3.6 V | 3.8 | 33 | 155 | 18 | 140 | 705 | | | | powered | | 1.8 V | 3.4 | 32 | 150 | 9 | 100 | 480 | | | Supply
current in | | | 2.4 V | 3.7 | 32 | 155 | 11 | 120 | 540 | | IDD(Stop 1) | Stop 1
mode | | | | | | | | | | | | Enabled | 3 V | 4.0 | 33 | 155 | 16 | 140 | 630 | µA | | | | | | 3.6 V | 4.4 | 34 | 160 | 20 | 145 | 720 | | | | | | 1.8 V | 6.9 | 36 | 155 | 12 | 100 | 575 | | | | | | 2.4 V | 7.3 | 36 | 160 | 14 | 110 | 600 | | | | Powered | Disabled | 3 V | 7.3 | 37 | 160 | 18 | 120 | 645 | | | | | | 3.6 V | 7.8 | 38 | 160 | 23 | 135 | 665 | ^1. Based on characterization results, not tested in production.

Table 30. Current consumption in Standby mode

| Symbol | Parameter | Conditions | | | Typ | | | Max(1) | | Unit | |--------------|------------------------------|-----------------|-------|------|-------|-------|------|--------|-------|------|-----|-----|-----|----|----|--| | | | General | VDD | 25°C | 85°C | 125°C | 25°C | 85°C | 130°C | | | | | 1.8 V | 0.07 | 1.7 | 6.7 | 0.7 | 9 | 34 | | | | RTC disabled | 2.4 V | 0.13 | 2.1 | 8.1 | 0.8 | 12 | 38 | | | | | 3.0 V | 0.20 | 2.5 | 10.0 | 0.9 | 14 | 46 | | | | | 3.6 V | 0.34 | 3.0 | 12.0 | 1.0 | 16 | 55 | | | | | 1.8 V | 0.35 | 2.0 | 7.0 | 0.8 | 10 | 35 | | | | RTC enabled, | | | | | | | 2.4 V | 0.49 | 2.4 | 8.4 | 1.0 | 12 | 40 | | | | clocked by LSI; | 3.0 V | 0.66 | 2.9 | 10.5 | 1.3 | 15 | 47 | | | Supply current
in Standby | | | | 3.6 V | 0.90 | 3.5 | 12.5 | 2.2 | 18 | 56 | µA | | IDD(Standby) | mode(2) | | 1.8 V | 0.26 | 1.9 | 6.8 | 0.8 | 10 | 34 | | | | IWDG enabled, | 2.4 V | 0.37 | 2.3 | 8.3 | 1.0 | 12 | 39 | | | | clocked by LSI | 3.0 V | 0.49 | 2.7 | 10.3 | 1.4 | 15 | 45 | | | | | 3.6 V | 0.69 | 3.3 | 12.3 | 2.1 | 18 | 52 | | | | | 1.8 V | 0.70 | 1.6 | 6.6 | - | - | - | | | | | 2.4 V | 0.89 | 2.0 | 8.0 | - | - | - | | | ENB_ULP = 0 | 3.0 V | 1.10 | 2.4 | 9.8 | - | - | - | | | | | 3.6 V | 1.30 | 2.9 | 11.8 | - | - | - | ^2. Clocked by LSI

Symbol	Parameter	Conditions			Typ			Max(1)		Unit
		General	VDD	25°C	85°C	125°C	25°C	85°C	130°C
	Extra supply		1.8 V	0.49	3.0	14.8	0.6	16	58
	current to	SRAM retention	2.4 V	0.57	3.1	14.9	1.1	17	63	µA
∆IDD(SRAM)	retain SRAM	enabled	3.0 V	0.67	3.2	15.0	1.5	17	67
	content(3)		3.6 V	0.77	3.3	15.0	1.9	18	71
Table 30. Current consumption in Standby mode (continued)

• 1. Based on characterization results, not tested in production.
• 1. Without SRAM retention and with ULPEN bit set
• 1. To be added to IDD(Standby) as appropriate

Table 31. Current consumption in Shutdown mode

| Symbol | Parameter | Conditions | | | Typ | | | Max(1) | | Unit | |---------------|-------------------------------|--------------------------------------|-------|-------|-------|--------|-------|--------|--------|-------|----| | | | RTC | VDD | 25 °C | 85 °C | 125 °C | 25 °C | 85 °C | 130 °C | | | | | 1.8 V | 17 | 515 | 4500 | 250 | 3000 | 32600 | | | | | 2.4 V | 23 | 600 | 5150 | 450 | 3500 | 33600 | | | | Disabled | 3.0 V | 33 | 730 | 6450 | 1075 | 4250 | 37400 | | | Supply current
in Shutdown | | | 3.6 V | 53 | 940 | 7700 | 1250 | 5300 | 43600 | nA | | IDD(Shutdown) | mode | | 1.8 V | 205 | 710 | 4700 | 900 | 4500 | 27300 | | | | Enabled, clocked
by LSE bypass at | 2.4 V | 300 | 890 | 5500 | 1550 | 5500 | 34800 | | | | 32.768 kHz | 3.0 V | 420 | 1150 | 6800 | 2475 | 6000 | 40900 | | | | | 3.6 V | 565 | 1450 | 8100 | 3250 | 7000 | 48500 | ^1. Based on characterization results, not tested in production.

Table 32. Current consumption in VBAT mode

| | | Conditions | | | Typ | |-----------|-------------------|---------------------------------------|-------|------|------|-------|------| | Symbol | Parameter | RTC | VDD | 25°C | 85°C | 125°C | Unit | | | | | 1.8 V | 165 | 170 | 620 | | | | Enabled, clocked by | 2.4 V | 260 | 355 | 970 | | | | LSE bypass at
32.768 kHz | 3.0 V | 365 | 475 | 1200 | | | | | 3.6 V | 505 | 655 | 2070 | | | | | 1.8 V | 290 | 390 | 960 | | | Supply current in | Enabled, clocked by
LSE crystal at | 2.4 V | 370 | 480 | 1150 | nA | | IDD(VBAT) | VBAT mode | 32.768 kHz | 3.0 V | 470 | 600 | 1650 | | | | | 3.6 V | 600 | 815 | 2250 | | | | | 1.8 V | 1 | 80 | 660 | | | | Disabled | 2.4 V | 2 | 90 | 750 | | | | | 3.0 V | 2 | 105 | 1200 | | | | | 3.6 V | 6 | 200 | 1700 |

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used with internal or external pull-up or pull-down resistor generate current consumption when the pin is externally or internally tied low or high, respectively. The value of this current consumption can be simply computed by using the pull-up/pull-down resistor values. For internal pull-up/pull-down resistors, the indicative values are given in Table 51: I/O static characteristics. Any other external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see Table 33: Current consumption of peripherals), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal and external) connected to the pin:

$$I_{SW} = V_{DDIO1} \times f_{SW} \times C$$

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

VDDIO1 is the I/O supply voltage

fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
  • when the peripheral is clocked on
  • when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 18: Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Table 33. Current consumption of peripherals

| | | | Consumption in µA/MHz | |----------------------|--------|---------|-----------------------|----------------------------| | Peripheral | Bus | Range 1 | Range 2 | Low-power run
and sleep | | IOPORT Bus | IOPORT | 1.0 | 0.7 | 0.5 | | GPIOA | IOPORT | 3.4 | 2.8 | 3.0 | | GPIOB | IOPORT | 3.1 | 2.6 | 2.5 | | GPIOC | IOPORT | 2.9 | 2.5 | 3.0 | | GPIOD | IOPORT | 1.8 | 1.5 | 1.5 | | GPIOF | IOPORT | 0.7 | 0.6 | 1.0 | | Bus matrix | AHB | 3.2 | 2.2 | 2.8 | | All AHB Peripherals | AHB | 15.0 | 12.5 | 14.0 | | DMA1/DMAMUX | AHB | 4.7 | 3.8 | 4.5 | | CRC | AHB | 0.5 | 0.4 | 0.5 | | FLASH | AHB | 4.1 | 3.5 | 4.0 | | All APB peripherals | APB | 46.5 | 47.5 | 48.0 | | AHB to APB bridge(1) | APB | 0.2 | 0.2 | 0.1 | | PWR | APB | 0.4 | 0.3 | 0.5 | | SYSCFG/VREFBUF/COMP | APB | 0.4 | 0.4 | 0.3 | | WWDG | APB | 0.4 | 0.3 | 0.5 | | TIM1 | APB | 7.3 | 6.1 | 6.5 | | TIM2 | APB | 4.7 | 3.8 | 5.0 | | TIM3 | APB | 3.6 | 3.0 | 2.5 | | TIM6 | APB | 0.7 | 0.6 | 0.5 | | TIM7 | APB | 0.7 | 0.7 | 1.0 | | TIM14 | APB | 1.5 | 1.2 | 1.5 | | TIM15 | APB | 4.0 | 3.3 | 3.0 | | TIM16 | APB | 2.3 | 2.0 | 2.0 |

Table 33. Current consumption of peripherals (continued)

| | | | Consumption in µA/MHz | |------------|-----|---------|-----------------------|----------------------------| | Peripheral | Bus | Range 1 | Range 2 | Low-power run
and sleep | | TIM17 | APB | 0.7 | 0.7 | 0.5 | | LPTIM1 | APB | 3.2 | 2.7 | 3.0 | | LPTIM2 | APB | 3.1 | 2.5 | 3.0 | | I2C1 | APB | 3.8 | 3.1 | 3.5 | | I2C2 | APB | 0.7 | 0.6 | 1.0 | | SPI2 | APB | 1.5 | 1.2 | 1.0 | | USART1 | APB | 7.2 | 6.0 | 6.5 | | USART2 | APB | 7.2 | 6.0 | 6.0 | | USART3 | APB | 2.0 | 1.7 | 2.0 | | USART4 | APB | 2.0 | 1.7 | 2.0 | | LPUART1 | APB | 4.3 | 3.5 | 4.0 | | CEC | APB | 0.4 | 0.3 | 0.5 | | UCPD1 | APB | 4.0 | 7.7 | NA(2) | | UCPD2 | APB | 4.0 | 7.7 | NA(2) | | ADC | APB | 2.0 | 1.7 | 2.0 | | DAC | APB | 2.2 | 1.8 | 2.0 |

^1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.

5.3.6 Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in Table 34 are the latency between the event and the execution of the first user instruction.

Table 34. Low-power mode wakeup times(1)

Symbol	Parameter	Conditions	Typ	Max	Unit
tWUSLEEP	Wakeup time from Sleep to Run mode	-	11	11	CPU cycles
tWULPSLEEP	Wakeup time from Low-power sleep mode	Transiting to Low-power-run-mode execution in flash memory not powered in Low-power sleep mode; HCLK = HSI16 / 8 = 2 MHz	11	14	CPU cycles

^2. UCPDx are always clocked by HSI16.

Table 34. Low-power mode wakeup times(1) (continued)

Symbol	Parameter	Conditions	Typ	Max	Unit
	Wakeup time from	Transiting to Run-mode execution in flash memory not powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2	5.6	6
tWUSTOP0	Stop 0	Transiting to Run-mode execution in SRAM or in flash memory powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2	2	2.4	µs
	Transiting to Run-mode execution in flash memory not powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2		9.0	11.2
	Wakeup time from Stop 1	Transiting to Run-mode execution in SRAM or in flash memory powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2	5	7.5	µs
tWUSTOP1		Transiting to Low-power-run-mode execution in flash memory not powered in Stop 1 mode; HCLK = HSI16/8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1)	22	25.3
		Transiting to Low-power-run-mode execution in SRAM or in flash memory powered in Stop 1 mode; HCLK = HSI16 / 8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1)	18	23.5
tWUSTBY	Wakeup time from Standby mode	Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1	14.5	30	µs
tWUSHDN	Wakeup time from Shutdown mode	Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1	258	340	µs
tWULPRUN	Wakeup time from Low-power run mode(2)	Transiting to Run mode; HSISYS = HSI16/8 = 2 MHz	5	7	µs

• 1. Based on characterization results, not tested in production.
• 1. Time until REGLPF flag is cleared in PWR_SR2.

Table 35. Regulator mode transition times(1)

Symbol	Parameter	Conditions	Typ	Max	Unit
tVOST	Transition times between regulator Range 1 and Range 2(2)	HSISYS = HSI16	20	40	µs

• 1. Based on characterization results, not tested in production.
• 1. Time until VOSF flag is cleared in PWR_SR2.

Table 36	Wakeun	time	usina	LPUART (1)
I abic oc.	TTUNCUP	unio	usilig

Symbol	Parameter	Conditions	Typ	Max	Unit
t	Wakeup time needed to calculate the maximum LPUART baud rate allowing to wakeup up from Stop	Stop mode 0	-	1.7	μs
l WULPUART	mode when LPUART clock source is HSI16	Stop mode 1	-	8.5	μδ

^1. Specified by design. Not tested in production.

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See Figure 16 for recommended clock input waveform.

Table 37. High-speed external user clock characteristics⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
f	User external clock source frequency	Voltage scaling Range 1	-	8	48	MHz
f HSE_ext	Oser external clock source frequency	Voltage scaling Range 2	-	8	26	IVII IZ
V HSEH	OSC_IN input pin high level voltage	-	0.7 V DDIO1	-	V DDIO1	V
$V_{HSEL}$	OSC_IN input pin low level voltage	-	V SS	-	0.3 V DDIO1	V
t w(HSEH)	OSC IN high or low time	Voltage scaling Range 1	7	-	-	ns
t w(HSEL)	OSC_IN HIGH OF IOW LITTLE	Voltage scaling Range 2	18	-	-	115

^1. Specified by design. Not tested in production.

Figure 16. High-speed external clock source AC timing diagram

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See Figure 17 for recommended clock input waveform.

Table 38. Low-speed external user clock characteristics⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
f LSE_ext	User external clock source frequency	-	-	32.768	1000	kHz
V LSEH	OSC32_IN input pin high level voltage	-	0.7 V DDIO1	-	V DDIO1	V
V LSEL	OSC32_IN input pin low level voltage	-	$V_{SS}$	-	0.3 V DDIO1	V
$t_{w(LSEH)}$ $t_{w(LSEL)}$	OSC32_IN high or low time	-	250	-	-	ns

^1. Specified by design. Not tested in production.

Figure 17. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 39. HSE oscillator characteristics⁽¹⁾

Symbol	Parameter	Conditions (2)	Min	Typ	Max	Unit
f OSC_IN	Oscillator frequency	-	4	8	48	MHz
$R_{F}$	Feedback resistor	-	-	200	-	kΩ

71/143

Table 39. HSE oscillator characteristics(1) (continued)

Symbol	Parameter	Conditions(2)	Min	Typ	Max	Unit
		During startup(3)	-	-	5.5
		VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz	-	0.44	-
		VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz	-	0.45	-
IDD(HSE)	HSE current consumption	VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz	-	0.68	-	mA
		VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz	-	0.94	-
		VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz	-	1.77	-
Gm	Maximum critical crystal transconductance	Startup	-	-	1.5	mA/V
tSU(HSE)(4)	Startup time	VDD is stabilized	-	2	-	ms

• 1. Specified by design. Not tested in production.
• 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
• 1. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
• 1. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

Figure 18. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Conditions(2)	Min	Typ	Max	Unit
		LSEDRV[1:0] = 00 Low drive capability	-	250	-
IDD(LSE)		LSEDRV[1:0] = 01 Medium low drive capability	-	315	-	nA
	LSE current consumption	LSEDRV[1:0] = 10 Medium high drive capability	-	500	-
		LSEDRV[1:0] = 11 High drive capability	-	630	-
		LSEDRV[1:0] = 00 Low drive capability	-	-	0.5
	Maximum critical crystal	LSEDRV[1:0] = 01 Medium low drive capability	-	-	0.75	µA/V
Gmcritmax	gm	LSEDRV[1:0] = 10 Medium high drive capability	-	-	1.7
		LSEDRV[1:0] = 11 High drive capability	-	-	2.7
tSU(LSE)(3)	Startup time	VDD is stabilized	-	2	-	s

Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

^2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers".

^1. Specified by design. Not tested in production.

1. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

Figure 19. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

5.3.8 Internal clock source characteristics

The parameters given in Table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 41. HSI16 oscillator characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI16	HSI16 Frequency	VDD=3.0 V, TA=30 °C	15.88	-	16.08	MHz
	HSI16 oscillator frequency drift over	TA= 0 to 85 °C	-1	-	1	%
	∆Temp(HSI16) temperature HSI16 oscillator frequency drift over VDD HSI16 frequency user trimming step	TA= -40 to 125 °C	-2	-	1.5	%
∆VDD(HSI16)		VDD=1.62 V to 3.6 V	-0.1	-	0.05	%
		From code 127 to 128	-8	-6	-4
TRIM		From code 63 to 64 From code 191 to 192	-5.8	-3.8	-1.8	%
		For all other code increments	0.2	0.3	0.4
DHSI16(2)	Duty Cycle	-	45	-	55	%
tsu(HSI16)(2)	HSI16 oscillator start-up time	-	-	0.8	1.2	μs

Table 41. HSI16 oscillator characteristics⁽¹⁾ (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t stab(HSI16) (2)	HSI16 oscillator stabilization time	-	-	3	5	μs
I DD(HSI16) (2)	HSI16 oscillator power consumption	-	-	155	190	μΑ

• 1. Based on characterization results, not tested in production.
• 2. Specified by design. Not tested in production.

Figure 20. HSI16 frequency vs. temperature

Low-speed internal (LSI) RC oscillator

Table 42. LSI oscillator characteristics⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
		V DD = 3.0 V, T A = 30 °C	31.04	-	32.96
f LSI	LSI frequency	V DD = 1.62 V to 3.6 V, T A = -40 to 125 °C	29.5	-	34	kHz
t SU(LSI) (2)	LSI oscillator start-up time	-	-	80	130	μs
t STAB(LSI) (2)	LSI oscillator stabilization time	5% of final frequency	-	125	180	μs
I DD(LSI) (2)	LSI oscillator power consumption	-	1	110	180	nA

• 1. Based on characterization results, not tested in production.
• 2. Specified by design. Not tested in production.

5.3.9 PLL characteristics

The parameters given in Table 43 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 21: General operating conditions.

Table 43. PLL characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fPLL_IN	PLL input clock frequency(2)	-	2.66	-	16	MHz
DPLL_IN	PLL input clock duty cycle	-	45	-	55	%
		Voltage scaling Range 1	3.09	-	122
fPLL_P_OUT	PLL multiplier output clock P	Voltage scaling Range 2	3.09	-	40	MHz
		Voltage scaling Range 1	12	-	128
fPLL_Q_OUT	PLL multiplier output clock Q	Voltage scaling Range 2	12	-	33 64	MHz
		Voltage scaling Range 1	12	-		MHz
fPLL_R_OUT	PLL multiplier output clock R	Voltage scaling Range 2	12	-	16
		Voltage scaling Range 1	96	-	344	MHz
fVCO_OUT	PLL VCO output	Voltage scaling Range 2	96	-	128
tLOCK	PLL lock time	-	-	15	40	μs
Jitter	RMS cycle-to-cycle jitter	System clock 56 MHz	-	50	-
	RMS period jitter		-	40	-	±ps
		VCO freq = 96 MHz	-	200	260
IDD(PLL)	PLL power consumption on VDD(1)	VCO freq = 192 MHz	-	300	380	μA
		VCO freq = 344 MHz	-	520	650
1. Specified by design. Not tested in production.

5.3.10 Flash memory characteristics

Table 44. Flash memory characteristics(1)

Symbol	Parameter Conditions		Typ	Max	Unit
tprog	64-bit programming time	-	85	125	µs
Row (32 double word) programming time		Normal programming	2.7	4.6	ms
tprog_row		Fast programming	1.7	2.8
		Normal programming	21.8	36.6
tprog_page	Page (2 Kbyte) programming time	Fast programming	13.7	22.4	ms
tERASE	Page (2 Kbyte) erase time	-	22.0	40.0	ms
	Bank (128 Kbyte(2)) programming time	Normal programming	1.4	2.4
tprog_bank		Fast programming	0.9	1.4	s
tME	Mass erase time	-	22.1	40.1	ms

^2. Make sure to use the appropriate division factor M to obtain the specified PLL input clock values.

Symbol	Parameter	Conditions	Typ	Max	Unit
I DD(FlashA)	Average consumption from V DD	Programming	3	-
		Page erase	3	-	mA
		Mass erase	3	-
I DD(FlashP)	Maximum current (peak)	Programming, 2 μs peak duration	7	-	mA
DD(Hashir)		Erase, 41 µs peak duration	7	-
Table 44. Flash memory characteristics(1) (continued)

^2. Values provided also apply to devices with less flash memory than one 128 Kbyte bank

| Table 43. I lash memory endurance and data retention | |------------------------------------------------------|---------------------------------------------------|------------------------------------------------------|--------------------|---------|--|--|--| | Symbol | Parameter | Conditions | Min ⁽¹⁾ | Unit | | N _END | Endurance | T _A = -40 to +105 °C | 10 | kcycles | | | 1 kcycle ⁽²⁾ at T _A = 85 °C | 30 | | | | 1 kcycle ⁽²⁾ at T _A = 105 °C | 15 | | | Data retention | 1 kcycle ⁽²⁾ at T _A = 125 °C | 7 | Vooro | | ^l RET | t _RET Data retention | 10 kcycles ⁽²⁾ at T _A = 55 °C | 30 | Years | | | | 10 kcycles ⁽²⁾ at T _A = 85 °C | 15 | | | | 10 kcycles ⁽²⁾ at T _A = 105 °C | 10 | Table 45. Flash memory endurance and data retention

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V_DD and V_SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 46. They are based on the EMS levels and classes defined in application note AN1709.

^1. Specified by design. Not tested in production.

^1. Evaluated by characterization. Not tested in production.

^2. Cycling performed over the whole temperature range.

Symbol	Parameter	Conditions	Level/ Class
VFESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	VDD = 3.3 V, TA = +25 °C, fHCLK = 64 MHz, LQFP64, conforming to IEC 61000-4-2	2B
VEFTB	Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a	VDD = 3.3 V, TA = +25 °C, fHCLK = 64 MHz, LQFP64,	5A

Table 46. EMS characteristics

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

conforming to IEC 61000-4-4

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• corrupted program counter
• unexpected reset

functional disturbance

• critical data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol	Parameter	Conditions	Monitored frequency band	Value	Unit
			0.1 MHz to 30 MHz	7
SEMI	Peak(1)	fHSE = 8 MHz fHCLK = 64 MHz	30 MHz to 130 MHz	-1
		VDD = 3.6 V, TA = 25 °C, 130 MHz to 1 GHz		8	dBµV
		LQFP64 package compliant with IEC 61967-2	1 GHz to 2 GHz	7
	Level(2)		0.1 MHz to 2 GHz	2.5	-

Table 47. EMI characteristics

^1. Refer to AN1709 "EMI radiated test" section.

V_ESD(CDM)

1. Refer to AN1709 "EMI level classification" section

5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Maximum Symbol Ratings Conditions Class Unit value⁽¹⁾ Electrostatic discharge voltage $T_A = +25$ °C, conforming to 2 2000 V_ESD(HBM) ٧/ (human body model) ANSI/ESDA/JEDEC JS-001 $T_A = +25$ °C, conforming to

ANSI/ESDA/JEDEC JS-002

Table 48. ESD absolute maximum ratings

(charge device model)

Electrostatic discharge voltage

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 49. Electrical sensitivity

Symbol	Parameter	Conditions	Class
LU	Static latch-up class	T A = +125 °C conforming to JESD78	II Level A

5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V_SS or above V_DDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

DS12232 Rev 5 79/143

C2a

500

٧

^1. Based on characterization results, not tested in production.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Table 50. I/O current injection susceptibility(1)

| | | | | Functional susceptibility | |------------------------------------|------------------------------------------------|------------------------|-----------------------|---------------------------|------| | Symbol | | Description | Negative
injection | Positive
injection | Unit | | Injected current
IINJ
on pin | All except PA4, PA5, PA6, PB0, PB3,
and PC0 | -5 | N/A | mA | | | | PA4, PA5 | -5 | 0 | mA | | | | PA6, PB0, PB3, and PC0 | 0 | N/A | mA |

^1. Based on characterization results, not tested in production.

5.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.

Note: For information on GPIO configuration, refer to the application note AN4899 "STM32 GPIO configuration for hardware settings and low-power consumption" available from the ST website www.st.com.

Table 51. I/O static characteristics

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
		All except	< 3.6 V	-	-	0.3 x VDDIO1 (2)
(1) VIL	I/O input low level voltage	FT_c	1.62 V < VDDIO1			0.39 x VDDIO1 - 0.06 (3)	V
		FT_c	2.7 V < VDDIO1 < 3.6 V	-	-	0.3 x VDDIO1
			1.62 V < VDDIO1 < 2.7 V	-	-	0.25 x VDDIO1
		All		0.7 x VDDIO1(2)	-	-
VIH(1)	I/O input high level voltage	except FT_c	1.62 V < VDDIO1 < 3.6 V	0.49 x VDDIO1 + 0.26(3)	-	-	V
		FT_c	1.62 V < VDDIO1 < 3.6 V	0.7 x VDDIO1	-	5
Vhys(3)	I/O input hysteresis	TT_xx, FT_xx, RST	1.62 V < VDDIO1 < 3.6 V	-	200	-	mV
			≤ VDDIO1 0 < VIN	-	-	2000
		FT_c	VDDIO1 < VIN ≤ 5 V	-	-	3000(4)
		FT_d	≤ VDDIO1 0 < VIN	-	-	4500
			VDDIO1 < VIN ≤ 5.5 V	-	-	9000(4)
			≤ VDDIO1 0 < VIN	-	-	±70
Ilkg	Input leakage current(3)	Other FT_xx	VDDIO1 ≤ VDDIO1 + 1 V ≤ VIN	-	-	600(4)	nA
			VDDIO1 +1 V < VIN ≤ 5.5 V	-	-	150(4)
			≤ VDDIO1 0 < VIN	-	-	±150
		TT_a	VDDIO1 < VIN ≤ VDDIO1 + 0.3 V	-	-	2000(4)
RPU	Weak pull-up equivalent resistor (5)	VIN = VSS		25	40	55	kΩ
RPD	Weak pull-down equivalent resistor(5)	VIN = VDDIO1		25	40	55	kΩ
CIO	I/O pin capacitance		-	-	5	-	pF

• 1. Refer to Figure 21: I/O input characteristics.
• 2. Tested in production.
• 3. Specified by design. Not tested in production.
• 4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula: $I_{Total_Ileak_max} = 10 \ \mu A + [number of I/Os where V_{IN} is applied on the pad] \times I_{lkg}(Max)$ .
• Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 21.

Figure 21. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to $\pm 8$ mA, and up to $\pm 15$ mA with relaxed $V_{OL}/V_{OH}$ .

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

• The sum of the currents sourced by all the I/Os on V_DDIO1, plus the maximum consumption of the MCU sourced on V_DD, cannot exceed the absolute maximum rating I_VDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on V_SS, plus the maximum consumption of the MCU sunk on V_SS, cannot exceed the absolute maximum rating I_VSS (see Table 18: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).

Table 52. Output voltage characteristics⁽¹⁾⁽²⁾

Symbol	Parameter	Conditions	Min	Max	Unit
V OL	Output low level voltage for an I/O pin	CMOS port (3)	-	0.4	V
V OH	Output high level voltage for an I/O pin	$ I_{IO} = 2 \text{ mA for FT_c I/Os}$ = 8 mA for other I/Os $V_{DDIO1} \ge 2.7 \text{ V}$	V DDIO1 - 0.4	-	٧
V OL (4)	Output low level voltage for an I/O pin	TTL port (3)	-	0.4	V
V OH (4)	Output high level voltage for an I/O pin	$ I_{IO} = 2 \text{ mA for FT_c I/Os}$ = 8 mA for other I/Os $V_{DDIO1} \ge 2.7 \text{ V}$	2.4	-	٧
V OL (4)	Output low level voltage for an I/O pin	All I/Os except FT_c	-	1.3	V
V OH (4)	Output high level voltage for an I/O pin	I IO = 15 mA V DDIO1 ≥ 2.7 V	V DDIO1 - 1.3	-	V
V OL (4)	Output low level voltage for an I/O pin	I IO = 1 mA for FT_c I/Os	-	0.4	V
V OH (4)	Output high level voltage for an I/O pin	= 3 mA for other I/Os V DDIO1 ≥ V DD (min)	V DDIO1 - 0.45	-	V
V OLFM+	Output low level voltage for an FT I/O	I IO = 20 mA V DDIO1 ≥ 2.7 V	-	0.4	V
(4)	pin in FM+ mode (FT I/O with _f option)	$ I_{IO} = 9 \text{ mA}$ $V_{DDIO1} \ge V_{DD}(\text{min})$	-	0.4	]

The I_IO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣI_IO.

Output buffer timing characteristics

The definition and values of input/output AC characteristics are given in Figure 22 and Table 53, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

^2. As PC13, PC14 and PC15 are supplied through the power switch, the sum of currents sourced by those I/Os must not exceed 3 mA.

^3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^4. Specified by design. Not tested in production.

Table 53. Non-FT_c I/O output timing characteristics(1)(2)

| Speed | Symbol | Parameter | Conditions | Min | Max | Unit | |-------|--------|------------------------------------|------------------------------------|-----|-------|------|--| | | | | C=50 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 2 | | | | | C=50 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 0.35 | | | fmax | Maximum frequency | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 3 | MHz | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 0.45 | | 00 | | | C=50 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 100 | | | | | C=50 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 225 | | | tr/tf | Output rise and fall time | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 75 | ns | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 150 | | | | | C=50 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 10 | | | | | C=50 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 2 | | | fmax | Maximum frequency | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 15 | MHz | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 2.5 | | 01 | | | C=50 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 30 | | | | | C=50 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 60 | | | tr/tf | Output rise and fall time | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 15 | ns | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 30 | | | | Maximum frequency | C=50 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 30 | | | | | C=50 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 15 | | | fmax | | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 60 | MHz | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 30 | | 10 | | | C=50 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 11 | | | | | C=50 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 22 | | | tr/tf | Output rise and fall time | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 4 | ns | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 8 | | | | | C=30 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 60 | | | | | C=30 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 30 | | | fmax | Maximum frequency | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 80(3) | MHz | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 40 | | 11 | | | C=30 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 5.5 | | | | | C=30 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 11 | | | | tr/tf
Output rise and fall time | C=10 pF, 2.7 V ≤ VDDIO1
≤ 3.6 V | - | 2.5 | ns | | | | | C=10 pF, 1.6 V ≤ VDDIO1
≤ 2.7 V | - | 5 | | | fmax | Maximum frequency | | - | 1 | MHz | | Fm+ | tf | Output fall time(4) | C=50 pF, 1.6 V ≤ VDDIO1
≤ 3.6 V | - | 5 | ns | ^1. The I/O speed is configured with the OSPEEDRy[1:0] bitfield. The FM+ mode is configured through the SYSCFG_CFGR1 register. Refer to the reference manual RM0444 for the description of the GPIO port configuration.

^2. Specified by design. Not tested in production.

^3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

^4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
		Maximum frequency	C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V	-	2	MHz
	fmax		C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V	-	1
0		Output rise and fall time	C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V	-	170
	tr/tf		C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V	-	330	ns
			C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V	-	10
	fmax	Maximum frequency	C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V	-	5	MHz
1	tr/tf		C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V	-	35
		Output rise and fall time	C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V	-	65	ns

Table 54. FT_c I/O output timing characteristics(1)(2)

^2. Specified by design. Not tested in production.

Figure 22. I/O AC characteristics definition

5.3.15 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU.

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low level voltage - - - 0.3 x VDDIO1 ^V VIH(NRST) NRST input high level voltage - 0.7 x VDDIO1 - -V Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV

Table 55. NRST pin characteristics(1)

^1. The I/O speed is configured using the OSPEEDRy[0] bit. Refer to the reference manual RM0444 for description of the GPIO port configuration.

| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |-----------|----------------------------------------|------------------------|-----|-----|-----|------|--|--| | RPU | Weak pull-up
equivalent resistor(2) | VIN = VSS | 25 | 40 | 55 | kΩ | | VF(NRST) | NRST input filtered
pulse | - | - | - | 70 | ns | | VNF(NRST) | NRST input not filtered
pulse | 1.7 V ≤ VDD
≤ 3.6 V | 350 | - | - | ns | Table 55. NRST pin characteristics(1) (continued)

• 1. Specified by design. Not tested in production.
• 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

MS19878V4 RPU VDD Internal reset External reset circuit(1) NRST(2) Filter 0.1 μF(3)

Figure 23. Recommended NRST pin protection

• 1. The reset network protects the device against parasitic resets.
• 1. The user must ensure that, upon power-on, the level on the NRST pin can exceed the minimum VIH(NRST) level. Otherwise, the device does not exit the power-on reset. This applies to any PF2-NRST configuration set, the GPIO mode inclusive.
• 3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must equal or exceed the minimum length, to guarantee that it is detected by the event controller.

Table 56. EXTI input characteristics(1)

Symbol	Parameter	Min	Typ	Max	Unit
PLEC	Pulse length to event controller	20	-	-	ns

1. Specified by design. Not tested in production.

5.3.17 Analog switch booster

Table 57. Analog switch booster characteristics(1)

Symbol	Parameter	Min	Typ	Max	Unit
VDD	Supply voltage	1.62 V	-	3.6	V
tSU(BOOST)	Booster startup time	-	-	240	µs
IDD(BOOST)	Booster consumption for 1.62 V ≤ VDD ≤ 2.0 V	-	-	250
	Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V	-	-	500	µA
	Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V	-	-	900
1. Specified by design. Not tested in production.

5.3.18 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 58 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 21: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Table 58. ADC characteristics(1)

Symbol	Parameter	Conditions(2)	Min	Typ	Max	Unit
VDDA	Analog supply voltage	-	1.62	-	3.6	V
	Positive reference	VDDA ≥ 2 V	2	-	VDDA
VREF+	voltage	VDDA < 2 V		VDDA		V
	ADC clock frequency	Range 1	0.14	-	35	MHz
fADC		Range 2	0.14	-	16
DADC(3)	ADC analog clock duty cycle	-	45	-	55	%
		12 bits	-	-	2.50
	Sampling rate	10 bits	-	-	2.92
fs		8 bits	-	-	3.50	MSps
		6 bits	-	-	4.38
	External trigger	fADC = 35 MHz; 12 bits	-	-	2.33
fTRIG	frequency	12 bits	-	-	fADC/15	MHz
(4) VAIN	Conversion voltage range	-	VSSA	-	VREF+	V
RAIN	External input impedance	-	-	-	50	kΩ
CADC	Internal sample and hold capacitor	-	-	5	-	pF

Table 58. ADC characteristics⁽¹⁾ (continued)

Symbol	Parameter	Conditions (2)	Min	Typ	Max	Unit
t STAB	ADC power-up time	-		2	•	Conversion cycle
	Calibration time	f ADC = 35 MHz		2.35		μs
$t_CAL$	Calibration time	-		82		1/f ADC
		CKMODE[1:0] = 00	1.5 f ADC + 2 f PCLK cycles	-	1.5 f ADC + 3 f PCLK cycles	-
W LATENCY	ADC_DR register write latency	CKMODE[1:0] = 01	-	4.5	-
	laterity	CKMODE[1:0] = 10	-	8.5	-	1/f PCLK
		CKMODE[1:0] = 11	-	2.5	-
		CKMODE[1:0] = 00	2	-	3	1/f ADC
	Trigger conversion	CKMODE[1:0] = 01		6.5	1
t LATR	latency	CKMODE[1:0] = 10		12.5		1/f PCLK
		CKMODE[1:0] = 11		3.5
		f ADC = 35 MHz;	0.043	-	4.59	μs
t s	O I'm I'm	V DDA > 2V	1.5	-	160.5	1/f ADC
	Sampling time	f ADC = 35 MHz;	0.1	-	4.59	μs
		V DDA < 2V	3.5		160.5	1/f ADC
t ADCVREG_STUP	ADC voltage regulator start-up time	-	-	-	20	μs
	Total conversion time	f ADC = 35 MHz Resolution = 12 bits	0.40	-	4.95	μs
t CONV	(including sampling time)	Resolution = 12 bits	t s + 12.5 cycles for successive approximation = 14 to 173		1/f ADC
t IDLE	Laps of time allowed between two conversions without rearm	-	-	-	100	μs
		f s = 2.5 MSps	-	410	-
I DDA(ADC)	ADC consumption from V DDA	f s = 1 MSps	-	164	-	μA
	TODA	f s = 10 kSps	-	17	-	1
		f s = 2.5 MSps	-	65	-
I DDV(ADC)	ADC consumption from V REF+	f s = 1 MSps	-	26	-	μΑ
	"" KEF+	f s = 10 kSps	-	0.26	-	1

^1. Specified by design. Not tested in production.

^2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when $V_{DDA}$ < 2.4 V and disabled when $V_{DDA} \ge 2.4$ V.

^3. This requirement is granted when the incoming clock (PCLK or ADC asynchronous clock) is divided by two or more in the ADC. For other cases, refer to the reference manual section ADC clock for information on how to fulfill this requirement.

1. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate functions for further details.

Table 59. Maximum ADC RAIN .

Resolution	Sampling cycle at 35 MHz	Sampling time at 35 MHz [ns]	Max. RAIN(1)(2) (Ω)
	1.5(3)	43	50
	3.5	100	680
	7.5	214	2200
	12.5	357	4700
12 bits	19.5	557	8200
	39.5	1129	15000
	79.5	2271	33000
	160.5	4586	50000
	1.5(3)	43	68
	3.5	100	820
	7.5	214	3300
	12.5	357	5600
10 bits	19.5	557	10000
	39.5	1129	22000
	79.5	2271	39000
	160.5	4586	50000
	1.5(3)	43	82
	3.5	100	1500
	7.5	214	3900
	12.5	357	6800
8 bits	19.5	557	12000
	39.5	1129	27000
	79.5	2271	50000
	160.5	4586	50000

Table 59. Maximum ADC RAIN . (continued)

Resolution	Sampling cycle at 35 MHz	Sampling time at 35 MHz [ns]	Max. RAIN(1)(2) (Ω)
	1.5(3)	43	390
	3.5	100	2200
	7.5	214	5600
	12.5	357	10000
6 bits	19.5	557	15000
	39.5	1129	33000
	79.5	2271	50000
	160.5	4586	50000

^1. Specified by design. Not tested in production.

Table 60. ADC accuracy(1)(2)(3)

Symbol	Parameter	Conditions(4)	Min	Typ	Max	Unit
ET		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	-	±3	±4
	Total unadjusted error	2 V < VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	-	±3	±6.5	LSB
		1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	-	±3	±7.5
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	-	±1.5	±2
EO	Offset error	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	-	±1.5	±4.5	LSB
		1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	-	±1.5	±5.5
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V.

^3. Only allowed with VDDA > 2 V

Table 60. ADC accuracy(1)(2)(3) (continued)

Symbol	Parameter	Conditions(4)	Min	Typ	Max	Unit
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	-	±3	±3.5
EG	Gain error	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	-	±3	±5	LSB
	1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	-	±3	±6.5
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	-	±1.2	±1.5
ED	Differential linearity error	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	-	±1.2	±1.5	LSB
		1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	-	±1.2	±1.5
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	-	±2.5	±3
EL	Integral linearity error	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	-	±2.5	±3	LSB
		1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	-	±2.5	±3.5
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	10.1	10.2	-
ENOB	Effective number of bits	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	9.6	10.2	-	bit
		1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	9.5	10.2	-
Table 60. ADC accuracy(1)(2)(3) (continued)

Symbol	Parameter	Conditions(4)	Min	Typ	Max	Unit
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	62.5	63	-
SINAD	Signal-to-noise and distortion ratio	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	59.5	63	-	dB
		1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	59	63	-
	Signal-to-noise SNR ratio	VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	63	64	-
		2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	60	64	-	dB
		1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	60	64	-
		VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C	-	-74	-73
THD	Total harmonic distortion	2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range	-	-74	-70	dB
		1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;	-	-74	-70
1. Based on characterization results, not tested in production.

^2. ADC DC accuracy values are measured after internal calibration.

^3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive negative current.

^4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V.

Figure 24. ADC accuracy characteristics

• 1. Refer to Table 58: ADC characteristics for the values of RAIN and CADC.
• C_parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 51: I/O static characteristics for the value of the pad capacitance). A high C_parasitic value downgrades conversion accuracy. To remedy this, f_ADC should be reduced.
• 1. Refer to Table 51: I/O static characteristics for the values of I_lkq.
• 1. Refer to Figure 13: Power supply scheme.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DS12232 Rev 5 93/143

5.3.19 Digital-to-analog converter characteristics

Table 61. DAC characteristics(1)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
VDDA	Analog supply voltage for DAC ON	pin not connected (internal connection only)	DAC output buffer OFF, DAC_OUT	1.71	-	3.6	V
		Other modes		1.80	-
VREF+	Positive reference voltage	pin not connected (internal connection only)	DAC output buffer OFF, DAC_OUT	1.71 -	VDDA	V
		Other modes		1.80	-
		DAC output	connected to VSSA	5	-	-
RL	Resistive load	buffer ON	connected to VDDA		-	-	kΩ
RO	Output Impedance		DAC output buffer OFF		11.7	13.8	kΩ
	Output impedance sample	VDD = 2.7 V		-	-	2
RBON	and hold mode, output buffer ON	VDD = 2.0 V		-	-	3.5	kΩ
	Output impedance sample	VDD = 2.7 V		-	-	16.5
RBOFF	and hold mode, output buffer OFF	VDD = 2.0 V			-	18.0	kΩ
CL		DAC output buffer ON		-	-	50	pF
CSH	Capacitive load	Sample and hold mode		-	0.1	1	µF
VDAC_OUT	Voltage on DAC_OUT output	DAC output buffer ON		0.2	-	VREF+ – 0.2	V
		DAC output buffer OFF		0	-	VREF+
			±0.5 LSB	-	1.7	3
	Settling time (full scale: for a 12-bit code transition	Normal mode DAC output	±1 LSB	-	1.6	2.9
	between the lowest and the	buffer ON	±2 LSB	-	1.55	2.85
tSETTLING	highest input codes when DAC_OUT reaches final	CL ≤ 50 pF, RL ≥ 5 kΩ	±4 LSB	-	1.48	2.8	µs
	value ±0.5LSB, ±1 LSB,		±8 LSB	-	1.4	2.75
	±2 LSB, ±4 LSB, ±8 LSB)		Normal mode DAC output buffer OFF, ±1LSB, CL = 10 pF		2	2.5
	Wakeup time from off state (setting the ENx bit in the	Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ		-	4.2	7.5
tWAKEUP(2)	DAC Control register) until final value ±1 LSB	Normal mode DAC output buffer OFF, CL ≤ 10 pF		-	2	5	µs
PSRR	VDDA supply rejection ratio	CL ≤ 50 pF, RL = 5 kΩ, DC	Normal mode DAC output buffer ON	-	-80	-28	dB

Table 61. DAC characteristics(1) (continued)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
	Minimum time between two consecutive writes into the DAC_DORx register to	001 CL ≤ 50 pF; RL ≥ 5 kΩ	DAC_MCR:MODEx[2:0] = 000 or	1	-	-
TW_to_W	guarantee a correct DAC_OUT for a small variation of the input code (1 LSB)	DAC_MCR:MODEx[2:0] = 010 or 011 CL ≤ 10 pF		1.4	-	-	µs
		DAC_OUT	DAC output buffer ON, CSH = 100 nF	-	0.7	3.5
	Sampling time in sample and hold mode (code transition between the	pin connected	DAC output buffer OFF, CSH = 100 nF	-	10.5	18	ms
tSAMP	lowest input code and the highest input code when DACOUT reaches final value ±1LSB)	DAC_OUT pin not connected (internal connection only)	DAC output buffer OFF	-	2	3.5	µs
Ileak	Output leakage current	Sample and hold mode, DAC_OUT pin connected		-	-	-(3)	nA
CIint	Internal sample and hold capacitor		-	5.2	7	8.8	pF
tTRIM	Middle code offset trim time	DAC output buffer ON		50	-	-	µs
	Middle code offset for 1 trim	VREF+ = 3.6 V		-	1500	-
Voffset	code step	VREF+ = 1.8 V		-	750	-	µV
		DAC output	No load, middle code (0x800)	-	315	500
		buffer ON	No load, worst code (0xF1C)	-	450	670
IDDA(DAC)	DAC consumption from VDDA	DAC output buffer OFF	No load, middle code (0x800)	-	-	0.2	µA
		100 nF	Sample and hold mode, CSH =	-	315 ₓ Ton/(Ton+ (4) Toff)	670 ₓ Ton/(Ton+ (4) Toff)
Symbol	Parameter		Conditions			Max	Unit
-----------	-------------------------------	--------------------------------------------------------------	---------------------------------------------------------------	---	------------------------------------	------------------------------------	------
		DAC output	No load, middle code (0x800)	-	185	240
		buffer ON	No load, worst code (0xF1C)	-	340	400	µA
IDDV(DAC)	DAC consumption from VREF+	DAC output buffer OFF	No load, middle code (0x800)	-	155	205
		Sample and hold mode, buffer ON, CSH = 100 nF, worst case		-	185 ₓ Ton/(Ton+ (4) Toff)	400 ₓ Ton/(Ton+ (4) Toff)
			Sample and hold mode, buffer OFF, CSH = 100 nF, worst case		155 ₓ Ton/(Ton+ (4) Toff)	205 ₓ Ton/(Ton+ (4) Toff)
Table 61. DAC characteristics(1) (continued)

• 1. Specified by design. Not tested in production.
• 1. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
• 1. Refer to Table 51: I/O static characteristics.
• 4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0444 reference manual for more details.

MSv47959V1 12-bit digital-to-analog converter Buffered / non-buffered DAC DAC_OUTx RLOAD CLOAD Buffer(1)

Figure 26. 12-bit buffered / non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Table 62. DAC accuracy(1)

| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |----------------------|-----------------------|----------------------|------------|-----|-----|------|--| | | Differential non | DAC output buffer ON | - | - | ±2 | | DNL
linearity (2) | DAC output buffer OFF | - | - | ±2 | LSB | | - | monotonicity | 10 bits | guaranteed | | LSB | Table 62. DAC accuracy(1) (continued)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
INL	Integral non	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ		-	-	±4	LSB
	linearity(3)	DAC output buffer OFF CL ≤ 50 pF, no RL		-	-	±4
		DAC output buffer ON	VREF+ = 3.6 V	-	-	±12
Offset	Offset error at code 0x800(3)	CL ≤ 50 pF, RL ≥ 5 kΩ	VREF+ = 1.8 V	-	-	±25	LSB
		DAC output buffer OFF CL ≤ 50 pF, no RL		-	-	±8
Offset1	Offset error at code 0x001(4)	DAC output buffer OFF CL ≤ 50 pF, no RL		-	-	±5	LSB
OffsetCal	Offset Error at code 0x800	DAC output buffer ON	VREF+ = 3.6 V	-	-	±5	LSB
	after calibration	CL ≤ 50 pF, RL ≥ 5 kΩ	VREF+ = 1.8 V	-	-	±7
Gain	Gain error(5)	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ		-	-	±0.5	%
		DAC output buffer OFF - CL ≤ 50 pF, no RL		-	±0.5
TUE	Total unadjusted	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ		-	-	±30	LSB
	error	DAC output buffer OFF CL ≤ 50 pF, no RL		-	-	±12
TUECal	Total unadjusted error after calibration	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ		-	-	±23	LSB
	Signal-to-noise	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ 1 kHz, BW 500 kHz		-	71.2	-
SNR	ratio	DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz BW 500 kHz		-	71.6	-	dB
	Total harmonic	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz		-	-78	-
THD	distortion	DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz		-	-79	-	dB
	Signal-to-noise	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz		-	70.4	-
SINAD	and distortion ratio	DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz		-	71	-	dB

| Table 62. DAC accuracy(1) (continued) |

---------------------------------------	--

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
ENOB	Effective number of bits	DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz	-	11.4	-	bits
		DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz	-	11.5	-

• 1. Specified by design. Not tested in production.
• 1. Difference between two consecutive codes 1 LSB.
• 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
• 1. Difference between the value measured at Code (0x001) and the ideal value.
• 1. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.

5.3.20 Voltage reference buffer characteristics

Table 63. VREFBUF characteristics(1)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
	VREFBUF	VRS = 0		2.4	-	3.6
VDDA	operating voltage	VRS = 1		2.8	-	3.6	V
VREFBUF_	Voltage	Iload =	VRS = 0	2.038(2)	2.042	2.046
OUT	reference output	100 µA T = 30 °C	VRS = 1	2.497(2)	2.5	2.503	V
TRIM	Trim step resolution	-			±0.05	±0.1	%
CL	Load capacitor	-			1	1.5	µF
esr	Equivalent Serial Resistor of Cload	-		-	-	2	Ω
Iload	Static load current	-		-	-	4	mA
			Iload = 500 µA	-	200	1000	ppm/V
Iline_reg	Line regulation	2.8 V ≤ VDDA ≤ 3.6 V	Iload = 4 mA	-	100	500
Iload_reg	Load regulation	500 μA ≤ Iload ≤4 mA	Normal mode	-	50	500	ppm/mA
TCoeff_vrefbuf	Temperature coefficient of VREFBUF(3)	-40 °C < TJ < +125 °C		-	-	50	ppm/ °C
	Power supply	DC		40	60	-
PSRR	rejection	100 kHz		25	40	-	dB
		CL = 0.5 µF(4)			300	350
tSTART	Start-up time	(4) CL = 1.1 µF		-	500	650	µs
		CL = 1.5 µF(4)		-	650	800
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
-------------	---------------------------------------------------------------------------------------------	----------------	-----	-----	-----	------
IINRUSH	Control of maximum DC current drive on VREFBUF_OUT during start-up phase (5)	-	-	8	-	mA
	VREFBUF	Iload = 0 µA	-	16	25
IDDA(VREFBU	consumption	Iload = 500 µA	-	18	30	µA
F)	from VDDA	Iload = 4 mA	-	35	50
Table 63. VREFBUF characteristics(1) (continued)

• 1. Specified by design. Not tested in production.
• 2. If the VDDA is below the VREFBUF operating voltage, the voltage reference buffer can not maintain accurately the output voltage and it could drop down to VDDA - 150mV.
• 1. The temperature coefficient at VREF+ output is the sum of TCoeff_vrefint and TCoeff_vrefbuf.
• 4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
• 1. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.

5.3.21 Comparator characteristics

Table 64. COMP characteristics(1)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
VDDA	Analog supply voltage		-	1.62	-	3.6	V
VIN	Comparator input voltage range		-	0	-	VDDA	V
VBG(2)	Scaler input voltage		-	VREFINT			V
VSC	Scaler offset voltage		-	-	±5	±10	mV
	Scaler static	BRG_EN=0 (bridge disable)		-	200	300	nA
IDDA(SCALER)	consumption from VDDA	BRG_EN=1 (bridge enable)		-	0.8	1	µA
tSTART_SCALER	Scaler startup time	-		-	100	200	µs
	Comparator startup time to reach	High-speed mode		-	-	5	µs
tSTART	propagation delay specification	Medium-speed mode		-	-	15
		200 mV step;	High-speed mode	-	30	50	ns
	Propagation delay	100 mV overdrive	Medium-speed mode	-	0.3	0.6	µs
tD		>200 mV step;	High-speed mode	-	-	70	ns
		100 mV overdrive	Medium-speed mode	-	-	1.2	µs
Voffset	Comparator offset error	Full common mode range		-	±5	±20	mV

	Table 64. COMP characteristics(1) (continued)
--	-----------------------------------------------

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
		No hysteresis		-	0	-
	Comparator	Low hysteresis		-	10	-
Vhys	hysteresis	Medium hysteresis		-	20	-	mV
		High hysteresis		-	30	-
		Medium-speed mode	Static	-	5	7.5
	Comparator		With 50 kHz and ±100 mV overdrive square signal	-	6	-
IDDA(COMP)	consumption from VDDA		Static	-	250	400	µA
		High-speed mode	With 50 kHz and ±100 mV overdrive square signal	-	250	-
1. Specified by design. Not tested in production.

5.3.22 Temperature sensor characteristics

Table 65. TS characteristics

Symbol	Parameter	Min	Typ	Max	Unit
(1) TL	VTS linearity with temperature	-	±1	±2	°C
Avg_Slope(2)	Average slope	2.3	2.5	2.7	mV/°C
V30	Voltage at 30°C (±5 °C)(3)	0.742	0.76	0.785	V
tSTART(TS_BUF)(1)	Sensor Buffer Start-up time in continuous mode(4)	-	8	15	µs
tSTART(1)	Start-up time when entering in continuous mode(4)	-	70	120	µs
tS_temp(1)	ADC sampling time when reading the temperature	5	-	-	µs
IDD(TS)(1)	Temperature sensor consumption from VDD, when selected by ADC	-	4.7	7	µA

^1. Specified by design. Not tested in production.

5.3.23 VBAT monitoring characteristics

Table 66. VBAT monitoring characteristics

Symbol	Parameter	Min	Typ	Max	Unit
R	Resistor bridge for VBAT	-	39	-	kΩ
Q	Ratio on VBAT measurement	-	3	-	-

^2. Refer to Table 24: Embedded internal voltage reference.

^2. Based on characterization results, not tested in production.

^3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.

^4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

Table 66. VBAT monitoring characteristics (continued)

Symbol	Parameter	Min	Typ	Max	Unit
Er(1)	Error on Q	-10	-	10	%
tS_vbat(1)	ADC sampling time when reading the VBAT	12	-	-	µs

^1. Specified by design. Not tested in production.

Table 67. VBAT charging characteristics

| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |--------|----------------------|------------|-----|-----|-----|------|--| | RBC | Battery | VBRS = 0 | - | 5 | - | | | charging
resistor | VBRS = 1 | - | 1.5 | - | kΩ |

5.3.24 Timer characteristics

The parameters given in the following tables are specified by design and not tested in production. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 68. TIMx(1) characteristics

Symbol	Parameter	Conditions	Min	Max	Unit
		-	1	-	tTIMxCLK
tres(TIM)	Timer resolution time	fTIMxCLK = 64 MHz	15.625	-	ns
	Timer external clock frequency	-	0	fTIMxCLK/2	MHz
fEXT	on CH1 to CH4	fTIMxCLK = 64 MHz	0	40
		TIMx (except TIM2)	-	16
ResTIM	Timer resolution	TIM2	-	32	bit
		-	1	65536	tTIMxCLK
tCOUNTER	16-bit counter clock period	fTIMxCLK = 64 MHz	0.015625	1024	µs
tMAX_COUNT	Maximum possible count with	-	-	65536 × 65536	tTIMxCLK
	32-bit counter	fTIMxCLK = 64 MHz	-	67.10	s

^1. TIMx is used as a general term to refer to a timer (for example, TIM1).

Prescaler divider	PR[2:0] bits	Min timeout RL[11:0]= 0x000	Max timeout RL[11:0]= 0xFFF	Unit
/4	0	0.125	512
/8	1	0.250	1024
/16	2	0.500	2048
/32	3	1.0	4096	ms
/64	4	2.0	8192
/128	5	4.0	16384
/256	6 or 7	8.0	32768
Table 69. IWDG min/max timeout period at 32 kHz LSI clock(1)

5.3.25 Characteristics of communication interfaces

I 2 C-bus interface characteristics

The I2C-bus interface meets timing requirements of the I2C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are ensured by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the minimum shown in the following table.

| Symbol | Parameter | Condition | | Typ | Unit | |--------------|---------------------------------------------------------------------------|----------------|------------------------|-----|------|--| | | | | Standard-mode | 2 | | | Minimum I2CCLK
frequency for correct
operation of I2C
peripheral | | Analog filter enabled | | MHz | | | | Fast-mode | DNF = 0 | 9 | | | | | Analog filter disabled | | fI2CCLK(min) | | | DNF = 1 | 9 | | | | | Analog filter enabled | | | | | DNF = 0 | 18 | | | | Fast-mode Plus | Analog filter disabled | | | | | DNF = 1 | 16 | Table 70. Minimum I2CCLK frequency

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins

^1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period.

support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics:

Table 71. I2C analog filter characteristics(1)

Symbol	Parameter	Min	Max	Unit
tAF	Limiting duration of spikes suppressed by the filter(2)	50	260	ns

• 1. Based on characterization results, not tested in production.
• 1. Spikes shorter than the limiting duration are suppressed.

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 72 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. The additional general conditions are:

• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 72. SPI characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
		Master mode 1.65 < VDD < 3.6 V Range 1			32
		Master transmitter 1.65 < VDD < 3.6 V Range 1			32
fSCK	SPI clock frequency	Slave receiver 1.65 < VDD < 3.6 V Range 1	-	-	32	MHz
1/tc(SCK)		Slave transmitter/full duplex 2.7 < VDD < 3.6 V Range 1			32
		Slave transmitter/full duplex 1.65 < VDD < 3.6 V Range 1
		1.65 < VDD < 3.6 V Range 2			8
tsu(NSS)	NSS setup time	Slave mode, SPI prescaler = 2	4 ₓ TPCLK	-	-	ns
th(NSS)	NSS hold time	Slave mode, SPI prescaler = 2	2 ₓ TPCLK	-	-	ns

Table 72. SPI characteristics(1) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tw(SCKH)	SCK high time	Master mode	TPCLK - 1.5	TPCLK	TPCLK + 1.5	ns
tw(SCKL)	SCK low time	Master mode	TPCLK - 1.5	TPCLK	TPCLK + 1.5	ns
tsu(MI)	Master data input setup time	-	1	-	-	ns
tsu(SI)	Slave data input setup time	-	1	-	-	ns
th(MI)	Master data input hold time	-	5	-	-	ns
th(SI)	Slave data input hold time	-	1	-	-	ns
ta(SO)	Data output access time	Slave mode	9	-	34	ns
tdis(SO)	Data output disable time	Slave mode	9	-	16	ns
		2.7 < VDD < 3.6 V Range 1	-	9	14
tv(SO)	Slave data output valid time	1.65 < VDD < 3.6 V Range 1	-	9	21	ns
		1.65 < VDD < 3.6 V Voltage Range 2	-	11	24
tv(MO)	Master data output valid time	-	-	3	5	ns
th(SO)	Slave data output hold time	-	5	-	-	ns
th(MO)	Master data output hold time	-	1	-	-	ns

^1. Based on characterization results, not tested in production.

Figure 27. SPI timing diagram - slave mode and CPHA = 0

Figure 29. SPI timing diagram - master mode

Table 73. I2S characteristics(1)

| Symbol | Parameter | Conditions | Min | Max | Unit | |------------|------------------------------------------------|---------------------------------------------------------------------------------------|-------|--------|------|--| | fMCK | I2S main clock output | fMCK= 256 x Fs; (Fs = audio sampling
frequency)
Fsmin = 8 kHz; Fsmax = 192 kHz; | 2.048 | 49.152 | MHz | | | | Master data | - | 64xFs | MHz | | fCK | I2S clock frequency | Slave data | - | 64xFs | | DCK | I2S clock frequency duty
cycle | Slave receiver | 30 | 70 | % | | tv(WS) | WS valid time | Master mode | - | 8 | ns | | th(WS) | WS hold time | Master mode | 2 | - | ns | | tsu(WS) | WS setup time | Slave mode | 4 | - | ns | | th(WS) | WS hold time | Slave mode | 2 | - | ns | | tsu(SD_MR) | | Master receiver | 4 | - | ns | | tsu(SD_SR) | Data input setup time | Slave receiver | 5 | - | ns | | th(SD_MR) | Data input hold time | Master receiver | 4.5 | - | ns | | th(SD_SR) | | Slave receiver | 2 | - | ns | | | Data output valid time - | after enable edge; 2.7 < VDD < 3.6V | | 16 | | tv(SD_ST) | slave transmitter | after enable edge; 1.65 < VDD < 3.6V | - | 23 | ns | | tv(SD_MT) | Data output valid time -
master transmitter | after enable edge | | 5.5 | ns | Table 73. I2S characteristics(1) (continued)

Symbol	Parameter	Conditions	Min	Max	Unit
th(SD_ST)	Data output hold time - slave transmitter	after enable edge	8	-	ns
th(SD_MT)	Data output hold time - master transmitter	after enable edge	1	-	ns

^1. Based on characterization results, not tested in production.

Figure 30. I2S slave timing diagram (Philips protocol)

• 1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.
• 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 31. I2S master timing diagram (Philips protocol)

• 1. Based on characterization results, not tested in production.
• 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

USART (SPI mode) characteristics

Unless otherwise specified, the parameters given in Table 74 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. The additional general conditions are:

• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART).

| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |----------|-----------------------|-------------|-------------|-----|-----|------|--|--| | | USART clock frequency | Master mode | - | - | 8 | MHz | | fCK | | Slave mode | - | - | 21 | | tsu(NSS) | NSS setup time | Slave mode | Tker(1) + 2 | - | - | ns | | th(NSS) | NSS hold time | Slave mode | 2 | - | - | ns | Table 74. USART characteristics in SPI mode

Table 74. USART characteristics in SPI mode

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t w(CKH)	CK high time	Master mode	1 / f CK / 2 - 1	1 / f CK / 2	1 / f CK / 2	ns
t w(CKL)	CK low time	Master mode	- 1	171CK 7 2	+ 1	ns
4	Data input actus time	Master mode	$T_{ker}^{(1)} + 2$	-	-	ns
t su(RX)	Data input setup time	Slave mode	4	-	-	ns
4	Data input hold time	Master mode	1	-	-	ns
t h(RX)	Data input hold time	Slave mode	0.5	-	-	ns
+	Data output valid time	Master mode	-	0.5	1	ns
t v(TX)	Data output valid time	Slave mode	-	10	19	ns
4	Data autout bald times	Master mode	0	-	-	ns
t h(TX)	Data output hold time	Slave mode	7	-	-	ns

^1. T_ker is the usart_ker_ck_pres clock period

Figure 32. USART timing diagram in SPI master mode

Figure 33. USART timing diagram in SPI slave mode

UCPD characteristics

UCPD1 and UCPD2 controllers comply with USB Type-C Rev.2 and USB Power Delivery Rev. 3.0 specifications.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	UCPD operating supply	Sink mode only	3.0	3.3	3.6	V
VDD voltage		Sink and source mode	3.135	3.3	3.465
Vswing	Output voltage swing	-	1.05	-	1.2	V
ZDRV	Output driver impedance	Driving high or low	33	-	75	Ω

Table 75. UCPD operating conditions

STM32G071x8/xB Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

6.1 Device marking

Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors" (TN1433) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1.

Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

DS12232 Rev 5 111/143

Package information STM32G071x8/xB

6.2 WLCSP25 package information

Figure 34. WLCSP - 25 balls, 2.30x2.48 mm, 0.4 mm pitch, wafer level chip scale package outline

• 1. Drawing is not to scale.
• 1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
• 1. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
• 4. Bump position designation per JESD 95-1, SPP-010.

Table 76. WLCSP - 25 balls, 2.30x2.48 mm, 0.4 mm pitch, wafer level chip scale mechanical data

| Symbol | millimeters | | | inches ⁽¹⁾ | |------------------|-------------|----------------------|------|-----------------------|-------|-------| | Symbol | Min | Typ | Max | Min | Typ | Max | | A ⁽²⁾ | - | - | 0.59 | - | - | 0.023 | | A1 | - | 0.18 | - | - | 0.007 | - | | A2 | - | 0.38 | - | - | 0.015 | - | | A3 | - | 0.025 ⁽³⁾ | - | - | 0.001 | - | | b | 0.22 | 0.25 | 0.28 | 0.009 | 0.010 | 0.011 | | D | 2.28 | 2.30 | 2.32 | 0.090 | 0.091 | 0.091 | | E | 2.46 | 2.48 | 2.50 | 0.097 | 0.098 | 0.098 |

STM32G071x8/xB Package information

Table 76. WLCSP - 25 balls, 2.30x2.48 mm, 0.4 mm pitch, wafer level chip scale mechanical data (continued)

| | millimeters | | | inches(1) | |--------|-------------|-------|------|-----------|-------|-------| | Symbol | Min | Typ | Max | Min | Typ | Max | | e | - | 0.40 | - | - | 0.016 | - | | e1 | - | 1.60 | - | - | 0.063 | - | | e2 | - | 1.60 | - | - | 0.063 | - | | F(4) | - | 0.350 | - | - | 0.014 | - | | G(4) | - | 0.440 | - | - | 0.017 | - | | aaa | - | - | 0.10 | - | - | 0.004 | | bbb | - | - | 0.10 | - | - | 0.004 | | ccc | - | - | 0.10 | - | - | 0.004 | | ddd | - | - | 0.05 | - | - | 0.002 | | eee | - | - | 0.05 | - | - | 0.002 |

• 1. Values in inches are converted from mm and rounded to 3 decimal digits.
• 1. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2.
• 1. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
• 4. Calculated dimensions are rounded to the 3rd decimal place

Figure 35. WLCSP - 25 balls, 2.30x2.48 mm, 0.4 mm pitch, wafer level chip scale recommended footprint

1. Dimensions are expressed in millimeters.

Table 77. WLCSP25 recommended PCB design rules

Dimension	Recommended values
Pitch	0.4 mm
Dpad	0,225 mm
Dsm	0.290 mm typ. (depends on soldermask registration tolerance)

Package information STM32G071x8/xB

Table 77. WLCSP25 recommended PCB design rules

Dimension	Recommended values
Stencil opening	0.250 mm
Stencil thickness	0.100 mm

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Figure 36. WLCSP25 package marking example

STM32G071x8/xB Package information

6.3 UFQFPN28 package information (A0B0)

UFQFPN28 is a 28-lead, 4 x 4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 37. UFQFPN28 - Outline

1. Drawing is not to scale.

Table 78. UFQFPN28 – Mechanical data(1)

| | millimeters | | | inches | |--------|-------------|-------|-------|--------|--------|--------| | Symbol | Min | Typ | Max | Min | Typ | Max | | A | 0.500 | 0.550 | 0.600 | 0.0197 | 0.0217 | 0.0236 | | A1 | - | 0.000 | 0.050 | - | 0.0000 | 0.0020 | | D | 3.900 | 4.000 | 4.100 | 0.1535 | 0.1575 | 0.1614 | | D1 | 2.900 | 3.000 | 3.100 | 0.1142 | 0.1181 | 0.1220 | | E | 3.900 | 4.000 | 4.100 | 0.1535 | 0.1575 | 0.1614 | | E1 | 2.900 | 3.000 | 3.100 | 0.1142 | 0.1181 | 0.1220 | | L | 0.300 | 0.400 | 0.500 | 0.0118 | 0.0157 | 0.0197 | | L1 | 0.250 | 0.350 | 0.450 | 0.0098 | 0.0138 | 0.0177 | | T | - | 0.152 | - | - | 0.0060 | - | | b | 0.200 | 0.250 | 0.300 | 0.0079 | 0.0098 | 0.0118 | | e | - | 0.500 | - | - | 0.0197 | - |

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Package information STM32G071x8/xB

Figure 38. UFQFPN28 – Footprint example

1. Dimensions are expressed in millimeters.

6.4 LQFP32 package information (5V)

This LQFP is a 32-pin, 7 x 7 mm, low-profile quad flat package.

Note: Figure 39 is not to scale.

Refer to the notes section for the list of notes on Figure 39 and Table 79.

Figure 39. LQFP32 - Outline

Package information STM32G071x8/xB

Table 79. LQFP32 - Mechanical data

| | | millimeters | | inches(14) | |---------------|----------------|-------------|------|------------|------------|--------| | Symbol | Min | Typ | Max | Min | Typ | Max | | θ | 0° | 3.5° | 7° | 0° | 3.5° | 7° | | θ1 | 0° | - | - | 0° | - | - | | θ2 | 10° | 12° | 14° | 10° | 12° | 14° | | θ3 | 10° | 12° | 14° | 10° | 12° | 14° | | A | - | - | 1.60 | - | - | 0.0630 | | A1(12) | 0.05 | - | 0.15 | 0.0020 | - | 0.0059 | | A2 | 1.35 | 1.40 | 1.45 | 0.0531 | 0.0551 | 0.0571 | | b(9)(11) | 0.30 | 0.37 | 0.45 | 0.0118 | 0.0146 | 0.0177 | | b1(11) | 0.30 | 0.35 | 0.40 | 0.0118 | 0.0128 | 0.0157 | | c(11) | 0.09 | - | 0.20 | 0.0035 | - | 0.0079 | | c1(11) | 0.09 | - | 0.16 | 0.0035 | - | 0.0063 | | D(4) | | 9.00 BSC | | | 0.3543 BSC | | D1(2)(5) | | 7.00 BSC | | | 0.2756 BSC | | e | | 0.80 BSC | | 0.0315 BSC | | E(4) | | 9.00 BSC | | 0.3543 BSC | | E1(2)(5) | | 7.00 BSC | | | 0.2756 BSC | | L | 0.45 | 0.60 | 0.75 | 0.0177 | 0.0236 | 0.0295 | | L1 | | 1.00 REF | | | 0.0394 REF | | N(13) | | | | 32 | | R1 | 0.08 | - | - | 0.0031 | - | - | | R2 | 0.08 | - | 0.20 | 0.0031 | - | 0.0079 | | S | 0.20 | - | - | 0.0079 | - | - | | aaa(1)(7)(15) | 0.20 | | | | 0.0079 | | bbb(1)(7)(15) | 0.20 | | | 0.0079 | | ccc(1)(7)(15) | 0.10 | | | 0.0039 | | ddd(1)(7)(15) | 0.20
0.0079 |

Notes:

• 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
• 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
• 1. Datums A-B and D to be determined at datum plane H.
• 4. To be determined at the seating datum plane C.
• 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is "0.25 mm" per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
• 1. Details of pin 1 identifier are optional but must be located within the zone indicated.
• 7. All dimensions are in millimeters.
• 1. No intrusion is allowed inwards the leads.
• 9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
• 1. The exact shape of each corner is optional.
• 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
• 12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
• 13. N is the number of terminal positions for the specified body size.
• 14. Values in inches are converted from mm and rounded to four decimal digits.
• 15. Recommended values and tolerances.

DS12232 Rev 5 119/143

Package information STM32G071x8/xB

Figure 40. LQFP32 – Footprint example

1. Dimensions are expressed in millimeters.

STM32G071x8/xB Package information

6.5 UFQFPN32 package information (A0B8)

This UFQFPN is a 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.

Note: Figure 41 and Figure 42 are not to scale.

Refer to the notes section for the list of notes on Figure 41, Table 80, and Table 81.

Figure 41. UFQFPN32 - Outline

Package information STM32G071x8/xB

Table 80. UFQFPN32 - Mechanical data

| | Millimeters | | | Inches(23) | |-----------|-------------|----------|------|------------|--------|--------| | Symbol | Min | Typ | Max | Min | Typ | Max | | A(17)(18) | 0.50 | 0.55 | 0.60 | 0.0197 | 0.0217 | 0.0236 | | A1(19) | 0.00 | - | 0.05 | 0.000 | - | 0.0020 | | b(21)(30) | 0.18 | 0.25 | 0.30 | 0.0071 | 0.0098 | 0.0118 | | D(22) | 5.00 BSC | | | 0.1969 BSC | | D2 | 3.40 | 3.50 | 3.60 | 0.1339 | 0.1378 | 0.1417 | | E(22) | | 5.00 BSC | | 0.1969 BSC | | E2 | 3.40 | 3.50 | 3.60 | 0.1339 | 0.1378 | 0.1417 | | e | | 0.50 BSC | | 0.0197 BSC | | N(27) | 32 | | L(30) | 0.30 | - | 0.50 | 0.0118 | - | 0.0197 | | R | 0.09 | - | - | 0.0035 | - | - |

Table 81. Tolerance of form and position

| Symbol | Millimeters | Inches(23) | |--------|-------------|------------|--|--|--|--|--|--| | aaa | 0.15 | 0.0059 | | bbb | 0.10 | 0.0039 | | ccc | 0.10 | 0.0039 | | ddd | 0.05 | 0.0020 | | eee | 0.08 | 0.0315 | | fff | 0.10 | 0.0039 |

Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2018 except for European.

• 17. UFQFPN stands for ultra-thin fine pitch quad flat package no lead: A ≤ 0.60 mm / Fine pitch e ≤ 1.00 mm.
• 18. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured perpendicular to the seating plane.
• 19. A1 is the vertical distance from the bottom surface of the plastic body to the nearest metallized package feature.
• 1. A3 is the distance from the seating plane to the upper surface of the terminals.
• 21. Dimension b applies to metallized terminal. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
• 22. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance.
• 23. Values in inches are converted from millimeters and rounded to four decimal digits.
• 1. Primary datum C is defined by the plane established by the contact points of three or more solder balls that support the device when it is placed on top of a planar surface.
• 1. Terminal A1 identifier and terminal numbering convention must conform to JEP95 SPP-002. Terminal A1 identifier must be located within the zone indicated on the outline drawing. Topside terminal A1 indicator may be a molded, or metallized feature. Optional indicator on bottom surface may be a molded, marked, or metallized feature.
• 1. ddd coplanarity zone applies to the exposed pad as well as the terminals.
• 27. N represents the total number of terminals.
• 1. K gives the minimum separation between any two terminals or the terminals and the edges of the exposed metal heat feature.
• 1. The inner edge of corner terminals may be chamfered or rounded to achieve minimum gap k. This feature should not affect the terminal width b, which is measured L/2 from the edge of the package body.
• 30. Dimension b and L are measured at the terminal planting surface.

DS12232 Rev 5 123/143

Package information STM32G071x8/xB

Figure 42. UFQFPN32 - Footprint example

1. Dimensions are expressed in millimeters.

6.6 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package.

Note: See list of notes in the notes section.

Figure 43. LQFP48 - Outline⁽¹⁵⁾

Package information STM32G071x8/xB

Table 82. LQFP48 - Mechanical data

| | millimeters | | | inches(14) | |-----------|-------------|----------|------|------------|------------|--------| | Symbol | Min
Typ | | Max | Min | Typ | Max | | A | - | - | 1.60 | - | - | 0.0630 | | A1(12) | 0.05 | - | 0.15 | 0.0020 | - | 0.0059 | | A2 | 1.35 | 1.40 | 1.45 | 0.0531 | 0.0551 | 0.0571 | | b(9)(11) | 0.17 | 0.22 | 0.27 | 0.0067 | 0.0087 | 0.0106 | | b1(11) | 0.17 | 0.20 | 0.23 | 0.0067 | 0.0079 | 0.0090 | | c(11) | 0.09 | - | 0.20 | 0.0035 | - | 0.0079 | | c1(11) | 0.09 | - | 0.16 | 0.0035 | - | 0.0063 | | D(4) | 9.00 BSC | | | | 0.3543 BSC | | D1(2)(5) | | 7.00 BSC | | | 0.2756 BSC | | E(4) | 9.00 BSC | | | 0.3543 BSC | | E1(2)(5) | 7.00 BSC | | | 0.2756 BSC | | e | | 0.50 BSC | | 0.1970 BSC | | L | 0.45 | 0.60 | 0.75 | 0.0177 | 0.0236 | 0.0295 | | L1 | 1.00 REF | | | | 0.0394 REF | | N(13) | | | | 48 | | θ | 0° | 3.5° | 7° | 0° | 3.5° | 7° | | θ1 | 0° | - | - | 0° | - | - | | θ2 | 10° | 12° | 14° | 10° | 12° | 14° | | θ3 | 10° | 12° | 14° | 10° | 12° | 14° | | R1 | 0.08 | - | - | 0.0031 | - | - | | R2 | 0.08 | - | 0.20 | 0.0031 | - | 0.0079 | | S | 0.20 | - | - | 0.0079 | - | - | | aaa(1)(7) | 0.20 | | | | 0.0079 | | bbb(1)(7) | 0.20 | | | | 0.0079 | | ccc(1)(7) | | 0.08 | | 0.0031 | | ddd(1)(7) | | 0.08 | | | 0.0031 |

Notes:

• 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
• 1. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
• 1. Datums A-B and D to be determined at datum plane H.
• 1. To be determined at seating datum plane C.
• 1. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is "0.25 mm" per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
• 1. Details of pin 1 identifier are optional but must be located within the zone indicated.
• 7. All Dimensions are in millimeters.
• 1. No intrusion allowed inwards the leads.
• 1. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
• 1. Exact shape of each corner is optional.
• 1. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
• 1. A1 is defined as the distance from the seating plane to the lowest point on the package body.
• 1. "N" is the number of terminal positions for the specified body size.
• 14. Values in inches are converted from mm and rounded to 4 decimal digits.
• 15. Drawing is not to scale.

12 24 1 37 36 5.80 0.30 ²⁵ 1.20 0.50 48 13 9.70 7.30 9.70 0.20 5B_LQFP48_FP_V1

Figure 44. LQFP48 - Footprint example

1. Dimensions are expressed in millimeters.

Package information STM32G071x8/xB

6.7 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

D1 E1 EXPOSED PAD E2 ^e D2 PIN 1 idenfier BOTTOM VIEW L A A3 FRONT VIEW DETAIL A SEATING PLANE LEADS COPLANARITY ddd C SEATING PLANE A1 A1 A ddd C PIN 1 IDENTIFIER LASER MAKER AREA E D TOP VIEW A0B9_UFQFPN48_ME_V4

Figure 45. UFQFPN48 – Outline

• 1. Drawing is not to scale.
• 1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
• 1. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect and solder this back-side pad to PCB ground.

| | | millimeters | | inches(1) | |--------|-------|-------------|-------|-----------|--------|--------| | Symbol | Min | Typ | Max | Min | Typ | Max | | A | 0.500 | 0.550 | 0.600 | 0.0197 | 0.0217 | 0.0236 | | A1 | 0.000 | 0.020 | 0.050 | 0.0000 | 0.0008 | 0.0020 | | A3 | - | 0.152 | - | - | 0.0060 | - | | b | 0.200 | 0.250 | 0.300 | 0.0079 | 0.0098 | 0.0118 | | D(2) | 6.900 | 7.000 | 7.100 | 0.2717 | 0.2756 | 0.2795 | | D1 | 5.400 | 5.500 | 5.600 | 0.2126 | 0.2165 | 0.2205 | | D2(3) | 5.500 | 5.600 | 5.700 | 0.2165 | 0.2205 | 0.2244 | | E(2) | 6.900 | 7.000 | 7.100 | 0.2717 | 0.2756 | 0.2795 | | E1 | 5.400 | 5.500 | 5.600 | 0.2126 | 0.2165 | 0.2205 | | E2(3) | 5.500 | 5.600 | 5.700 | 0.2165 | 0.2205 | 0.2244 | | e | - | 0.500 | - | - | 0.0197 | - | | L | 0.300 | 0.400 | 0.500 | 0.0118 | 0.0157 | 0.0197 | | ddd | - | - | 0.080 | - | - | 0.0031 |

Table 83. UFQFPN48 – Mechanical data

• 1. Values in inches are converted from mm and rounded to four decimal digits.
• 2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
• 3. Dimensions D2 and E2 are not in accordance with JEDEC.

Figure 46. UFQFPN48 – Footprint example

1. Dimensions are expressed in millimeters.

Package information STM32G071x8/xB

6.8 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.

Note: See list of notes in the notes section.

Figure 47. LQFP64 - Outline⁽¹⁵⁾

Table 84. LQFP64 - Mechanical data

| millimeters | | | inches(14) | |-------------|-----------|--------|------------|------------|--------| | Min | Typ | Max | Min | Typ | Max | | - | - | 1.60 | - | - | 0.0630 | | 0.05 | - | 0.15 | 0.0020 | - | 0.0059 | | 1.35 | 1.40 | 1.45 | 0.0531 | 0.0551 | 0.0570 | | 0.17 | 0.22 | 0.27 | 0.0067 | 0.0087 | 0.0106 | | 0.17 | 0.20 | 0.23 | 0.0067 | 0.0079 | 0.0091 | | 0.09 | - | 0.20 | 0.0035 | - | 0.0079 | | 0.09 | - | 0.16 | 0.0035 | - | 0.0063 | | | 12.00 BSC | | | 0.4724 BSC | | | 10.00 BSC | | | 0.3937 BSC | | 12.00 BSC | | | 0.4724 BSC | | 10.00 BSC | | | 0.3937 BSC | | | 0.50 BSC | | 0.1970 BSC | | 0.45 | 0.60 | 0.75 | 0.0177 | 0.0236 | 0.0295 | | 1.00 REF | | | 0.0394 REF | | 0° | 3.5° | 7° | 0° | 3.5° | 7° | | 0° | - | - | 0° | - | - | | 10° | 12° | 14° | 10° | 12° | 14° | | 10° | 12° | 14° | 10° | 12° | 14° | | 0.08 | - | - | 0.0031 | - | - | | 0.08 | - | 0.20 | 0.0031 | - | 0.0079 | | 0.20 | - | - | 0.0079 | - | - | | 0.20 | | | | 0.0079 | | 0.20 | | 0.0079 | | 0.08 | | | | 0.0031 | | 0.08 | | | | 0.0031 | | | | | | 64 | Package information STM32G071x8/xB

Notes:

• 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
• 1. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
• 1. Datums A-B and D to be determined at datum plane H.
• 1. To be determined at seating datum plane C.
• 1. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is "0.25 mm" per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
• 1. Details of pin 1 identifier are optional but must be located within the zone indicated.
• 1. All Dimensions are in millimeters.
• 1. No intrusion allowed inwards the leads.
• 1. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
• 1. Exact shape of each corner is optional.
• 1. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
• 1. A1 is defined as the distance from the seating plane to the lowest point on the package body.
• 1. "N" is the number of terminal positions for the specified body size.
• 14. Values in inches are converted from mm and rounded to 4 decimal digits.
• 1. Drawing is not to scale.

Figure 48. LQFP64 - Footprint example

1. Dimensions are expressed in millimeters.

6.9 UFBGA64 package information (A019)

This UFBGA is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package.

Note: See list of notes in the notes section.

Figure 49. UFBGA64 – Outline(13) E1

Package information STM32G071x8/xB

Table 85. UFBGA64 – Mechanical data

| | millimeters(1)
Min
Typ
Max | | inches(12) | |---------|-------------------------------------|----------|------------|------------|------------|--------| | Symbol | | | | Min | Typ | Max | | A(2)(3) | - | - | 0.60 | - | - | 0.0236 | | A1(4) | 0.05 | - | - | 0.0020 | - | - | | A2 | - | 0.43 | - | - | 0.0169 | - | | b(5) | 0.23 | 0.28 | 0.33 | 0.0090 | 0.0110 | 0.0130 | | D(6) | | 5.00 BSC | | | 0.1969 BSC | | D1 | 3.50 BSC | | | | 0.1378 BSC | | E | 5.00 BSC | | | | 0.1969 BSC | | E1 | 3.50 BSC | | | 0.1378 BSC | | e(9) | 0.50 BSC | | 0.0197 BSC | | N(11) | 64 | | SD(12) | 0.25 BSC | | 0.0098 BSC | | SE(12) | 0.25 BSC | | | | 0.0098 BSC | | aaa | 0.15 | | | | 0.0059 | | ccc | 0.20 | | 0.0079 | | ddd | 0.08 | | 0.0031 | | eee | 0.15 | | | 0.0059 | | fff | | 0.05 | | | 0.0020 |

Notes:

• 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart European projection.
• 1. UFBGA stands for ultra profile fine pitch ball grid array: 0.5 mm < A ≤ 0.65 mm / fine pitch e < 1.00 mm.
• 3. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured perpendicular to the seating plane.
• 4. A1 is defined as the distance from the seating plane to the lowest point on the package body.
• 5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum C.
• 6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to form and position table. On the drawing these dimensions are framed.
• 1. Primary datum C is defined by the plane established by the contact points of three or more solder balls that support the device when it is placed on top of a planar surface.
• 1. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer, ink or metalized markings, or other feature of package body or

integral heat slug. A distinguish feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

• 9. e represents the solder ball grid pitch.
• 1. N represents the total number of balls on the BGA.
• 1. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the position of the centre ball(s) in the outer row or column of a fully populated matrix.
• 12. Values in inches are converted from mm and rounded to 4 decimal digits.
• 13. Drawing is not to scale.

Figure 50. UFBGA64 – Footprint example

Table 86. UFBGA64 - Example of PCB design rules (0.5 mm pitch BGA)

Dimension	Values
Pitch	0.5 mm
Dpad	0.280 mm
Dsm	0.370 mm typ. (depends on the soldermask registration tolerance)
Stencil opening	0.280 mm
Stencil thickness	Between 0.100 mm and 0.125 mm
Pad trace width	0.100 mm

6.10 Thermal characteristics

The operating junction temperature TJ must never exceed the maximum given in Table 21: General operating conditions.

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:

$$T_J(max) = T_A(max) + P_D(max) \times \Theta_{JA}$$

where:

• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O,
  • PINT is power dissipation contribution from product of IDD and VDD
  • PI/O is power dissipation contribution from output ports where:

$$\mathsf{P}{\mathsf{I}/\mathsf{O}} = \Sigma ; (\mathsf{V}{\mathsf{OL}} \times \mathsf{I}{\mathsf{OL}}) + \Sigma ; ((\mathsf{V}{\mathsf{DDIO1}} - \mathsf{V}{\mathsf{OH}}) \times \mathsf{I}{\mathsf{OH}}),$$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Table 87. Package thermal characteristics

| Symbol | Parameter | Package | Value | Unit | |--------|--------------------|----------|---------|------|----|--| | | | | WLCSP25 | | 75 | | | | UFQFPN28 | 69 | | | | LQFP32 | 63 | | | Thermal resistance | UFQFPN32 | 41 | | ΘJA | junction-ambient | LQFP48 | 64 | °C/W | | | | UFQFPN48 | 31 | | | | LQFP64 | 55 | | | | UFBGA64 | 82 | | | | WLCSP25 | 44 | | | | UFQFPN28 | 39 | | | | LQFP32 | 31 | | | Thermal resistance | UFQFPN32 | 23 | | ΘJB | junction-board | LQFP48 | 31 | °C/W | | | | UFQFPN48 | 15 | | | | LQFP64 | 28 | | | | UFBGA64 | 53 |

Symbol	Parameter	Package	Value	Unit
	Thermal resistance junction-board	WLCSP25	5
		UFQFPN28	21
		LQFP32	15
		UFQFPN32	21
ΘJC		LQFP48	15	°C/W
		UFQFPN48	12
		LQFP64	13
		UFBGA64	21
Table 87. Package thermal characteristics (continued)

6.10.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (still air). Available from www.jedec.org.

6.10.2 Selecting the product temperature range

The temperature range is specified in the ordering information scheme shown in Section 7: Ordering information.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature.

As applications do not commonly use microcontrollers at their maximum power consumption, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range best suits the application.

The following example shows how to calculate the temperature range needed for a given application.

Example:

Assuming the following worst application conditions:

• ambient temperature TA = 50 °C (measured according to JESD51-2)
• IDD = 50 mA; VDD = 3.6 V
• 20 I/Os simultaneously used as output at low level with IOL = 8 mA (VOL= 0.4 V), and
• 8 I/Os simultaneously used as output at low level with IOL = 20 mA (VOL= 1.3 V),

the power consumption from power supply PINT is:

$$P_{INT}$$ = 50 mA × 3.6 V= 118 mW,

the power loss through I/Os PIO is

$$P_{IO} = 20 \times 8 \text{ mA} \times 0.4 \text{ V} + 8 \times 20 \text{ mA} \times 1.3 \text{ V} = 272 \text{ mW},$$

and the total power PD to dissipate is:

$$P_{D} = 180 \text{ mW} + 272 \text{ mW} = 452 \text{ mW}$$

For a package with ΘJA= 65 °C/W, the junction temperature stabilizes at:

$$T_J = 50$$ °C + (65 °C/W × 452 mW) = 50 °C + 29.4 °C = 79.4 °C

As a conclusion, product version with suffix 6 (maximum allowed TJ = 105° C) is sufficient for this application.

If the same application was used in a hot environment with maximum TA greater than 75.5 °C, the junction temperature would exceed 105°C and the product version allowing higher maximum TJ would have to be ordered.

7 Ordering information

xTR = tape and reel packing; x = N ("N" product version), otherwise blank

x˽˽ = tray packing; x = N ("N" product version) or blank

other = 3-character ID incl. custom Flash code and packing information; x = N for "N" product version

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office.

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

STM32G071x8/xB Revision history

9 Revision history

Table 88. Document revision history

Date	Revision	Changes
8-Nov-2018	1	Initial release.
28-Nov-2018	2	Table 19: IINJ(PIN) parameter definition modified; Table 21: VIN parameter definition modified; Table 51: FT_d type added to Ilkg parameter specification, note attached to Ilkg values, and TT_xx modified to TT_a; Table 58: "single ended mode" removed from IDDV(ADC) parameter definition; Table 87: UFBGA64 5x5 mm package ΘJA corrected
06-Mar-2020	3	Cover page updated; Section 2: Description updated; Section 3.3.1: Securable area added; Section 3.7.1: Power supply schemes: corrected minimum VDD and VDDA values; Section 3.14.1: Temperature sensor: "engineering bytes" replaced "System memory"; Section 3.20: Inter-integrated circuit interface (I2C): SMBus and PMBus feature points; Section 3.21: Universal synchronous/asynchronous receiver transmitter (USART): max. speed corrected; Table 12: Note 3 inserted and note 4 modified; Table 18 updated; Table 19: Note 2 removed; Table 21: Redefined VIN for I/Os of other than TT_xx and FT_c type; Table 49: LU class modified from "II" to "II Level A"; Table 52: I/O current condition for relaxed VOL/VOH corrected from 18 mA to 15 mA; section Output driving current corrected accordingly; Table 58: major update; Section 3.12: DMA request multiplexer (DMAMUX) added; Figures with package marking examples corrected.
23-Sep-2021	4	Updated: – Section 2: Description – Section 4: Pinouts, pin description and alternate functions – Replaced "PD version" reference for "N version" reference on Figure 6: STM32G071KxU UFQFPN32 pinout, Figure 4: STM32G071GxU UFQFPN28 pinout, Table 12: Pin assignment and description and Section 7: Ordering information – Section 6: Package information: all subsections were rearranged – Example in Section 6.10.2: Selecting the product temperature range – Footnote 3 on Table 25: Current consumption in Run and Low-power run modes at different die temperatures – Footnote 2 on Table 43: PLL characteristics – VIL line on Table 51: I/O static characteristics – VREFBUF_OUT line on Table 63: VREFBUF characteristics

Revision history STM32G071x8/xB

Table 88. Document revision history (continued)

Cover page updated; Introduction; preamble; modes (OTP added); Updated Section 3.5: Boot modes; Updated Section 3.7.6: VBAT operation; Updated Section 3.14: Analog-to-digital converter (ADC); Updated Table 7: Timer feature comparison; (USART);	Date	Revision	Table 88. Document revision history (continued) Changes
used in Pin assignment and description table; Updated Figure 13: Power supply scheme; Updated Section 5.2: Absolute maximum ratings, with Table 18: Voltage characteristics and Table 19: Current characteristics; 17-Jun-2025 5 General operating conditions, Section : I/O system current consumption, characteristics, Figure 22: I/O AC characteristics definition, Figure 23: Recommended NRST pin protection, Section : Output driving current and Section 5.3.16: Extended interrupt and event controller input (EXTI) (removed IDDA(COMP) medium-speed mode and deglitcher information), diagram - slave mode and CPHA = 1, title of Section : USART (SPI mode) characteristics and Table 74: USART characteristics in SPI mode, added timing diagram in SPI slave mode, updated Table 75: UCPD operating conditions; Updated Section 6: Package information, with added Section 6.1: Device marking, removed corresponding subsections for all packages except for WLCSP25, and added note related to Section 6.5: UFQFPN32 package information (A0B8); Updated Table 87: Package thermal characteristics; Added Section 8: Important security notice.			Added references to the reference manual and errata sheet into Section 1: Added information on standard and alternative pinouts in Section 2: Description Updated Table 2: STM32G071x8/xB device features and peripheral counts; Updated Table 3: Access status versus readout protection level and execution Updated Section 3.21: Universal synchronous/asynchronous receiver transmitter Updated Section 4: Pinouts, pin description and alternate functions (packages ordered from lowest to highest pin count), with Table 11: Terms and symbols In Section 5.3: Operating conditions, all table footnotes "Guaranteed by design" changed to "Specified by design. Not tested in production", updated Table 21: Table 47: EMI characteristics, Section : General input/output characteristics (a note added), Table 52: Output voltage characteristics, title change for Section : Output buffer timing characteristics and Table 53: Non-FT_c I/O output timing Table 52: Output voltage characteristics (maximum driving current), added characteristics, updated Table 58: ADC characteristics, Table 60: ADC accuracy, Figure 24: ADC accuracy characteristics, Figure 25: ADC typical connection diagram, Table 63: VREFBUF characteristics, Table 64: COMP characteristics Figure 27: SPI timing diagram - slave mode and CPHA = 0, Figure 28: SPI timing Figure 32: USART timing diagram in SPI master mode and Figure 33: USART

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