STM32G031K8T6

Part: STM32G031x4/x6/x8

Type: Arm® Cortex®-M0+ 32-bit MCU

Key Specs:

• Core frequency: Up to 64 MHz
• Flash memory: Up to 64 Kbytes
• SRAM: 8 Kbytes
• Voltage range: 1.7 V to 3.6 V
• Operating temperature: -40°C to 85°C/125°C
• ADC: 12-bit, 0.4 μs
• I/Os: Up to 44

Features:

• Core: Arm® 32-bit Cortex®-M0+ CPU
• CRC calculation unit
• Reset and power management: Power-on/Power-down reset (POR/PDR), Programmable Brownout reset (BOR), Programmable voltage detector (PVD), Low-power modes (Sleep, Stop, Standby, Shutdown), VBAT supply for RTC and backup registers
• Clock management: 4 to 48 MHz crystal oscillator, 32 kHz crystal oscillator with calibration, Internal 16 MHz RC with PLL option (±1 %), Internal 32 kHz RC oscillator (±5 %)
• Up to 44 fast I/Os, all mappable on external interrupt vectors, multiple 5 V-tolerant I/Os
• 5-channel DMA controller with flexible mapping
• 12-bit ADC (up to 16 ext. channels), up to 16-bit with hardware oversampling, conversion range: 0 to 3.6V
• 11 timers: one 128 MHz capable 16-bit for advanced motor control, one 32-bit and four 16-bit general-purpose, two low-power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown
• Communication interfaces: Two I2C-bus interfaces (Fastmode Plus, 1 Mbit/s, one supporting SMBus/PMBus and wakeup), Two USARTs (master/slave synchronous SPI, one supporting ISO7816, LIN, IrDA, auto baud rate detection and wakeup), One low-power UART, Two SPIs (32 Mbit/s, 4- to 16-bit programmable bitframe, one multiplexed with I2S)
• Development support: serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK®2 compliant

Applications:

• null

Package:

• UFQFPN48: 7 × 7 mm
• UFQFPN32: 5 × 5 mm
• UFQFPN28: 4 × 4 mm
• LQFP48: 7 × 7 mm
• LQFP32: 7 × 7 mm
• TSSOP20: 6.4 × 4.4 mm
• SO8N: 4.9 × 6 mm
• WLCSP18: 1.86 × 2.14 mm

• Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz
• -40°C to 85°C/125°C operating temperature
• Memories
  • Up to 64 Kbytes of Flash memory
  • 8 Kbytes of SRAM with HW parity check
• CRC calculation unit
• Reset and power management
  • Voltage range: 1.7 V to 3.6 V
  • Power-on/Power-down reset (POR/PDR)
  • Programmable Brownout reset (BOR)
  • Programmable voltage detector (PVD)
  • Low-power modes:
  • Sleep, Stop, Standby, Shutdown
  • VBAT supply for RTC and backup registers
• Clock management
  • 4 to 48 MHz crystal oscillator
  • 32 kHz crystal oscillator with calibration
  • Internal 16 MHz RC with PLL option (±1 %)
  • Internal 32 kHz RC oscillator (±5 %)
• Up to 44 fast I/Os
  • All mappable on external interrupt vectors
  • Multiple 5 V-tolerant I/Os
• 5-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 16 ext. channels)
  • Up to 16-bit with hardware oversampling
  • Conversion range: 0 to 3.6V
• 11 timers (one 128 MHz capable): 16-bit for advanced motor control, one 32-bit and four 16-bit general-purpose, two low-power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown

UFQFPN48 UFQFPN32 UFQFPN28 LQFP48 LQFP32 7 × 7 mm 5 × 5 mm 4 × 4 mm 7 × 7 mm 7 × 7 mm TSSOP20 6.4 × 4.4 mm SO8N 4.9 × 6 mm WLCSP18 1.86 × 2.14 mm

• Communication interfaces
  • Two I2C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
  • Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
  • One low-power UART
  • Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface
• Development support: serial wire debug (SWD)
• 96-bit unique ID

• All packages ECOPACK®2 compliant

Table 1. Device summary

Reference	Part number
STM32G031x4	STM32G031C4, STM32G031K4, STM32G031G4, STM32G031F4, STM32G031J4
STM32G031x6	STM32G031C6, STM32G031K6, STM32G031G6, STM32G031F6, STM32G031J6
STM32G031x8	STM32G031C8, STM32G031K8, STM32G031G8, STM32G031F8, STM32G031Y8

This is information on a product in full production.

Figure 3. STM32G031CxT LQFP48 pinout

Figure 7. STM32G031GxU UFQFPN28 pinout

Figure 9. STM32G031Yx WLCSP18 ballout

Figure 10. STM32G031Jx SO8N pinout

Top view
1: PB7/PB8/PB9/PC14-OSC32_IN 2: VDD/VDDA 3: VSS/VSSA 4: PA0/PA1/PA2/PF2-NRST 8: PB5/PB6/PA14-BOOT0/PA15 7: PA13 6: PA12

Column	Symbol	Definition
Pin name		Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.
	S	Supply pin
Pin type	I	Input only pin
	I/O	Input / output pin
	FT	5 V tolerant I/O
	RST	Bidirectional reset pin with embedded weak pull-up resistor
		Options for FT I/Os
I/O structure	_f	I/O, Fm+ capable
	_a	I/O, with analog switch function
	_e	I/O, with switchable diode to VDD
Note		Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Pin functions	Alternate functions	Functions selected through GPIOx_AFR registers
	Additional functions	Functions directly selected/enabled through peripheral registers

Table 11. Terms and symbols used in Table 12

• SO8N
• 1
• 2
• 3
• 4
• 4
• 4
• 4

Table 12. Pin assignment and description

			Pin
SO8N	WLCSP18	TSSOP20	UFQFPN28
-	-	-	-
-	-	-	-
1	B6	2	1
-	A7	3	2
-	-	-	-
-	-	-	-
2	C7	4	3
3	D6	5	4
-	-	-	-
-	-	-	-
4	E7	6	5
4	E7	7	6
4	C5	8	7
4	E5	9	8
-

Table 12. Pin assignment and description (continued)

SO8N	WLCSP18	TSSOP20	UFQFPN28	LQFP32 / UFQFPN32	LQFP48 / UFQFPN48
-	-	-	-	-	1
-	-	-	-	-	2
1	B6	2	1	2	-
-	A7	3	2	3	3
-	-	-	-	-	4
-	-	-	-	-	5
2	C7	4	3	4	6
3	D6	5	4	5	7
-	-	-	-	-	8
-	-	-	-	-	9
4	E7	6	5	6	10
4	E7	7	6	7	11
4	C5	8	7	8	12
4	E5	9	8	9	13
-	D4	10	9	10	14

Table 12. Pin assignment and description (continued)

• 1
• 4
• 4
• 4
• 4

Table 12. Pin assignment and description (continued)

Pin name	Alternate functions
PC13	TIM1_BK
PC14-OSC32_IN (PC14)	TIM1_BK2
PC14-OSC32_IN (PC14)	TIM1_BK2
PC15-OSC32_OUT (PC15)	OSC32_EN, OSC_EN
VBAT	-
VREF+	-
VDD/VDDA	-
VSS/VSSA	-
PF0-OSC_IN (PF0)	TIM14_CH1
PF1-OSC_OUT (PF1)	OSC_EN
PF2-NRST	MCO
PA0	SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, LPTIM1_OUT
PA1	SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, I2C1_SMBA, EVENTOUT
PA2	SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, LPUART1_TX
PA3	SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX, EVENTOUT

40/117 DS12992 Rev 1 Table 14. Port B alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PB0 SPI1_NSS/ I2S1_WS TIM3_CH3 TIM1_CH2N - - LPTIM1_OUT - - PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - - LPTIM2_IN1 LPUART1_RTS _DE EVENTOUT PB2 - SPI2_MISO - - - LPTIM1_OUT - EVENTOUT PB3 SPI1_SCK/ I2S1_CK TIM1_CH2 TIM2_CH2 - USART1_RTS _DE_CK - - EVENTOUT PB4 SPI1_MISO/ I2S1_MCK TIM3_CH1 - - USART1_CTS TIM17_BKIN - EVENTOUT PB5 SPI1_MOSI/ I2S1_SD TIM3_CH2 TIM16_BKIN - - LPTIM1_IN1 I2C1_SMBA - PB6 USART1_TX TIM1_CH3 TIM16_CH1N - SPI2_MISO LPTIM1_ETR I2C1_SCL EVENTOUT PB7 USART1_RX SPI2_MOSI TIM17_CH1N - - LPTIM1_IN2 I2C1_SDA EVENTOUT PB8 - SPI2_SCK TIM16_CH1 - - - I2C1_SCL EVENTOUT PB9 IR_OUT - TIM17_CH1 - - SPI2_NSS I2C1_SDA EVENTOUT PB10 - LPUART1_RX TIM2_CH3 - - SPI2_SCK I2C2_SCL - PB11 SPI2_MOSI LPUART1_TX TIM2_CH4 - - - I2C2_SDA - PB12 SPI2_NSS LPUART1_RTS _DE TIM1_BKIN - - - - EVENTOUT PB13 SPI2_SCK LPUART1_CTS TIM1_CH1N - - - I2C2_SCL EVENTOUT PB14 SPI2_MISO - TIM1_CH2N - - - I2C2_SDA EVENTOUT PB15 SPI2_MOSI - TIM1_CH3N - - - - EVENTOUT

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Table 15. Port C alternate function mapping

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
PB0	SPI1_NSS/I2S1_WS	TIM3_CH3	TIM1_CH2N	-	-	LPTIM1_OUT	-	-
PB1	TIM14_CH1	TIM3_CH4	TIM1_CH3N	-	-	LPTIM2_IN1	LPUART1_RTS_DE	EVENTOUT
PB2	-	SPI2_MISO	-	-	-	LPTIM1_OUT	-	EVENTOUT
PB3	SPI1_SCK/I2S1_CK	TIM1_CH2	TIM2_CH2	-	USART1_RTS_DE_CK	-	-	EVENTOUT
PB4	SPI1_MISO/I2S1_MICK	TIM3_CH1	-	-	USART1_CTS	TIM17_BKIN	-	EVENTOUT
PB5	SPI1_MOSI/I2S1_SD	TIM3_CH2	TIM16_BKIN	-	-	LPTIM1_IN1	I2C1_SMBA	-
PB6	USART1_TX	TIM1_CH3	TIM16_CH1N	-	SPI2_MISO	LPTIM1_ETR	I2C1_SCL	EVENTOUT
PB7	USART1_RX	SPI2_MOSI	TIM17_CH1N	-	-	LPTIM1_IN2	I2C1_SDA	EVENTOUT
PB8	-	SPI2_SCK	TIM16_CH1	-	-	-	I2C1_SCL	EVENTOUT
PB9	IR_OUT	-	TIM17_CH1	-	-	SPI2_NSS	I2C1_SDA	EVENTOUT
PB10	-	LPUART1_RX	TIM2_CH3	-	-	SPI2_SCK	I2C2_SCL	-
PB11	SPI2_MOSI	LPUART1_TX	TIM2_CH4	-	-	-	I2C2_SDA	-
PB12	SPI2_NSS	LPUART1_RTS_DE	TIM1_BKIN	-	-	-	-	EVENTOUT
PB13	SPI2_SCK	LPUART1_CTS	TIM1_CH1N	-	-	-	I2C2_SCL	EVENTOUT
PB14	SPI2_MISO	-	TIM1_CH2N	-	-	-	I2C2_SDA	EVENTOUT
PB15	SPI2_MOSI	-	TIM1_CH3N	-	-	-	-	EVENTOUT

Table 16. Port D alternate function mapping

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
PB0	SPI1_NSS/I2S1_WS	TIM3_CH3	TIM1_CH2N	-	-	LPTIM1_OUT	-	EVENTOUT
PB1	TIM14_CH1	TIM3_CH4	TIM1_CH3N	-	-	LPTIM2_IN1	LPUART1_RTS _DE	EVENTOUT
PB2	-	SPI2_MISO	-	-	USART1_RTS _DE_CK	LPTIM1_OUT	-	EVENTOUT
PB3	SPI1_SCK/I2S1_CK	TIM1_CH2	TIM2_CH2	-	-	-	-	EVENTOUT
PB4	SPI1_MISO/I2S1_MICK	TIM3_CH1	-	-	USART1_CTS	TIM17_BKIN	-	EVENTOUT
PB5	SPI1_MOSI/I2S1_SD	TIM3_CH2	TIM16_BKIN	-	-	LPTIM1_IN1	I2C1_SMBA	-
PB6	USART1_TX	TIM1_CH3	TIM16_CH1N	-	SPI2_MISO	LPTIM1_ETR	I2C1_SCL	EVENTOUT
PB7	USART1_RX	SPI2_MOSI	TIM17_CH1N	-	-	LPTIM1_IN2	I2C1_SDA	EVENTOUT
PB8	-	SPI2_SCK	TIM16_CH1	-	-	-	I2C1_SCL	EVENTOUT
PB9	IR_OUT	-	TIM17_CH1	-	-	SPI2_NSS	I2C1_SDA	EVENTOUT
PB10	-	LPUART1_RX	TIM2_CH3	-	-	SPI2_SCK	I2C2_SCL	-
PB11	SPI2_MOSI	LPUART1_TX	TIM2_CH4	-	-	-	I2C2_SDA	-
PB12	SPI2_NSS	LPUART1_RTS _DE	TIM1_BKIN	-	-	-	-	EVENTOUT
PB13	SPI2_SCK	LPUART1_CTS	TIM1_CH1N	-	-	-	I2C2_SCL	EVENTOUT
PB14	SPI2_MISO	-	TIM1_CH2N	-	-	-	I2C2_SDA	EVENTOUT
PB15	SPI2_MOSI	-	TIM1_CH3N	-	-	-	-	EVENTOUT

*

Table 17. Port F alternate function mapping

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
PF0	-	-	TIM14_CH1	-	-	-	-	-
PF1	OSC_EN	-	-	-	-	-	-	-
PF2	MCO	-	-	-	-	-	-	-

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

5.1.6 Power supply scheme

Figure 13. Power supply scheme

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

5.1.7 Current consumption measurement

Figure 14. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD - VSS	External supply voltage	-0.3	4.0
VBAT - VSS	External supply voltage	-0.3	4.0
VIN(1)	Input voltage on FT_xx	VSS - 0.3	VDD + 4.0(2)	V
	Input voltage on any other pin	VSS - 0.3	4.0

Table 18. Voltage characteristics

1. Refer to Table 19 for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)(1)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)(1)	100	mA
IIO(PIN)	Output current sunk by any I/O and control pin except FT_f	15	mA
	Output current sunk by any FT_f pin	20	mA
	Output current sourced by any I/O and control pin	15	mA
∑IIO(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	80	mA
	Total output current sourced by sum of all I/Os and control pins(2)	80	mA
IINJ(PIN)(3)	Injected current on a FT_xx pin	-5 / NA(4)	mA
∑	IINJ(PIN)		Total injected current (sum of all I/Os and control pins)(5)

Table 19. Current characteristics

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced within one current group as defined in Table 12: Pin assignment and description.

1. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.

2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	150	°C

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD - VSS	External supply voltage	-0.3	4.0
VBAT - VSS	External supply voltage	-0.3	4.0
VIN(1)	Input voltage on FT_xx	VSS - 0.3	VDD + 4.0(2)	V
	Input voltage on any other pin	VSS - 0.3	4.0

Table 18. Voltage characteristics

1. Refer to Table 19 for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)(1)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)(1)	100	mA
IIO(PIN)	Output current sunk by any I/O and control pin except FT_f	15	mA
	Output current sunk by any FT_f pin	20	mA
	Output current sourced by any I/O and control pin	15	mA
∑IIO(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	80	mA
	Total output current sourced by sum of all I/Os and control pins(2)	80	mA
IINJ(PIN)(3)	Injected current on a FT_xx pin	-5 / NA(4)	mA
∑	IINJ(PIN)		Total injected current (sum of all I/Os and control pins)(5)

Table 19. Current characteristics

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced within one current group as defined in Table 12: Pin assignment and description.

1. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.

2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	150	°C

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	150	°C