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STM32G031K8T6

ARM Cortex-M0+ MCU

The STM32G031K8T6 is a arm cortex-m0+ mcu from STMicroelectronics. View the full STM32G031K8T6 datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Category

ARM Cortex-M0+ MCU

Package

32-LQFP

Key Specifications

ParameterValue
ConnectivityI2C, IrDA, LINbus, SPI, SmartCard, UART/USART
Core ProcessorARM® Cortex®-M0+
Core Size32-Bit
Data ConvertersA/D 18x12b SAR
DigiKey ProgrammableNot Verified
Mounting TypeSurface Mount
Number of I/O30
Operating Temperature-40°C ~ 85°C (TA)
Oscillator TypeExternal, Internal
Package / Case32-LQFP
PeripheralsBrown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
Flash Memory Size64KB (64K x 8)
Program Memory TypeFLASH
RAM Size8K x 8 B
Clock Speed64MHz
Supplier Device Package32-LQFP (7x7)
Supply Voltage1.7V ~ 3.6V

Overview

Part: STM32G031x4/x6/x8

Type: Arm Cortex-M0+ 32-bit MCU

Description: 32-bit Arm Cortex-M0+ MCU operating up to 64 MHz with up to 64 KB Flash, 8 KB SRAM, and a 1.7–3.6 V supply voltage.

Operating Conditions:

  • Supply voltage: 1.7 V to 3.6 V
  • Operating temperature: -40 to 85 °C / -40 to 125 °C
  • Max CPU frequency: 64 MHz
  • ADC conversion range: 0 to 3.6 V

Absolute Maximum Ratings:

  • Max supply voltage (V DD - V SS): 4.0 V
  • Max input voltage (5V tolerant I/O): 5.5 V
  • Max continuous current (I DD): 120 mA
  • Max continuous current (per I/O): 25 mA
  • Max junction temperature: 125 °C
  • Max storage temperature: 150 °C

Key Specs:

  • Core: Arm 32-bit Cortex-M0+ CPU
  • Flash memory: Up to 64 Kbytes
  • SRAM: 8 Kbytes with HW parity check
  • ADC resolution: 12-bit
  • ADC conversion time: 0.4 μs
  • I/Os: Up to 44 fast I/Os, multiple 5 V-tolerant
  • I2C speed: Up to 1 Mbit/s (Fastmode Plus)
  • SPI speed: Up to 32 Mbit/s

Features:

  • CRC calculation unit
  • Power-on/Power-down reset (POR/PDR)
  • Programmable Brownout reset (BOR)
  • Low-power modes: Sleep, Stop, Standby, Shutdown
  • VBAT supply for RTC and backup registers
  • 5-channel DMA controller with flexible mapping
  • 11 timers (one 128 MHz capable)
  • Calendar RTC with alarm and periodic wakeup
  • 96-bit unique ID

Package:

  • LQFP48
  • UFQFPN48
  • LQFP32
  • UFQFPN32
  • UFQFPN28
  • TSSOP20
  • WLCSP18
  • SO8N

Features

  • Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 64 MHz
  • -40°C to 85°C/125°C operating temperature
  • Memories
  • -Up to 64 Kbytes of Flash memory
  • -8 Kbytes of SRAM with HW parity check
  • CRC calculation unit
  • Reset and power management
  • -Voltage range: 1.7 V to 3.6 V
  • -Power-on/Power-down reset (POR/PDR)
  • -Programmable Brownout reset (BOR)
  • -Programmable voltage detector (PVD)
  • -Low-power modes: Sleep, Stop, Standby, Shutdown
  • -VBAT supply for RTC and backup registers
  • Clock management
  • -4 to 48 MHz crystal oscillator
  • -32 kHz crystal oscillator with calibration
  • -Internal 16 MHz RC with PLL option (±1 %)
  • -Internal 32 kHz RC oscillator (±5 %)
  • Up to 44 fast I/Os
  • -All mappable on external interrupt vectors
  • -Multiple 5 V-tolerant I/Os
  • 5-channel DMA controller with flexible mapping
  • 12-bit, 0.4 μs ADC (up to 16 ext. channels)
  • -Up to 16-bit with hardware oversampling
  • -Conversion range: 0 to 3.6V
  • 11 timers (one 128 MHz capable): 16-bit for advanced motor control, one 32-bit and four 16-bit general-purpose, two low-power 16-bit, two watchdogs, SysTick timer
  • Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown

Pin Configuration

Figure 3. STM32G031CxT LQFP48 pinout

Figure 4. STM32G031CxU UFQFPN48 pinout

38

Figure 5. STM32G031KxT LQFP32 pinout

Figure 6. STM32G031KxU UFQFPN32 pinout

Figure 7. STM32G031GxU UFQFPN28 pinout

Figure 8. STM32G031Fx TSSOP20 pinout

Figure 9. STM32G031Yx WLCSP18 ballout

38

Figure 10. STM32G031Jx SO8N pinout

MSv47956V1

1

2

3

4

8

7

  • 6 PA12[PA10]

5

PB7/PB8/PB9/PC14-OSC32_IN

PA0/PA1/PA2/PF2-NRST

PB5/PB6/PA14-BOOT0/PA15

PA13

VDD/VDDA

VSS/VSSA

PA8/PA11[PA9]/PB0/PB1

Top view

Table 11. Terms and symbols used in Table 12

Table 11. Terms and symbols used in Table 12

ColumnColumnSymbolDefinition
Pin namePin nameTerminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.
SSupply pin
typeIInput only pin
I/OInput / output pin
FT5 V tolerant I/O
RSTBidirectional reset pin with embedded weak pull-up resistor
Options for FT I/OsOptions for FT I/Os
structure_fI/O, Fm+ capable
_aI/O, with analog switch function
_eI/O, with switchable diode to V DD
Upon reset, all I/Os are set as analog inputs, unless otherwise specified.Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Alternate functionsFunctions selected through GPIOx_AFR registersFunctions selected through GPIOx_AFR registers
Additional functionsFunctions directly selected/enabled through peripheral registersFunctions directly selected/enabled through peripheral registers

Table 11. Terms and symbols used in Table 12

Table 12. Pin assignment and description

PinPinPinPinPinPin
SO8NWLCSP18TSSOP20UFQFPN28LQFP32 / UFQFPN32LQFP48 / UFQFPN48
-----1
-----2
1B6212-
-A73233
-----4
-----5
2C74346
3D65457
-----8
-----9
4E765610
4E776711
4C587812
4E598913
-D41091014

Table 12. Pin assignment and description

38

Table 12. Pin assignment and description (continued)

PinPinPinPinPinPin
SO8NWLCSP18TSSOP20UFQFPN28LQFP32 / UFQFPN32LQFP48 / UFQFPN48
-----15
-D4111011-
-C312111216
-E313121317
-D214131418
5E115141519
5E115151620
-E115-1721
-----22
-----23
-----24
-----25
-----26

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

PinPinPinPinPinPin
SO8NWLCSP18TSSOP20UFQFPN28LQFP32 / UFQFPN32LQFP48 / UFQFPN48
-----27
5E115161828
----1929
---172030
-----31
----2132
-----33
5C1161822-
-----34
6B2171923-
7A118202435
8A319212536
8A319222637
-----38
-----39

Table 12. Pin assignment and description (continued)

38

Table 12. Pin assignment and description (continued)

PinPinPinPinPinPinAdditional
SO8NWLCSP18TSSOP20UFQFPN28LQFP32 / UFQFPN32LQFP48 / UFQFPN48Pin name (function upon reset)Pin typeI/O structureCurrent groupNoteAlternate functionsfunctions
-----40PD2I/OFTN-TIM3_ETR, TIM1_CH1N-
-----41PD3I/OFTN-USART2_CTS, SPI2_MISO, TIM1_CH2N-
-B420232742PB3I/OFTN-SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK, EVENTOUT-
-B420242843PB4I/OFTN-SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BK, EVENTOUT-
8B420252944PB5I/OFTN-SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BK, LPTIM1_IN1, I2C1_SMBAWKUP6
8B420263045PB6I/OFT_fN-USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT-
-----46PB7I/OFT_fN-USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA, EVENTOUTPVD_IN
1A512731-PB7I/OFT_faN-USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA, EVENTOUTADC_IN11, PVD_IN
1A51283247PB8I/OFT_fN-SPI2_SCK, TIM16_CH1, I2C1_SCL, EVENTOUT-
1B62-148PB9I/OFT_fN-IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA, EVENTOUT-

Table 12. Pin assignment and description (continued)

Table 13. Port A alternate function mapping

PortAF0AF1AF2AF3AF4AF5AF6AF7
PA0SPI2_SCKUSART2_CTSTIM2_CH1_ETR--LPTIM1_OUT--
PA1SPI1_SCK/ I2S1_CKUSART2_RTS _DE_CKTIM2_CH2---I2C1_SMBAEVENTOUT
PA2SPI1_MOSI/ I2S1_SDUSART2_TXTIM2_CH3---LPUART1_TX-
PA3SPI2_MISOUSART2_RXTIM2_CH4---LPUART1_RXEVENTOUT
PA4SPI1_NSS/ I2S1_WSSPI2_MOSI--TIM14_CH1LPTIM2_OUT-EVENTOUT
PA5SPI1_SCK/ I2S1_CK-TIM2_CH1_ETR--LPTIM2_ETR-EVENTOUT
PA6SPI1_MISO/ I2S1_MCKTIM3_CH1TIM1_BKIN--TIM16_CH1LPUART1_CTS-
PA7SPI1_MOSI/ I2S1_SDTIM3_CH2TIM1_CH1N-TIM14_CH1TIM17_CH1--
PA8MCOSPI2_NSSTIM1_CH1--LPTIM2_OUT-EVENTOUT
PA9MCOUSART1_TXTIM1_CH2-SPI2_MISO-I2C1_SCLEVENTOUT
PA10SPI2_MOSIUSART1_RXTIM1_CH3--TIM17_BKINI2C1_SDAEVENTOUT
PA11SPI1_MISO/ I2S1_MCKUSART1_CTSTIM1_CH4--TIM1_BKIN2I2C2_SCL-
PA12SPI1_MOSI/ I2S1_SDUSART1_RTS _DE_CKTIM1_ETR--I2S_CKINI2C2_SDA-
PA13SWDIOIR_OUT-----EVENTOUT
PA14SWCLKUSART2_TX-----EVENTOUT
PA15SPI1_NSS/ I2S1_WSUSART2_RXTIM2_CH1_ETR----EVENTOUT

Table 13. Port A alternate function mapping

Table 14. Port B alternate function mapping

PortAF0AF1AF2AF3AF4AF5AF6AF7
PB0SPI1_NSS/ I2S1_WSTIM3_CH3TIM1_CH2N--LPTIM1_OUT--
PB1TIM14_CH1TIM3_CH4TIM1_CH3N--LPTIM2_IN1LPUART1_RTS _DEEVENTOUT
PB2-SPI2_MISO---LPTIM1_OUT-EVENTOUT
PB3SPI1_SCK/ I2S1_CKTIM1_CH2TIM2_CH2-USART1_RTS _DE_CK--EVENTOUT
PB4SPI1_MISO/ I2S1_MCKTIM3_CH1--USART1_CTSTIM17_BKIN-EVENTOUT
PB5SPI1_MOSI/ I2S1_SDTIM3_CH2TIM16_BKIN--LPTIM1_IN1I2C1_SMBA-
PB6USART1_TXTIM1_CH3TIM16_CH1N-SPI2_MISOLPTIM1_ETRI2C1_SCLEVENTOUT
PB7USART1_RXSPI2_MOSITIM17_CH1N--LPTIM1_IN2I2C1_SDAEVENTOUT
PB8-SPI2_SCKTIM16_CH1---I2C1_SCLEVENTOUT
PB9IR_OUT-TIM17_CH1--SPI2_NSSI2C1_SDAEVENTOUT
PB10-LPUART1_RXTIM2_CH3--SPI2_SCKI2C2_SCL-
PB11SPI2_MOSILPUART1_TXTIM2_CH4---I2C2_SDA-
PB12SPI2_NSSLPUART1_RTS _DETIM1_BKIN----EVENTOUT
PB13SPI2_SCKLPUART1_CTSTIM1_CH1N---I2C2_SCLEVENTOUT
PB14SPI2_MISO-TIM1_CH2N---I2C2_SDAEVENTOUT
PB15SPI2_MOSI-TIM1_CH3N----EVENTOUT

Table 14. Port B alternate function mapping

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 23 and Table 54 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions .

Table 54. I/O AC characteristics (1)(2)

SpeedSymbolParameterConditionsMinMaxUnit
00FmaxMaximum frequencyC=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-2MHz
00FmaxMaximum frequencyC=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-0.35MHz
00FmaxMaximum frequencyC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-3MHz
00FmaxMaximum frequencyC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-0.45MHz
00Tr/TfOutput rise and fall timeC=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-100ns
00Tr/TfOutput rise and fall timeC=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-225ns
00Tr/TfOutput rise and fall timeC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-75ns
00Tr/TfOutput rise and fall timeC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-150ns

Table 54. I/O AC characteristics (1)(2)

Table 54. I/O AC characteristics (1)(2) (continued)

SpeedParameterConditionsMinMaxUnit
01C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-10MHz
01Maximum frequencyC=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-2MHz
01C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-15MHz
01C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-2.5MHz
01Tr/Tf Output rise and fallC=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-30ns
01timeC=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-60ns
01Tr/Tf Output rise and fallC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-15ns
01Tr/Tf Output rise and fallC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-30ns
10Fmax Maximum frequencyC=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-30MHz
10Fmax Maximum frequencyC=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-15MHz
10Fmax Maximum frequencyC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-60MHz
10Fmax Maximum frequencyC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-30MHz
10Tr/Tf Output rise and fallC=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-11ns
10timeC=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-22ns
10Tr/Tf Output rise and fallC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-4ns
10Tr/Tf Output rise and fallC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-8ns
11Fmax Maximum frequencyC=30 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-60MHz
11Fmax Maximum frequencyC=30 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-30MHz
11Fmax Maximum frequencyC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-80 (3)MHz
11Fmax Maximum frequencyC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-40MHz
11Tr/Tf Output rise and fallC=30 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-5.5ns
11timeC=30 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-11ns
11Tr/Tf Output rise and fallC=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V-2.5ns
11Tr/Tf Output rise and fallC=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V-5ns
Fm+Maximum frequencyC=50 pF, 1.6 V ≤ V DDIO1 ≤ 3.6 V-1MHz
Fm+Output fall time (4)C=50 pF, 1.6 V ≤ V DDIO1 ≤ 3.6 V-5ns
  1. Guaranteed by design.
  2. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.
  3. The fall time is defined between 70% and 30% of the output waveform, according to I 2 C specification.

92

Figure 23. I/O AC characteristics definition (1)

  1. Refer to Table 54: I/O AC characteristics .

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 18 , Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 18. Voltage characteristics

SymbolRatingsMinMaxUnit
V DD - V SS V BAT - V SSExternal supply voltage-0.34.0
V IN (1)Input voltage on FT_xxV SS - 0.3V DD + 4.0 (2)V
V IN (1)Input voltage on any other pinV SS - 0.34.0
SymbolRatingsMaxUnit
I VDD/VDDACurrent into VDD/VDDA power pin (source) (1)100mA
I VSS/VSSACurrent out of VSS/VSSA ground pin (sink) (1)100mA
I IO(PIN)Output current sunk by any I/O and control pin except FT_f15mA
I IO(PIN)Output current sunk by any FT_f pin20mA
I IO(PIN)Output current sourced by any I/O and control pin15mA
∑ I IO(PIN)Total output current sunk by sum of all I/Os and control pins (2)80mA
∑ I IO(PIN)Total output current sourced by sum of all I/Os and control pins (2)80mA
I INJ(PIN) (3)Injected current on a FT_xx pin-5 / NA (4)mA
∑ \I INJ(PIN) \Total injected current (sum of all I/Os and control pins) (5)
  1. A positive injection is induced by V IN > V DDIOx while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
  2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  3. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

Table 20. Thermal characteristics

Thermal Information

The operating junction temperature T J must never exceed the maximum given in Table 21: General operating conditions

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
STM32G031K8STMicroelectronics
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