STM32G031K8
The STM32G031K8 is an electronic component from STMicroelectronics. View the full STM32G031K8 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Overview
Part: STM32G031x4/x6/x8
Type: Arm Cortex-M0+ 32-bit MCU
Description: 32-bit Arm Cortex-M0+ MCU operating up to 64 MHz with up to 64 KB Flash, 8 KB SRAM, and a 1.7–3.6 V supply voltage.
Operating Conditions:
- Supply voltage: 1.7 V to 3.6 V
- Operating temperature: -40 to 85 °C / -40 to 125 °C
- Max CPU frequency: 64 MHz
- ADC conversion range: 0 to 3.6 V
Absolute Maximum Ratings:
- Max supply voltage (V DD - V SS): 4.0 V
- Max input voltage (5V tolerant I/O): 5.5 V
- Max continuous current (I DD): 120 mA
- Max continuous current (per I/O): 25 mA
- Max junction temperature: 125 °C
- Max storage temperature: 150 °C
Key Specs:
- Core: Arm 32-bit Cortex-M0+ CPU
- Flash memory: Up to 64 Kbytes
- SRAM: 8 Kbytes with HW parity check
- ADC resolution: 12-bit
- ADC conversion time: 0.4 μs
- I/Os: Up to 44 fast I/Os, multiple 5 V-tolerant
- I2C speed: Up to 1 Mbit/s (Fastmode Plus)
- SPI speed: Up to 32 Mbit/s
Features:
- CRC calculation unit
- Power-on/Power-down reset (POR/PDR)
- Programmable Brownout reset (BOR)
- Low-power modes: Sleep, Stop, Standby, Shutdown
- VBAT supply for RTC and backup registers
- 5-channel DMA controller with flexible mapping
- 11 timers (one 128 MHz capable)
- Calendar RTC with alarm and periodic wakeup
- 96-bit unique ID
Package:
- LQFP48
- UFQFPN48
- LQFP32
- UFQFPN32
- UFQFPN28
- TSSOP20
- WLCSP18
- SO8N
Features
- Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 64 MHz
- -40°C to 85°C/125°C operating temperature
- Memories
- -Up to 64 Kbytes of Flash memory
- -8 Kbytes of SRAM with HW parity check
- CRC calculation unit
- Reset and power management
- -Voltage range: 1.7 V to 3.6 V
- -Power-on/Power-down reset (POR/PDR)
- -Programmable Brownout reset (BOR)
- -Programmable voltage detector (PVD)
- -Low-power modes: Sleep, Stop, Standby, Shutdown
- -VBAT supply for RTC and backup registers
- Clock management
- -4 to 48 MHz crystal oscillator
- -32 kHz crystal oscillator with calibration
- -Internal 16 MHz RC with PLL option (±1 %)
- -Internal 32 kHz RC oscillator (±5 %)
- Up to 44 fast I/Os
- -All mappable on external interrupt vectors
- -Multiple 5 V-tolerant I/Os
- 5-channel DMA controller with flexible mapping
- 12-bit, 0.4 μs ADC (up to 16 ext. channels)
- -Up to 16-bit with hardware oversampling
- -Conversion range: 0 to 3.6V
- 11 timers (one 128 MHz capable): 16-bit for advanced motor control, one 32-bit and four 16-bit general-purpose, two low-power 16-bit, two watchdogs, SysTick timer
- Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown
Pin Configuration
Figure 3. STM32G031CxT LQFP48 pinout
Figure 4. STM32G031CxU UFQFPN48 pinout
38
Figure 5. STM32G031KxT LQFP32 pinout
Figure 6. STM32G031KxU UFQFPN32 pinout
Figure 7. STM32G031GxU UFQFPN28 pinout
Figure 8. STM32G031Fx TSSOP20 pinout
Figure 9. STM32G031Yx WLCSP18 ballout
38
Figure 10. STM32G031Jx SO8N pinout
MSv47956V1
1
2
3
4
8
7
- 6 PA12[PA10]
5
PB7/PB8/PB9/PC14-OSC32_IN
PA0/PA1/PA2/PF2-NRST
PB5/PB6/PA14-BOOT0/PA15
PA13
VDD/VDDA
VSS/VSSA
PA8/PA11[PA9]/PB0/PB1
Top view
Table 11. Terms and symbols used in Table 12
Table 11. Terms and symbols used in Table 12
| Column | Column | Symbol | Definition |
|---|---|---|---|
| Pin name | Pin name | Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name. | Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name. |
| S | Supply pin | ||
| type | I | Input only pin | |
| I/O | Input / output pin | ||
| FT | 5 V tolerant I/O | ||
| RST | Bidirectional reset pin with embedded weak pull-up resistor | ||
| Options for FT I/Os | Options for FT I/Os | ||
| structure | _f | I/O, Fm+ capable | |
| _a | I/O, with analog switch function | ||
| _e | I/O, with switchable diode to V DD | ||
| Upon reset, all I/Os are set as analog inputs, unless otherwise specified. | Upon reset, all I/Os are set as analog inputs, unless otherwise specified. | ||
| Alternate functions | Functions selected through GPIOx_AFR registers | Functions selected through GPIOx_AFR registers | |
| Additional functions | Functions directly selected/enabled through peripheral registers | Functions directly selected/enabled through peripheral registers |
Table 11. Terms and symbols used in Table 12
Table 12. Pin assignment and description
| Pin | Pin | Pin | Pin | Pin | Pin |
|---|---|---|---|---|---|
| SO8N | WLCSP18 | TSSOP20 | UFQFPN28 | LQFP32 / UFQFPN32 | LQFP48 / UFQFPN48 |
| - | - | - | - | - | 1 |
| - | - | - | - | - | 2 |
| 1 | B6 | 2 | 1 | 2 | - |
| - | A7 | 3 | 2 | 3 | 3 |
| - | - | - | - | - | 4 |
| - | - | - | - | - | 5 |
| 2 | C7 | 4 | 3 | 4 | 6 |
| 3 | D6 | 5 | 4 | 5 | 7 |
| - | - | - | - | - | 8 |
| - | - | - | - | - | 9 |
| 4 | E7 | 6 | 5 | 6 | 10 |
| 4 | E7 | 7 | 6 | 7 | 11 |
| 4 | C5 | 8 | 7 | 8 | 12 |
| 4 | E5 | 9 | 8 | 9 | 13 |
| - | D4 | 10 | 9 | 10 | 14 |
Table 12. Pin assignment and description
38
Table 12. Pin assignment and description (continued)
| Pin | Pin | Pin | Pin | Pin | Pin |
|---|---|---|---|---|---|
| SO8N | WLCSP18 | TSSOP20 | UFQFPN28 | LQFP32 / UFQFPN32 | LQFP48 / UFQFPN48 |
| - | - | - | - | - | 15 |
| - | D4 | 11 | 10 | 11 | - |
| - | C3 | 12 | 11 | 12 | 16 |
| - | E3 | 13 | 12 | 13 | 17 |
| - | D2 | 14 | 13 | 14 | 18 |
| 5 | E1 | 15 | 14 | 15 | 19 |
| 5 | E1 | 15 | 15 | 16 | 20 |
| - | E1 | 15 | - | 17 | 21 |
| - | - | - | - | - | 22 |
| - | - | - | - | - | 23 |
| - | - | - | - | - | 24 |
| - | - | - | - | - | 25 |
| - | - | - | - | - | 26 |
Table 12. Pin assignment and description (continued)
Table 12. Pin assignment and description (continued)
| Pin | Pin | Pin | Pin | Pin | Pin |
|---|---|---|---|---|---|
| SO8N | WLCSP18 | TSSOP20 | UFQFPN28 | LQFP32 / UFQFPN32 | LQFP48 / UFQFPN48 |
| - | - | - | - | - | 27 |
| 5 | E1 | 15 | 16 | 18 | 28 |
| - | - | - | - | 19 | 29 |
| - | - | - | 17 | 20 | 30 |
| - | - | - | - | - | 31 |
| - | - | - | - | 21 | 32 |
| - | - | - | - | - | 33 |
| 5 | C1 | 16 | 18 | 22 | - |
| - | - | - | - | - | 34 |
| 6 | B2 | 17 | 19 | 23 | - |
| 7 | A1 | 18 | 20 | 24 | 35 |
| 8 | A3 | 19 | 21 | 25 | 36 |
| 8 | A3 | 19 | 22 | 26 | 37 |
| - | - | - | - | - | 38 |
| - | - | - | - | - | 39 |
Table 12. Pin assignment and description (continued)
38
Table 12. Pin assignment and description (continued)
| Pin | Pin | Pin | Pin | Pin | Pin | Additional | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SO8N | WLCSP18 | TSSOP20 | UFQFPN28 | LQFP32 / UFQFPN32 | LQFP48 / UFQFPN48 | Pin name (function upon reset) | Pin type | I/O structure | Current group | Note | Alternate functions | functions |
| - | - | - | - | - | 40 | PD2 | I/O | FT | N | - | TIM3_ETR, TIM1_CH1N | - |
| - | - | - | - | - | 41 | PD3 | I/O | FT | N | - | USART2_CTS, SPI2_MISO, TIM1_CH2N | - |
| - | B4 | 20 | 23 | 27 | 42 | PB3 | I/O | FT | N | - | SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK, EVENTOUT | - |
| - | B4 | 20 | 24 | 28 | 43 | PB4 | I/O | FT | N | - | SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BK, EVENTOUT | - |
| 8 | B4 | 20 | 25 | 29 | 44 | PB5 | I/O | FT | N | - | SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BK, LPTIM1_IN1, I2C1_SMBA | WKUP6 |
| 8 | B4 | 20 | 26 | 30 | 45 | PB6 | I/O | FT_f | N | - | USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT | - |
| - | - | - | - | - | 46 | PB7 | I/O | FT_f | N | - | USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA, EVENTOUT | PVD_IN |
| 1 | A5 | 1 | 27 | 31 | - | PB7 | I/O | FT_fa | N | - | USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA, EVENTOUT | ADC_IN11, PVD_IN |
| 1 | A5 | 1 | 28 | 32 | 47 | PB8 | I/O | FT_f | N | - | SPI2_SCK, TIM16_CH1, I2C1_SCL, EVENTOUT | - |
| 1 | B6 | 2 | - | 1 | 48 | PB9 | I/O | FT_f | N | - | IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA, EVENTOUT | - |
Table 12. Pin assignment and description (continued)
Table 13. Port A alternate function mapping
| Port | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PA0 | SPI2_SCK | USART2_CTS | TIM2_CH1_ETR | - | - | LPTIM1_OUT | - | - |
| PA1 | SPI1_SCK/ I2S1_CK | USART2_RTS _DE_CK | TIM2_CH2 | - | - | - | I2C1_SMBA | EVENTOUT |
| PA2 | SPI1_MOSI/ I2S1_SD | USART2_TX | TIM2_CH3 | - | - | - | LPUART1_TX | - |
| PA3 | SPI2_MISO | USART2_RX | TIM2_CH4 | - | - | - | LPUART1_RX | EVENTOUT |
| PA4 | SPI1_NSS/ I2S1_WS | SPI2_MOSI | - | - | TIM14_CH1 | LPTIM2_OUT | - | EVENTOUT |
| PA5 | SPI1_SCK/ I2S1_CK | - | TIM2_CH1_ETR | - | - | LPTIM2_ETR | - | EVENTOUT |
| PA6 | SPI1_MISO/ I2S1_MCK | TIM3_CH1 | TIM1_BKIN | - | - | TIM16_CH1 | LPUART1_CTS | - |
| PA7 | SPI1_MOSI/ I2S1_SD | TIM3_CH2 | TIM1_CH1N | - | TIM14_CH1 | TIM17_CH1 | - | - |
| PA8 | MCO | SPI2_NSS | TIM1_CH1 | - | - | LPTIM2_OUT | - | EVENTOUT |
| PA9 | MCO | USART1_TX | TIM1_CH2 | - | SPI2_MISO | - | I2C1_SCL | EVENTOUT |
| PA10 | SPI2_MOSI | USART1_RX | TIM1_CH3 | - | - | TIM17_BKIN | I2C1_SDA | EVENTOUT |
| PA11 | SPI1_MISO/ I2S1_MCK | USART1_CTS | TIM1_CH4 | - | - | TIM1_BKIN2 | I2C2_SCL | - |
| PA12 | SPI1_MOSI/ I2S1_SD | USART1_RTS _DE_CK | TIM1_ETR | - | - | I2S_CKIN | I2C2_SDA | - |
| PA13 | SWDIO | IR_OUT | - | - | - | - | - | EVENTOUT |
| PA14 | SWCLK | USART2_TX | - | - | - | - | - | EVENTOUT |
| PA15 | SPI1_NSS/ I2S1_WS | USART2_RX | TIM2_CH1_ETR | - | - | - | - | EVENTOUT |
Table 13. Port A alternate function mapping
Table 14. Port B alternate function mapping
| Port | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PB0 | SPI1_NSS/ I2S1_WS | TIM3_CH3 | TIM1_CH2N | - | - | LPTIM1_OUT | - | - |
| PB1 | TIM14_CH1 | TIM3_CH4 | TIM1_CH3N | - | - | LPTIM2_IN1 | LPUART1_RTS _DE | EVENTOUT |
| PB2 | - | SPI2_MISO | - | - | - | LPTIM1_OUT | - | EVENTOUT |
| PB3 | SPI1_SCK/ I2S1_CK | TIM1_CH2 | TIM2_CH2 | - | USART1_RTS _DE_CK | - | - | EVENTOUT |
| PB4 | SPI1_MISO/ I2S1_MCK | TIM3_CH1 | - | - | USART1_CTS | TIM17_BKIN | - | EVENTOUT |
| PB5 | SPI1_MOSI/ I2S1_SD | TIM3_CH2 | TIM16_BKIN | - | - | LPTIM1_IN1 | I2C1_SMBA | - |
| PB6 | USART1_TX | TIM1_CH3 | TIM16_CH1N | - | SPI2_MISO | LPTIM1_ETR | I2C1_SCL | EVENTOUT |
| PB7 | USART1_RX | SPI2_MOSI | TIM17_CH1N | - | - | LPTIM1_IN2 | I2C1_SDA | EVENTOUT |
| PB8 | - | SPI2_SCK | TIM16_CH1 | - | - | - | I2C1_SCL | EVENTOUT |
| PB9 | IR_OUT | - | TIM17_CH1 | - | - | SPI2_NSS | I2C1_SDA | EVENTOUT |
| PB10 | - | LPUART1_RX | TIM2_CH3 | - | - | SPI2_SCK | I2C2_SCL | - |
| PB11 | SPI2_MOSI | LPUART1_TX | TIM2_CH4 | - | - | - | I2C2_SDA | - |
| PB12 | SPI2_NSS | LPUART1_RTS _DE | TIM1_BKIN | - | - | - | - | EVENTOUT |
| PB13 | SPI2_SCK | LPUART1_CTS | TIM1_CH1N | - | - | - | I2C2_SCL | EVENTOUT |
| PB14 | SPI2_MISO | - | TIM1_CH2N | - | - | - | I2C2_SDA | EVENTOUT |
| PB15 | SPI2_MOSI | - | TIM1_CH3N | - | - | - | - | EVENTOUT |
Table 14. Port B alternate function mapping
Electrical Characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and Table 54 , respectively.
Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions .
Table 54. I/O AC characteristics (1)(2)
| Speed | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| 00 | Fmax | Maximum frequency | C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 2 | MHz |
| 00 | Fmax | Maximum frequency | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 0.35 | MHz |
| 00 | Fmax | Maximum frequency | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 3 | MHz |
| 00 | Fmax | Maximum frequency | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 0.45 | MHz |
| 00 | Tr/Tf | Output rise and fall time | C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 100 | ns |
| 00 | Tr/Tf | Output rise and fall time | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 225 | ns |
| 00 | Tr/Tf | Output rise and fall time | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 75 | ns |
| 00 | Tr/Tf | Output rise and fall time | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 150 | ns |
Table 54. I/O AC characteristics (1)(2)
Table 54. I/O AC characteristics (1)(2) (continued)
| Speed | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| 01 | C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 10 | MHz | |
| 01 | Maximum frequency | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 2 | MHz |
| 01 | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 15 | MHz | |
| 01 | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 2.5 | MHz | |
| 01 | Tr/Tf Output rise and fall | C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 30 | ns |
| 01 | time | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 60 | ns |
| 01 | Tr/Tf Output rise and fall | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 15 | ns |
| 01 | Tr/Tf Output rise and fall | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 30 | ns |
| 10 | Fmax Maximum frequency | C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 30 | MHz |
| 10 | Fmax Maximum frequency | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 15 | MHz |
| 10 | Fmax Maximum frequency | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 60 | MHz |
| 10 | Fmax Maximum frequency | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 30 | MHz |
| 10 | Tr/Tf Output rise and fall | C=50 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 11 | ns |
| 10 | time | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 22 | ns |
| 10 | Tr/Tf Output rise and fall | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 4 | ns |
| 10 | Tr/Tf Output rise and fall | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 8 | ns |
| 11 | Fmax Maximum frequency | C=30 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 60 | MHz |
| 11 | Fmax Maximum frequency | C=30 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 30 | MHz |
| 11 | Fmax Maximum frequency | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 80 (3) | MHz |
| 11 | Fmax Maximum frequency | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 40 | MHz |
| 11 | Tr/Tf Output rise and fall | C=30 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 5.5 | ns |
| 11 | time | C=30 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 11 | ns |
| 11 | Tr/Tf Output rise and fall | C=10 pF, 2.7 V ≤ V DDIO1 ≤ 3.6 V | - | 2.5 | ns |
| 11 | Tr/Tf Output rise and fall | C=10 pF, 1.6 V ≤ V DDIO1 ≤ 2.7 V | - | 5 | ns |
| Fm+ | Maximum frequency | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 3.6 V | - | 1 | MHz |
| Fm+ | Output fall time (4) | C=50 pF, 1.6 V ≤ V DDIO1 ≤ 3.6 V | - | 5 | ns |
- Guaranteed by design.
- This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.
- The fall time is defined between 70% and 30% of the output waveform, according to I 2 C specification.
92
Figure 23. I/O AC characteristics definition (1)
- Refer to Table 54: I/O AC characteristics .
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 18 , Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 18. Voltage characteristics
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DD - V SS V BAT - V SS | External supply voltage | -0.3 | 4.0 | |
| V IN (1) | Input voltage on FT_xx | V SS - 0.3 | V DD + 4.0 (2) | V |
| V IN (1) | Input voltage on any other pin | V SS - 0.3 | 4.0 |
| Symbol | Ratings | Max | Unit |
|---|---|---|---|
| I VDD/VDDA | Current into VDD/VDDA power pin (source) (1) | 100 | mA |
| I VSS/VSSA | Current out of VSS/VSSA ground pin (sink) (1) | 100 | mA |
| I IO(PIN) | Output current sunk by any I/O and control pin except FT_f | 15 | mA |
| I IO(PIN) | Output current sunk by any FT_f pin | 20 | mA |
| I IO(PIN) | Output current sourced by any I/O and control pin | 15 | mA |
| ∑ I IO(PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 80 | mA |
| ∑ I IO(PIN) | Total output current sourced by sum of all I/Os and control pins (2) | 80 | mA |
| I INJ(PIN) (3) | Injected current on a FT_xx pin | -5 / NA (4) | mA |
| ∑ \ | I INJ(PIN) \ | Total injected current (sum of all I/Os and control pins) (5) |
- A positive injection is induced by V IN > V DDIOx while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).
Table 20. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 150 | °C |
Table 20. Thermal characteristics
Thermal Information
The operating junction temperature T J must never exceed the maximum given in Table 21: General operating conditions
The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32G031K8T6 | STMicroelectronics | 32-LQFP |
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