STM32F401XB/C
The STM32F401XB/C is an electronic component from STMicroelectronics. View the full STM32F401XB/C datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Overview
Part: STM32F401xB STM32F401xC
Type: ARM Cortex-M4 32-bit MCU
Description: 32-bit ARM Cortex-M4 MCU with FPU, operating at up to 84 MHz, featuring up to 256 KB Flash, up to 64 KB SRAM, 11 timers, 1 ADC, and 11 communication interfaces.
Operating Conditions:
- Supply voltage: 1.7 V to 3.6 V
- Operating temperature: -40 to 125 °C
- Max CPU frequency: 84 MHz
Absolute Maximum Ratings:
- Max supply voltage: 4.0 V
- Max junction/storage temperature: 150 °C
Key Specs:
- Core: ARM 32-bit Cortex-M4 CPU with FPU
- Max CPU Frequency: 84 MHz
- Flash Memory: Up to 256 Kbytes
- SRAM Memory: Up to 64 Kbytes
- ADC: 1x 12-bit, 2.4 MSPS, up to 16 channels
- I/O Ports: Up to 81, 5 V tolerant
- Run mode current: 128 μA/MHz (peripheral off)
- Standby mode current: 2.4 μA @25 °C / 1.7 V (without RTC)
Features:
- Adaptive real-time accelerator (ART Accelerator™)
- USB 2.0 full-speed device/host/OTG controller with on-chip PHY
- Up to 81 5 V tolerant I/O ports
- Serial wire debug (SWD) & JTAG interfaces
- CRC calculation unit
- 96-bit unique ID
Applications:
Package:
- WLCSP49
- UFQFPN48
- LQFP64
- LQFP100
- UFBGA100
Features
- Dynamic efficiency line with BAM (batch acquisition mode)
- -1.7 V to 3.6 V power supply
- --40 °C to 85/105/125 °C temperature range
- Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 84 MHz, memory protection unit, 105 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Memories
- -Up to 256 Kbytes of Flash memory
- -512 bytes of OTP memory
- -Up to 64 Kbytes of SRAM
- Clock, reset and supply management
- -1.7 V to 3.6 V application supply and I/Os
- -POR, PDR, PVD and BOR
- -4-to-26 MHz crystal oscillator
- -Internal 16 MHz factory-trimmed RC
- -32 kHz oscillator for RTC with calibration
- -Internal 32 kHz RC with calibration
- Power consumption
- -Run: 128 μA/MHz (peripheral off)
- -Stop (Flash in Stop mode, fast wakeup time): 42 μA typ @ 25 °C; 65 μA max @25 °C
- -Stop (Flash in Deep power down mode, slow wakeup time): down to 10 μA typ@ 25 °C; 28 μA max @25 °C
- -Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V
- -VBAT supply for RTC: 1 μA @25 °C
- 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
- General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
- Up to 11 timers: up to six 16-bit, two 32-bit timers up to 84 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature
April 2019
| Reference | Part number |
|---|---|
| STM32F401xB | STM32F401CB, STM32F401RB, STM32F401VB |
| STM32F401xC | STM32F401CC, STM32F401RC, STM32F401VC |
DS9716 Rev 11
Pin Configuration
Figure 10. STM32F401xB/STM32F401xC WLCSP49 pinout
- The above figure shows the package top view.
Figure 11. STM32F401xB/STM32F401xC UFQFPN48 pinout
Figure 11. STM32F401xB/STM32F401xC UFQFPN48 pinout
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Figure 12. STM32F401xB/STM32F401xC LQFP64 pinout
- The above figure shows the package top view.
Figure 13. STM32F401xB/STM32F401xC LQFP100 pinout
Figure 13. STM32F401xB/STM32F401xC LQFP100 pinout
- The above figure shows the package top view.
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Figure 14. STM32F401xB/STM32F401xC UFBGA100 pinout
- This figure shows the package top view
06 9
Table 7. Legend/abbreviations used in the pinout table
| Name | Abbreviation | Definition |
|---|---|---|
| Pin name | Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name | Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name |
| Pin type | S | Supply pin |
| Pin type | I | Input only pin |
| Pin type | I/O | Input/ output pin |
| I/O structure | FT | 5 V tolerant I/O |
| I/O structure | B | Dedicated BOOT0 pin |
| I/O structure | NRST | Bidirectional reset pin with embedded weak pull-up resistor |
| Notes | Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset | Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset |
| Alternate functions | Functions selected through GPIOx_AFR registers | Functions selected through GPIOx_AFR registers |
| Additional functions | Functions directly selected/enabled through peripheral registers | Functions directly selected/enabled through peripheral registers |
Table 8. STM32F401xB/STM32F401xC pin definitions
| Pin Number | Pin Number | Pin Number | Pin Number | Pin Number | Pin name (function (1) |
|---|---|---|---|---|---|
| UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | after reset) |
| - | - | - | 1 | B2 | PE2 |
| - | - | - | 2 | A1 | PE3 |
| - | - | - | 3 | B1 | PE4 |
| - | - | - | 4 | C2 | PE5 |
| - | - | - | 5 | D2 | PE6 |
| - | - | - | - | D3 | VSS |
| - | - | - | - | C4 | VDD |
| 1 | B7 | 1 | 6 | E2 | VBAT |
| 2 | D5 | 2 | 7 | C1 | PC13 |
Table 8. STM32F401xB/STM32F401xC pin definitions
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Electrical Characteristics
The definition and values of input/output AC characteristics are given in Figure 31 and Table 56 , respectively.
Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .
Table 56. I/O AC characteristics (1)(2)
| OSPEEDRy [1:0] bit value (1) | Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|---|
| 00 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DD ≥ 2.70 V | - | - | 4 | MHz |
| 00 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DD ≥ 1.7 V | - | - | 2 | MHz |
| 00 | f max(IO)out | Maximum frequency (3) | C L = 10 pF, V DD ≥ 2.70 V | - | - | 8 | MHz |
| 00 | f max(IO)out | Maximum frequency (3) | C L = 10 pF, V DD ≥ 1.7 V | - | - | 4 | MHz |
| 00 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high level rise time | C L = 50 pF, V DD = 1.7 V to 3.6 V | - | - | 100 | ns |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DD ≥ 2.70 V | - | - | 25 | MHz |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DD ≥ 1.7 V | - | - | 12.5 | MHz |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 10 pF, V DD ≥ 2.70 V | - | - | 50 | MHz |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 10 pF, V DD ≥ 1.7 V | - | - | 20 | MHz |
| 01 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high | C L = 50 pF, V DD ≥ 2.7 V | - | - | 10 | ns |
| 01 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high | C L = 50 pF, V DD ≥ 1.7 V | - | - | 20 | ns |
| 01 | t f(IO)out / t r(IO)out | level rise time | C L = 10 pF, V DD ≥ 2.70 V | - | - | 6 | ns |
| 01 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high | C L = 10 pF, V DD ≥ 1.7 V | - | - | 10 | |
| 10 | f max(IO)out | C L = 40 pF, V DD ≥ 2.70 V | - | - | 50 (4) | MHz | |
| 10 | f max(IO)out | (3) | C L = 40 pF, V DD ≥ 1.7 V | - | - | 25 | MHz |
| 10 | f max(IO)out | Maximum frequency | C L = 10 pF, V DD ≥ 2.70 V | - | - | 100 (4) | MHz |
| 10 | f max(IO)out | C L = 10 pF, V DD ≥ 1.7 V | - | - | 50 (4) | MHz | |
| 10 | t f(IO)out / t r(IO)out | Output high to low level fall | C L = 40 pF, V DD ≥ 2.70 V | - | - | 6 | ns |
| 10 | t f(IO)out / t r(IO)out | Output high to low level fall | C L = 40 pF, V DD ≥ 1.7 V | - | - | 10 | ns |
| 10 | t f(IO)out / t r(IO)out | time and output low to high level rise time | C L = 10 pF, V DD ≥ 2.70 V | - | - | 4 | ns |
| 10 | t f(IO)out / t r(IO)out | Output high to low level fall | C L = 10 pF, V DD ≥ 1.7 V | - | - | 6 | ns |
| 11 | F max(IO)out | Maximum frequency (3) | C L = 30 pF, V DD ≥ 2.70 V | - | - | 100 (4) | MHz |
| 11 | F max(IO)out | Maximum frequency (3) | C L = 30 pF, V DD ≥ 1.7 V | - | - | 50 (4) | MHz |
| 11 | F max(IO)out | Maximum frequency (3) | C L = 10 pF, V DD ≥ 2.70 V | - | - | 180 (4) | MHz |
| 11 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high | C L = 10 pF, V DD ≥ 1.7 V C = 30 pF, V ≥ 2.70 V | - | - | 100 (4) 4 | ns |
| 11 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high | L DD C L = 30 pF, V DD ≥ 1.7 V | - - | - - | 6 | ns |
| 11 | t f(IO)out / t r(IO)out | level rise time | C L = 10 pF, V DD ≥ 2.70 V | - | - | 2.5 | ns |
| 11 | t f(IO)out / t r(IO)out | Output high to low level fall time and output low to high | C L = 10 pF, V DD ≥ 1.7 V | - | - | 4 | ns |
| - | t EXTIpw | Pulse width of external signals detected by the EXTI controller | - | 10 | - | - | ns |
Table 56. I/O AC characteristics (1)(2)
113
- Guaranteed by characterization.
- The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOxSPEEDR GPIO port output speed register.
- The maximum frequency is defined in Figure 31 .
- For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.
Figure 31. I/O AC characteristics definition
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand.
Table 11. Voltage characteristics
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DD -V SS | External main supply voltage (including V DDA ,V DD and V BAT ) (1) | -0.3 | 4.0 | |
| Input voltage on FT pins (2) | V SS -0.3 | V DD +4.0 | V | |
| V IN | Input voltage on any other pin | V SS -0.3 | 4.0 | |
| Input voltage for BOOT0 | V SS | 9.0 | ||
| | ∆ V DDx | | Variations between different V DD power pins | - | 50 | |
| |V SSX - V SS | | Variations between all the different ground pins including V REF- | - | 50 | mV |
| V ESD(HBM) | Electrostatic discharge voltage (human body model) | see Section 6.3.14 | see Section 6.3.14 | - |
113
Table 12. Current characteristics
| Symbol | Ratings | Max. | Unit |
|---|---|---|---|
| Σ I VDD | Total current into sum of all V DD_x power lines (source) (1) | 160 | mA |
| Σ I VSS | Total current out of sum of all V SS_x ground lines (sink) (1) | -160 | mA |
| I VDD | Maximum current into each V DD_x power line (source) (1) | 100 | mA |
| I VSS | Maximum current out of each V SS_x ground line (sink) (1) | -100 | mA |
| I IO | Output current sunk by any I/O and control pin | 25 | mA |
| I IO | Output current sourced by any I/O and control pin | -25 | mA |
| Σ I IO | Total output current sunk by sum of all I/O and control pins (2) | 120 | mA |
| Σ I IO | Total output current sourced by sum of all I/Os and control pins (2) | -120 | mA |
| I INJ(PIN) (3) | Injected current on FT pins (4) | -5/+0 | mA |
| I INJ(PIN) (3) | Injected current on NRST and B pins (4) | -5/+0 | mA |
| Σ I INJ(PIN) | Total injected current (sum of all I/O and control pins) (5) | ±25 | mA |
- Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics .
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).
Table 13. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 130 | °C |
| T LEAD | Maximum lead temperature during soldering (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100) | See note (1) | °C |
Table 13. Thermal characteristics
Thermal Information
The maximum chip junction temperature (T J max) must never exceed the values given in Table 14: General operating conditions on page 59 .
The maximum chip-junction temperature, T J max., in degrees Celsius, may be calculated using the following equation:
T J max = T A max + (PD max x Θ JA )
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32F401CB | STMicroelectronics | — |
| STM32F401CC | STMicroelectronics | — |
| STM32F401CCU6 | STMicroelectronics | — |
| STM32F401RB | STMicroelectronics | — |
| STM32F401RC | STMicroelectronics | — |
| STM32F401VB | STMicroelectronics | — |
| STM32F401VC | STMicroelectronics | — |
| STM32F401X | STMicroelectronics | — |
| STM32F401XB | STMicroelectronics | — |
| STM32F401XC | STMicroelectronics | — |
| STM32F401XE | STMicroelectronics | — |
| STM32F401XX | STMicroelectronics | — |
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