STM32F401CCU6

Arm<sup>®</sup> Cortex<sup>®</sup>-M4 32-bit MCU+FPU, 105 DMIPS, 256KB Flash / 64KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces

Manufacturer

STMicroelectronics

Overview

Part: STM32F401xB STM32F401xC

Type: ARM Cortex-M4 32-bit MCU+FPU

Key Specs:

  • Core Frequency: Up to 84 MHz
  • Performance: 105 DMIPS
  • Flash Memory: Up to 256 Kbytes
  • SRAM: Up to 64 Kbytes
  • Operating Voltage: 1.7 V to 3.6 V
  • Operating Temperature: -40 °C to 85/105/125 °C
  • ADC: 1x 12-bit, 2.4 MSPS, up to 16 channels
  • Timers: Up to 11 (six 16-bit, two 32-bit, two watchdog, SysTick)

Features:

  • Dynamic efficiency line with BAM (batch acquisition mode)
  • ART Accelerator™ allowing 0-wait state execution from Flash memory
  • Memory protection unit
  • 512 bytes of OTP memory
  • POR, PDR, PVD and BOR
  • 4-to-26 MHz crystal oscillator
  • Internal 16 MHz factory-trimmed RC
  • 32 kHz oscillator for RTC with calibration
  • Internal 32 kHz RC with calibration
  • Run mode power consumption: 128 μA/MHz (peripheral off)
  • Stop mode power consumption: 42 μA typ @ 25 °C (Flash in Stop mode)
  • Standby mode power consumption: 2.4 μA @25 °C / 1.7 V without RTC
  • VBAT supply for RTC power consumption: 1 μA @25 °C
  • General-purpose DMA: 16-stream controllers with FIFOs and burst support
  • Debug mode: Serial wire debug (SWD) & JTAG interfaces, Cortex®-M4 Embedded Trace Macrocell™
  • Up to 81 I/O ports with interrupt capability
  • All IO ports 5 V tolerant
  • Up to 78 fast I/Os up to 42 MHz
  • Up to 3 I²C interfaces (1Mbit/s, SMBus/PMBus)
  • Up to 3 USARTs (2 x 10.5 Mbit/s, 1 x 5.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control
  • Up to 4 SPIs (up to 42 Mbits/s at fCPU = 84 MHz), SPI2 and SPI3 with muxed full-duplex I²S
  • SDIO interface
  • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar
  • All packages are ECOPACK2

Applications:

  • null

Package:

  • null
{

Features

  • Dynamic efficiency line with BAM (batch acquisition mode)
    • 1.7 V to 3.6 V power supply
    • -40 °C to 85/105/125 °C temperature range
  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 84 MHz, memory protection unit, 105 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
    • Up to 256 Kbytes of Flash memory
    • 512 bytes of OTP memory
    • Up to 64 Kbytes of SRAM
  • · Clock, reset and supply management
    • 1.7 V to 3.6 V application supply and I/Os
    • POR, PDR, PVD and BOR
    • 4-to-26 MHz crystal oscillator
    • Internal 16 MHz factory-trimmed RC
    • 32 kHz oscillator for RTC with calibration
    • Internal 32 kHz RC with calibration
  • Power consumption
    • Run: 128 μA/MHz (peripheral off)
    • Stop (Flash in Stop mode, fast wakeup time): 42 μA typ @ 25 °C; 65 μA max @25 °C
    • Stop (Flash in Deep power down mode, slow wakeup time): down to 10 μA typ@ 25 °C; 28 μA max @25 °C
    • Standby: 2.4 $\mu A$ @25 $^{\circ}C$ / 1.7 V without RTC; 12 $\mu A$ @85 $^{\circ}C$ @1.7 V
    • VBAT supply for RTC: 1 μA @25 °C
  • 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
  • General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
  • Up to 11 timers: up to six 16-bit, two 32-bit timers up to 84 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input, two watchdog timers (independent and window) and a SysTick timer

  • Debug mode
    • Serial wire debug (SWD) & JTAG interfaces
    • Cortex®-M4 Embedded Trace Macrocell™
  • Up to 81 I/O ports with interrupt capability
    • All IO ports 5 V tolerant
    • Up to 78 fast I/Os up to 42 MHz
  • Up to 11 communication interfaces
    • Up to 3 × I2C interfaces (1Mbit/s, SMBus/PMBus)
    • Up to 3 USARTs (2 x 10.5 Mbit/s, 1 x 5.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control)
    • Up to 4 SPIs (up to 42 Mbits/s at fCPU = 84 MHz), SPI2 and SPI3 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
    • SDIO interface
  • Advanced connectivity
    • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • · CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar
  • All packages are ECOPACK2

Table 1. Device summary

ReferencePart number
STM32F401xBSTM32F401CB, STM32F401RB,
STM32F401VB
STM32F401xCSTM32F401CC, STM32F401RC,
STM32F401VC

Pin Configuration

Figure 10. STM32F401xB/STM32F401xC WLCSP49 pinout

Figure 11. STM32F401xB/STM32F401xC UFQFPN48 pinout

Figure 12. STM32F401xB/STM32F401xC LQFP64 pinout

U VDD VSS V U VSS V U PE0 V U PE0 V U PB4 V U PB5 V U PB5 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U PD7 V U 000 989 987 997 997 998 998 998 998 998 998 75 UVDD 74 UVSS 73 UVCAP_2 72 UPA13 71 UPA12 70 UPA11 69 UPA10 68 UPA9 67 UPA8 66 UPC9 65 UPC8 PE2 1 PE3 🗆 2 PE4口 PE5 4 5 PE6 🗆 VBAT 🗆 PC13 PC14-OSC32_IN D 7 PC15-OSC32_OUT = 9 VSS ☐ 10 VDD 🗖 11 PH0-OSC_INE 12 PH1-OSC_OUT 13 64 PC7 63 PC6 LQFP100 62 PD15 61 PD14 NRST 🗆 14 PC0 🗖 15 PC1 ☐ 16 60 PD13 59 | PD12 58 | PD11 57 | PD10 56 | PD9 PC2 🗖 17 PC3 🗖 18 VDD d 19 VSSA/VREF- ☐ 20 55 | PD9 55 | PD8 54 | PB15 53 | PB14 52 | PB13 51 | PB12 VREF+ 21 VDDA [ 22 PA0 [ 23 PA1 [ 24 PA2 🗖 25 $\begin{array}{cccccccccccccccccccccccccccccccccccc$ VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 022 VSS 02 MS31151V4

Figure 13. STM32F401xB/STM32F401xC LQFP100 pinout

Figure 14. STM32F401xB/STM32F401xC UFBGA100 pinout

| | | | | | | Figure 14. STM32F401xB/STM32F401xC UFBGA100 pinout | |---------|-------------------|-------------|--------|-------------|----|----------------------------------------------------|----|----|-----|-----|------------|-----| | | 3( | 3( | 3% | %227 | 3' | 3' | 3% | 3% | 3$ | 3$ | 3$ | 3$ | | $
% | 3( | 3( | 3% | 3% | 3% | 3' | 3' | 3' | 3' | 3& | 3& | 3$ | | & | 3&
$17,B7$03 | 3( | 3( | 9'' | 3% | | | 3' | 3' | 3& | 9&$3
B | 3$ | | ' | 3&
26&B,1 | 3( | 966 | | | | | | | 3$ | 3$ | 3& | | ( | 3&
26&B287 | 9%$7 | | %<3$66B5(* | | | | | | 3& | 3& | 3& | | ) | 3+
26&B,1 | 966 | | | | | | | | | 966 | 966 | | * | 3+
26&B287 | 9'' | | | | | | | | | 9'' | 9'' | | + | 3& | 1567 | 3'5B21 | | | | | | | 3' | 3' | 3' | | - | 966$ | 3& | 3& | | | | | | | 3' | 3' | 3' | | | 95() | 3& | 3$ | 3$ | 3& | | | 3' | 3% | 3% | 3% | 3% | | / | 95() | 3$
:.83 | 3$ | 3$ | 3& | 3% | 3( | 3( | 3( | 3% | 9&$3
B | 3% | | 0 | 9''$ | 3$ | 3$ | 3$ | 3% | 3% | 3( | 3( | 3( | 3( | 3( | 3( |

1. This figure shows the package top view

069

Table 7. Legend/abbreviations used in the pinout table

NameAbbreviationDefinition
Pin nameUnless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
SSupply pin
Pin typeIInput only pin
I/OInput/ output pin
FT5 V tolerant I/O
BDedicated BOOT0 pin
I/O structureNRSTBidirectional reset pin with embedded weak pull-up resistor
NotesUnless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions		Functions selected through GPIOx_AFR registers
Additional
functions		Functions directly selected/enabled through peripheral registers

Table 8. STM32F401xB/STM32F401xC pin definitions

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|---------|-------------------------------------------|-------------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 1 | B2 | PE2 | I/O | FT | - | SPI4_SCK, TRACECLK,
EVENTOUT | - | | - | - | - | 2 | A1 | PE3 | I/O | FT | - | TRACED0, EVENTOUT | - | | - | - | - | 3 | B1 | PE4 | I/O | FT | - | SPI4_NSS, TRACED1,
EVENTOUT | - | | - | - | - | 4 | C2 | PE5 | I/O | FT | - | SPI4_MISO, TIM9_CH1,
TRACED2, EVENTOUT | - | | - | - | - | 5 | D2 | PE6 | I/O | FT | - | SPI4_MOSI, TIM9_CH2,
TRACED3, EVENTOUT | - | | - | - | - | - | D3 | VSS | S | - | - | - | - | | - | - | - | - | C4 | VDD | S | - | - | - | - | | 1 | B7 | 1 | 6 | E2 | VBAT | S | - | - | - | - | | 2 | D5 | 2 | 7 | C1 | PC13 | I/O | FT | (2) (3) | EVENTOUT, | RTC_TAMP1,
RTC_OUT, RTC_TS |

Table 8. STM32F401xB/STM32F401xC pin definitions (continued)

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|----------------|---------------------------------------------------------|-------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | 3 | C7 | 3 | 8 | D1 | PC14-
OSC32_IN
(PC14) | I/O | FT | (2) (3)
(4) | EVENTOUT | OSC32_IN | | 4 | C6 | 4 | 9 | E1 | PC15-
OSC32_OUT
(PC15) | I/O | FT | (2) (3)
(4) | EVENTOUT | OSC32_OUT | | - | - | - | 10 | F2 | VSS | S | - | - | - | - | | - | - | - | 11 | G2 | VDD | S | - | - | - | - | | 5 | D7 | 5 | 12 | F1 | PH0-OSC_IN
(PH0) | I/O | FT | (4) | EVENTOUT | OSC_IN | | 6 | D6 | 6 | 13 | G1 | PH1-
OSC_OUT
(PH1) | I/O | FT | (4) | EVENTOUT | OSC_OUT | | 7 | E7 | 7 | 14 | H2 | NRST | I/O | FT | - | EVENTOUT | - | | - | - | 8 | 15 | H1 | PC0 | I/O | FT | - | EVENTOUT | ADC1_IN10 | | - | - | 9 | 16 | J2 | PC1 | I/O | FT | - | EVENTOUT | ADC1_IN11 | | - | - | 10 | 17 | J3 | PC2 | I/O | FT | - | SPI2_MISO, I2S2ext_SD,
EVENTOUT | ADC1_IN12 | | - | - | 11 | 18 | K2 | PC3 | I/O | FT | - | SPI2_MOSI/I2S2_SD,
EVENTOUT | ADC1_IN13 | | - | - | - | 19 | - | VDD | S | - | - | - | - | | 8 | E6 | 12 | 20 | - | VSSA/VREF- | S | - | - | - | - | | - | - | - | - | J1 | VSSA | S | - | - | - | - | | - | - | - | - | K1 | VREF- | S | - | - | - | - | | 9 | - | 13 | - | - | VDDA/VREF+ | S | - | - | - | - | | - | - | - | 21 | L1 | VREF+ | S | - | - | - | - | | - | F7 | - | 22 | M1 | VDDA | S | - | - | - | - | | 10 | F6 | 14 | 23 | L2 | PA0 | I/O | FT | (5) | USART2_CTS,
TIM2_CH1/TIM2_ETR,
TIM5_CH1, EVENTOUT | ADC1_IN0, WKUP | | 11 | G7 | 15 | 24 | M2 | PA1 | I/O | FT | - | USART2_RTS, TIM2_CH2,
TIM5_CH2, EVENTOUT | ADC1_IN1 | | 12 | E5 | 16 | 25 | K3 | PA2 | I/O | FT | - | USART2_TX, TIM2_CH3,
TIM5_CH3, TIM9_CH1,
EVENTOUT | ADC1_IN2 |

Table 8. STM32F401xB/STM32F401xC pin definitions (continued)

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|-------|---------------------------------------------------------|-------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | 13 | E4 | 17 | 26 | L3 | PA3 | I/O | FT | - | USART2_RX, TIM2_CH4,
TIM5_CH4, TIM9_CH2,
EVENTOUT | ADC1_IN3 | | - | - | 18 | 27 | - | VSS | S | - | - | - | - | | - | - | 19 | 28 | - | VDD | S | - | - | - | - | | - | - | - | - | E3 | BYPASS_
REG | I | FT | - | - | - | | 14 | G6 | 20 | 29 | M3 | PA4 | I/O | FT | - | SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK, EVENTOUT | ADC1_IN4 | | 15 | F5 | 21 | 30 | K4 | PA5 | I/O | FT | - | SPI1_SCK,
TIM2_CH1/TIM2_ETR,
EVENTOUT | ADC1_IN5 | | 16 | F4 | 22 | 31 | L4 | PA6 | I/O | FT | - | SPI1_MISO, TIM1_BKIN,
TIM3_CH1, EVENTOUT | ADC1_IN6 | | 17 | F3 | 23 | 32 | M4 | PA7 | I/O | FT | - | SPI1_MOSI, TIM1_CH1N,
TIM3_CH2, EVENTOUT | ADC1_IN7 | | - | - | 24 | 33 | K5 | PC4 | I/O | FT | - | EVENTOUT | ADC1_IN14 | | - | - | 25 | 34 | L5 | PC5 | I/O | FT | - | EVENTOUT | ADC1_IN15 | | 18 | G5 | 26 | 35 | M5 | PB0 | I/O | FT | - | TIM1_CH2N, TIM3_CH3,
EVENTOUT | ADC1_IN8 | | 19 | G4 | 27 | 36 | M6 | PB1 | I/O | FT | - | TIM1_CH3N, TIM3_CH4,
EVENTOUT | ADC1_IN9 | | 20 | G3 | 28 | 37 | L6 | PB2 | I/O | FT | - | EVENTOUT | BOOT1 | | - | - | - | 38 | M7 | PE7 | I/O | FT | - | TIM1_ETR, EVENTOUT | - | | - | - | - | 39 | L7 | PE8 | I/O | FT | - | TIM1_CH1N, EVENTOUT | - | | - | - | - | 40 | M8 | PE9 | I/O | FT | - | TIM1_CH1, EVENTOUT | - | | - | - | - | 41 | L8 | PE10 | I/O | FT | - | TIM1_CH2N, EVENTOUT | - | | - | - | - | 42 | M9 | PE11 | I/O | FT | - | SPI4_NSS, TIM1_CH2,
EVENTOUT | - | | - | - | - | 43 | L9 | PE12 | I/O | FT | - | SPI4_SCK, TIM1_CH3N,
EVENTOUT | - | | - | - | - | 44 | M10 | PE13 | I/O | FT | - | SPI4_MISO, TIM1_CH3,
EVENTOUT | - |

Table 8. STM32F401xB/STM32F401xC pin definitions (continued)

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|-------|--------------------------------------------------------|-------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 45 | M11 | PE14 | I/O | FT | - | SPI4_MOSI, TIM1_CH4,
EVENTOUT | - | | - | - | - | 46 | M12 | PE15 | I/O | FT | - | TIM1_BKIN, EVENTOUT | - | | 21 | E3 | 29 | 47 | L10 | PB10 | I/O | FT | - | SPI2_SCK/I2S2_CK,
I2C2_SCL, TIM2_CH3,
EVENTOUT | - | | - | - | - | - | K9 | PB11 | I/O | FT | - | TIM2_CH4, I2C2_SDA,
EVENTOUT | - | | 22 | G2 | 30 | 48 | L11 | VCAP_1 | S | - | - | - | - | | 23 | D3 | 31 | 49 | F12 | VSS | S | - | - | - | - | | 24 | F2 | 32 | 50 | G12 | VDD | S | - | - | - | - | | 25 | E2 | 33 | 51 | L12 | PB12 | I/O | FT | - | SPI2_NSS/I2S2_WS,
I2C2_SMBA, TIM1_BKIN,
EVENTOUT | - | | 26 | G1 | 34 | 52 | K12 | PB13 | I/O | FT | - | SPI2_SCK/I2S2_CK,
TIM1_CH1N, EVENTOUT | - | | 27 | F1 | 35 | 53 | K11 | PB14 | I/O | FT | - | SPI2_MISO, I2S2ext_SD,
TIM1_CH2N, EVENTOUT | - | | 28 | E1 | 36 | 54 | K10 | PB15 | I/O | FT | - | SPI2_MOSI/I2S2_SD,
TIM1_CH3N, EVENTOUT | RTC_REFIN | | - | - | - | 55 | - | PD8 | I/O | FT | - | EVENTOUT | - | | - | - | - | 56 | K8 | PD9 | I/O | FT | - | EVENTOUT | - | | - | - | - | 57 | J12 | PD10 | I/O | FT | - | EVENTOUT | - | | - | - | - | 58 | J11 | PD11 | I/O | FT | - | EVENTOUT | - | | - | - | - | 59 | J10 | PD12 | I/O | FT | - | TIM4_CH1, EVENTOUT | - | | - | - | - | 60 | H12 | PD13 | I/O | FT | - | TIM4_CH2, EVENTOUT | - | | - | - | - | 61 | H11 | PD14 | I/O | FT | - | TIM4_CH3, EVENTOUT | - | | - | - | - | 62 | H10 | PD15 | I/O | FT | - | TIM4_CH4, EVENTOUT | - | | - | - | 37 | 63 | E12 | PC6 | I/O | FT | - | I2S2_MCK, USART6_TX,
TIM3_CH1, SDIO_D6,
EVENTOUT | - | | - | - | 38 | 64 | E11 | PC7 | I/O | FT | - | I2S3_MCK, USART6_RX,
TIM3_CH2, SDIO_D7,
EVENTOUT | - |

Table 8. STM32F401xB/STM32F401xC pin definitions (continued)

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|-------|------------------------------------------------------------------------------|-------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | 39 | 65 | E10 | PC8 | I/O | FT | - | USART6_CK, TIM3_CH3,
SDIO_D0, EVENTOUT | - | | - | - | 40 | 66 | D12 | PC9 | I/O | FT | - | I2S_CKIN, I2C3_SDA,
TIM3_CH4, SDIO_D1,
MCO_2, EVENTOUT | - | | 29 | D1 | 41 | 67 | D11 | PA8 | I/O | FT | - | I2C3_SCL, USART1_CK,
TIM1_CH1, OTG_FS_SOF,
MCO_1, EVENTOUT | - | | 30 | D2 | 42 | 68 | D10 | PA9 | I/O | FT | - | I2C3_SMBA, USART1_TX,
TIM1_CH2, EVENTOUT | OTG_FS_VBUS | | 31 | C2 | 43 | 69 | C12 | PA10 | I/O | FT | - | USART1_RX, TIM1_CH3,
OTG_FS_ID, EVENTOUT | - | | 32 | C1 | 44 | 70 | B12 | PA11 | I/O | FT | - | USART1_CTS, USART6_TX,
TIM1_CH4, OTG_FS_DM,
EVENTOUT | - | | 33 | C3 | 45 | 71 | A12 | PA12 | I/O | FT | - | USART1_RTS, USART6_RX,
TIM1_ETR, OTG_FS_DP,
EVENTOUT | - | | 34 | B3 | 46 | 72 | A11 | PA13 (JTMS
SWDIO) | I/O | FT | - | JTMS-SWDIO, EVENTOUT | - | | - | - | - | 73 | C11 | VCAP_2 | S | - | - | - | - | | 35 | B1 | 47 | 74 | F11 | VSS | S | - | - | - | - | | 36 | - | 48 | 75 | G11 | VDD | S | - | - | - | - | | - | B2 | - | - | - | VDD | S | - | - | - | - | | 37 | A1 | 49 | 76 | A10 | PA14 (JTCK
SWCLK) | I/O | FT | - | JTCK-SWCLK, EVENTOUT | - | | 38 | A2 | 50 | 77 | A9 | PA15 (JTDI) | I/O | FT | - | JTDI, SPI1_NSS,
SPI3_NSS/I2S3_WS,
TIM2_CH1/TIM2_ETR, JTDI,
EVENTOUT | - | | - | - | 51 | 78 | B11 | PC10 | I/O | FT | - | SPI3_SCK/I2S3_CK,
SDIO_D2, EVENTOUT | - | | - | - | 52 | 79 | C10 | PC11 | I/O | FT | - | I2S3ext_SD, SPI3_MISO,
SDIO_D3, EVENTOUT | - | | - | - | 53 | 80 | B10 | PC12 | I/O | FT | - | SPI3_MOSI/I2S3_SD,
SDIO_CK, EVENTOUT | - | | - | - | - | 81 | C9 | PD0 | I/O | FT | - | EVENTOUT | - |

Table 8. STM32F401xB/STM32F401xC pin definitions (continued)

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|-------|---------------------------------------------------------------------------------|-------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 82 | B9 | PD1 | I/O | FT | - | EVENTOUT | - | | - | - | 54 | 83 | C8 | PD2 | I/O | FT | - | TIM3_ETR, SDIO_CMD,
EVENTOUT | - | | - | - | - | 84 | B8 | PD3 | I/O | FT | - | SPI2_SCK/I2S2_CK,
USART2_CTS, EVENTOUT | - | | - | - | - | 85 | B7 | PD4 | I/O | FT | - | USART2_RTS, EVENTOUT | - | | - | - | - | 86 | A6 | PD5 | I/O | FT | - | USART2_TX, EVENTOUT | - | | - | - | - | 87 | B6 | PD6 | I/O | FT | - | SPI3_MOSI/I2S3_SD,
USART2_RX, EVENTOUT | - | | - | - | - | 88 | A5 | PD7 | I/O | FT | - | USART2_CK, EVENTOUT | - | | 39 | A3 | 55 | 89 | A8 | PB3
(JTDO-SWO) | I/O | FT | - | JTDO-SWO, SPI1_SCK,
SPI3_SCK/I2S3_CK,
I2C2_SDA, TIM2_CH2,
EVENTOUT | - | | 40 | A4 | 56 | 90 | A7 | PB4
(NJTRST) | I/O | FT | - | NJTRST, SPI1_MISO,
SPI3_MISO, I2S3ext_SD,
I2C3_SDA, TIM3_CH1,
EVENTOUT | - | | 41 | B4 | 57 | 91 | C5 | PB5 | I/O | FT | - | SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
I2C1_SMBA, TIM3_CH2,
EVENTOUT | - | | 42 | C4 | 58 | 92 | B5 | PB6 | I/O | FT | - | I2C1_SCL, USART1_TX,
TIM4_CH1, EVENTOUT | - | | 43 | D4 | 59 | 93 | B4 | PB7 | I/O | FT | - | I2C1_SDA, USART1_RX,
TIM4_CH2, EVENTOUT | - | | 44 | A5 | 60 | 94 | A4 | BOOT0 | I | B | - | - | VPP | | 45 | B5 | 61 | 95 | A3 | PB8 | I/O | FT | - | I2C1_SCL, TIM4_CH3,
TIM10_CH1, SDIO_D4,
EVENTOUT | - | | 46 | C5 | 62 | 96 | B3 | PB9 | I/O | FT | - | SPI2_NSS/I2S2_WS,
I2C1_SDA, TIM4_CH4,
TIM11_CH1, SDIO_D5,
EVENTOUT | - | | - | - | - | 97 | C3 | PE0 | I/O | FT | - | TIM4_ETR, EVENTOUT | - | | - | - | - | 98 | A2 | PE1 | I/O | FT | - | EVENTOUT | - |

| | | Pin Number | |--------|---------|------------|---------|----------|------------------------------------------|----------|---------------|-------|---------------------|-------------------------| | UQFN48 | WLCSP49 | LQFP64 | LQFP100 | UFBGA100 | Pin name
(function
after reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | 47 | A6 | 63 | 99 | - | VSS | S | - | - | - | - | | - | B6 | - | - | H3 | PDR_ON | I | FT | - | - | - | | 48 | A7 | 64 | 100 | - | VDD | S | - | - | - | - |

    1. Function availability depends on the chosen device.
    1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
    • The speed should not exceed 2 MHz with a maximum load of 30 pF.
    • These I/Os must not be used as a current source (e.g. to drive an LED).
    1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F401xx reference manual.
    1. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
    1. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low)

| | | | | | | Tabl | e 9. Alter | nate functi | on mapp | oing | |------|------|----------------|-----------------------|---------------------|--------------------------|--------------------|---------------------------------------|--------------------------|---------------------------------|---------------|---------------|-----------------|------|------|------|------|--------------| | | | AF00 | AF01 | AF02 | AF03 | AF04 | AF05 | AF06 | AF07 | AF08 | AF09 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | | Port | SYS_AF | TIM1/TIM2 | TIM3/
TIM4/ TIM5 | TIM9/
TIM10/
TIM11 | I2C1/I2C2/
I2C3 | SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4 | SPI2/I2S2/
SPI3/ I2S3 | SPI3/I2S3/
USART1/
USART2 | USART6 | I2C2/
I2C3 | OTG1_FS | | SDIO | | | PA0 | - | TIM2_CH1/
TIM2_ETR | TIM5_CH1 | - | - | - | - | USART2_
CTS | - | - | - | - | - | - | - | EVENT
OUT | | | PA1 | - | TIM2_CH2 | TIM5_CH2 | - | - | - | - | USART2_
RTS | - | - | - | - | - | - | - | EVENT
OUT | | | PA2 | - | TIM2_CH3 | TIM5_CH3 | TIM9_CH1 | - | - | - | USART2_
TX | - | - | - | - | - | - | - | EVENT
OUT | | | PA3 | - | TIM2_CH4 | TIM5_CH4 | TIM9_CH2 | - | | - | USART2_
RX | - | - | - | - | - | - | - | EVENT
OUT | | | PA4 | - | - | - | - | - | SPI1_NSS | SPI3_NSS/
I2S3_WS | USART2_
CK | - | - | - | - | - | - | - | EVENT
OUT | | | PA5 | - | TIM2_CH1/
TIM2_ETR | - | - | - | SPI1_SCK | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PA6 | - | TIM1_BKIN | TIM3_CH1 | - | - | SPI1_
MISO | - | - | - | - | - | - | - | - | - | EVENT
OUT | | Į. | PA7 | - | TIM1_CH1N | TIM3_CH2 | - | - | SPI1_
MOSI | - | - | - | - | - | - | - | - | - | EVENT
OUT | | Port | PA8 | MCO_1 | TIM1_CH1 | - | - | I2C3_SCL | - | - | USART1_
CK | - | - | OTG_FS_
SOF | - | - | - | - | EVENT
OUT | | | PA9 | - | TIM1_CH2 | - | - | I2C3_
SMBA | - | - | USART1_
TX | - | - | OTG_FS_
VBUS | - | - | | - | EVENT
OUT | | | PA10 | - | TIM1_CH3 | - | - | - | - | - | USART1_
RX | - | - | OTG_FS_I | - | - | - | - | EVENT
OUT | | | PA11 | - | TIM1_CH4 | - | - | - | - | - | USART1_
CTS | USART6_
TX | - | OTG_FS_
DM | - | - | - | - | EVENT
OUT | | | PA12 | - | TIM1_ETR | - | - | - | - | - | USART1_
RTS | USART6_
RX | - | OTG_FS_
DP | - | - | - | - | EVENT
OUT | | | PA13 | JTMS_
SWDIO | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PA14 | JTCK_
SWCLK | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PA15 | JTDI | TIM2_CH1/
TIM2_ETR | - | - | - | SPI1_NSS | SPI3_NSS/
I2S3_WS | - | - | - | - | - | - | - | - | EVENT
OUT |

Table 9. Alternate function mapping (continued)

AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4		SPI2/I2S2/
SPI3/ I2S3		SPI3/I2S3/
USART1/
USART2		USART6I2C2/
I2C3		OTG1_FSSDIO
PB0-TIM1_CH2NTIM3_CH3------------EVENT
OUT
PB1-TIM1_CH3NTIM3_CH4------------EVENT
OUT
PB2---------------EVENT
OUT
PB3JTDO-
SWO		TIM2_CH2---SPI1_SCKSPI3_SCK/
I2S3_CK		--I2C2_SDA-----EVENT
OUT
PB4JTRST-TIM3_CH1--SPI1_
MISO		SPI3_MISOI2S3ext_S
D		-I2C3_SDA-----EVENT
OUT
PB5--TIM3_CH2-I2C1_
SMBA		SPI1
_MOSI		SPI3_MOSI/
I2S3_SD		--------EVENT
OUT
PB6--TIM4_CH1-I2C1_SCL--USART1_
TX		-------EVENT
OUT
BPB7--TIM4_CH2-I2C1_SDA--USART1_
RX		-------EVENT
OUT
Port BPB8--TIM4_CH3TIM10_CH1I2C1_SCL-------SDIO_
D4		--EVENT
OUT
PB9--TIM4_CH4TIM11_CH1I2C1_SDASPI2_NSS/I
2S2_WS		------SDIO_
D5		--EVENT
OUT
PB10-TIM2_CH3--I2C2_SCLSPI2_SCK/I
2S2_CK		---------EVENT
OUT
PB11-TIM2_CH4--I2C2_SDA----------EVENT
OUT
PB12-TIM1_BKIN--I2C2_
SMBA		SPI2_NSS/I
2S2_WS		---------EVENT
OUT
PB13-TIM1_CH1N---SPI2_SCK/I
2S2_CK		---------EVENT
OUT
PB14-TIM1_CH2N---SPI2_MISOI2S2ext_SD--------EVENT
OUT
PB15RTC_
REFN		TIM1_CH3N---SPI2_MOSI
/I2S2_SD		---------EVENT
OUT
200AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4		SPI2/I2S2/
SPI3/ I2S3		SPI3/I2S3/
USART1/
USART2		USART612C2/
12C3		OTG1_FSSDIO
PC0-------,---,----ıEVENT
OUT
PC1--------------1EVENT
OUT
PC2-----SPI2_
MISO		I2S2ext_SD-------1EVENT
OUT
PC3-----SPI2_MOSI
/I2S2_SD		---------EVENT
OUT
PC4---------------EVENT
OUT
PC5---------------EVENT
OUT
D00746 D00 44PC6-TIM3_CH1--I2S2_MCK--USART6_
TX		---SDIO_
D6		--EVENT
OUT
6PC7-TIM3_CH2---I2S3_MCK-USART6_
RX		---SDIO_
D7		--EVENT
OUT
PC8--TIM3_CH3-----USART6_
CK		---SDIO_
D0		--EVENT
OUT
PC9MCO_2-TIM3_CH4-I2C3_SDAI2S_CKIN------SDIO_
D1		--EVENT
OUT
PC10------SPI3_SCK/
I2S3_CK		-----SDIO_
D2		--EVENT
OUT
PC11-----I2S3ext_
SD		SPI3_MISO-----SDIO_
D3		--EVENT
OUT
PC12------SPI3_MOSI/
I2S3_SD		-----SDIO_
CK		-1EVENT
OUT
PC13---------------EVENT
OUT
PC14---------------EVENT
OUT
PC15-----------ıı--EVENT
OUT

Table 9. Alternate function mapping (continued)

Table 9. Alternate function mapping (continued)

AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4		SPI2/I2S2/
SPI3/ I2S3		SPI3/I2S3/
USART1/
USART2		USART612C2/
12C3		OTG1_FSSDIO
PD0---------------EVENT
OUT
PD1---------------EVENT
OUT
PD2--TIM3_ETR---------SDIO_
CMD		--EVENT
OUT
PD3-----SPI2_SCK/
I2S2_CK		-USART2_
CTS		------EVENT
OUT
PD4-------USART2_
RTS		------EVENT
OUT
PD5-------USART2_
TX		-------EVENT
OUT
PD6-----SPI3_MOSI
/I2S3_SD		-USART2_
RX		-------EVENT
OUT
t DPD7-------USART2_
CK		-------EVENT
OUT
Port DPD8---------------EVENT
OUT
PD9---------------EVENT
OUT
PD10---------------EVENT
OUT
PD11---------------EVENT
OUT
PD12--TIM4_CH1------------EVENT
OUT
PD13--TIM4_CH2------------EVENT
OUT
PD14--TIM4_CH3------------EVENT
OUT
PD15--TIM4_CH4---- .--------EVENT
OUT

| | | | | | T | able 9. A | lternate fu | unction ma | apping (c | ontinue | d) | |--------|------|--------------|-----------|---------------------|--------------------------|--------------------|---------------------------------------|--------------------------|---------------------------------|---------|---------------|---------|------|------|------|------|--------------| | | | AF00 | AF01 | AF02 | AF03 | AF04 | AF05 | AF06 | AF07 | AF08 | AF09 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | | Port | SYS_AF | TIM1/TIM2 | TIM3/
TIM4/ TIM5 | TIM9/
TIM10/
TIM11 | I2C1/I2C2/
I2C3 | SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4 | SPI2/I2S2/
SPI3/ I2S3 | SPI3/I2S3/
USART1/
USART2 | USART6 | I2C2/
I2C3 | OTG1_FS | | SDIO | | | PE0 | - | - | TIM4_ETR | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE1 | - | TIM1_CH2N | - | - | - | - | - | - | - | - | - | - | - | 1 | - | EVENT
OUT | | | PE2 | TRACECL
K | - | - | - | - | SPI4_SCK | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE3 | TRACED0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE4 | TRACED1 | - | - | - | - | SPI4_NSS | - | - | - | - | - | - | - | 1 | , | EVENT
OUT | | | PE5 | TRACED2 | - | - | TIM9_CH1 | - | SPI4_MISO | - | - | - | - | - | - | - | 1 | , | EVENT
OUT | | | PE6 | TRACED3 | - | - | TIM9_CH2 | - | SPI4_MOSI | - | - | - | - | - | - | - | - | - | EVENT
OUT | | Ħ
H | PE7 | - | TIM1_ETR | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | Port | PE8 | - | TIM1_CH1N | - | - | - | - | - | - | - | - | - | - | - | - | 1 | EVENT
OUT | | | PE9 | - | TIM1_CH1 | - | - | - | - | - | - | - | - | - | - | - | - | i i | EVENT
OUT | | | PE10 | - | TIM1_CH2N | - | - | - | - | - | - | - | - | - | - | - | - | 1 | EVENT
OUT | | | PE11 | - | TIM1_CH2 | - | - | - | SPI4_NSS | - | - | - | - | - | - | - | - | i i | EVENT
OUT | | | PE12 | - | TIM1_CH3N | - | - | - | SPI4_SCK | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE13 | - | TIM1_CH3 | - | - | - | SPI4_MISO | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE14 | - | TIM1_CH4 | - | - | - | SPI4_MOSI | - | - | - | - | - | - | - | - | 1 | EVENT
OUT | | | PE15 | - | TIM1_BKIN | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT |

Table 9. Alternate function mapping (continued)

| | | | | | | | | | 11 5 ( | |-----|------|--------|-----------|---------------------|--------------------------|--------------------|---------------------------------------|--------------------------|---------------------------------|--------|---------------|---------|------|------|------|------|--------------| | | | AF00 | AF01 | AF02 | AF03 | AF04 | AF05 | AF06 | AF07 | AF08 | AF09 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | | Port | SYS_AF | TIM1/TIM2 | TIM3/
TIM4/ TIM5 | TIM9/
TIM10/
TIM11 | I2C1/I2C2/
I2C3 | SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4 | SPI2/I2S2/
SPI3/ I2S3 | SPI3/I2S3/
USART1/
USART2 | USART6 | 12C2/
12C3 | OTG1_FS | | SDIO | | Ŧ | PH0 | - | - | - | - | - | - | - | - | - | - | - | 1 | - | 1 | 1 | EVENT
OUT | | Por | PH1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT |

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 31 and Table 56, respectively.

Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

1. The $I_{IO}$ current sunk by the device must always respect the absolute maximum rating specified in Table 12. and the sum of $I_{IO}$ (I/O ports and control pins) must not exceed $I_{VSS}$ .

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The $I_{\rm IO}$ current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of $I_{\rm IO}$ (I/O ports and control pins) must not exceed $I_{\rm VDD}$ .

4. Guaranteed by characterization.

5. Guaranteed by design.

Table 56. I/O AC characteristics(1)(2)

| OSPEEDRy
[1:0] bit
value(1) | Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |-----------------------------------|-------------------------|---------------------------------------------------------------------------------|-------------------------------------|-----|-----|--------|------|--| | | | | CL = 50 pF, VDD ≥ 2.70 V | - | - | 4 | | | | Maximum frequency(3) | CL = 50 pF, VDD≥ 1.7 V | - | - | 2 | MHz | | | fmax(IO)out | | CL = 10 pF, VDD ≥ 2.70 V | - | - | 8 | | 00 | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 4 | | | tf(IO)out/
tr(IO)out | Output high to low level fall
time and output low to high
level rise time | CL = 50 pF, VDD = 1.7 V to
3.6 V | - | - | 100 | ns | | | | | CL = 50 pF, VDD ≥ 2.70 V | - | - | 25 | | | | Maximum frequency(3) | CL = 50 pF, VDD ≥ 1.7 V | - | - | 12.5 | | | fmax(IO)out | | CL = 10 pF, VDD ≥ 2.70 V | - | - | 50 | MHz | | | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 20 | | 01 | | | CL = 50 pF, VDD ≥2.7 V | - | - | 10 | | | tf(IO)out/ | Output high to low level fall | CL = 50 pF, VDD ≥ 1.7 V | - | - | 20 | ns | | | tr(IO)out | time and output low to high
level rise time | CL = 10 pF, VDD ≥ 2.70 V | - | - | 6 | | | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 10 | | | | | CL = 40 pF, VDD ≥ 2.70 V | - | - | 50(4) | | | | Maximum frequency(3) | CL = 40 pF, VDD ≥ 1.7 V | - | - | 25 | MHz | | | fmax(IO)out | | CL = 10 pF, VDD ≥ 2.70 V | - | - | 100(4) | | | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 50(4) | | 10 | | | CL = 40 pF, VDD≥ 2.70 V | - | - | 6 | | | tf(IO)out/ | Output high to low level fall | CL = 40 pF, VDD≥ 1.7 V | - | - | 10 | | | tr(IO)out | time and output low to high
level rise time | CL = 10 pF, VDD≥ 2.70 V | - | - | 4 | ns | | | | | CL = 10 pF, VDD≥ 1.7 V | - | - | 6 | | | | | CL = 30 pF, VDD ≥ 2.70 V | - | - | 100(4) | | | | Maximum frequency(3) | CL = 30 pF, VDD ≥ 1.7 V | - | - | 50(4) | | | Fmax(IO)out | | CL = 10 pF, VDD ≥ 2.70 V | - | - | 180(4) | MHz | | | | | CL = 10 pF, VDD≥ 1.7 V | - | - | 100(4) | | 11 | | | CL = 30 pF, VDD ≥ 2.70 V | - | - | 4 | | | tf(IO)out/ | Output high to low level fall | CL = 30 pF, VDD ≥ 1.7 V | - | - | 6 | ns | | | tr(IO)out | time and output low to high
level rise time | CL = 10 pF, VDD≥ 2.70 V | - | - | 2.5 | | | | | CL = 10 pF, VDD≥ 1.7 V | - | - | 4 | | - | tEXTIpw | Pulse width of external
signals detected by the EXTI
controller | - | 10 | - | - | ns |

    1. Guaranteed by characterization.
    1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
    1. The maximum frequency is defined in Figure 31.
    1. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.

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Figure 31. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand.

SymbolRatingsMinMaxUnit
VDD–VSSExternal main supply voltage (including VDDA, VDD and
(1)
VBAT)		–0.34.0
Input voltage on FT pins(2)VSS–0.3VDD+4.0V
VINInput voltage on any other pinVSS–0.34.0
Input voltage for BOOT0VSS9.0
ΔVDDxVariations between different VDD power pins-50
VSSX −VSSVariations between all the different ground pins
including VREF-		50mV
VESD(HBM)Electrostatic discharge voltage (human body model)see Section 6.3.14-

Table 11. Voltage characteristics

    1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
    1. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current.

Table 12. Current characteristics

SymbolRatingsMax.Unit
ΣIVDDTotal current into sum of all VDD_x power lines (source)(1)160
Σ IVSSTotal current out of sum of all VSS_x ground lines (sink)(1)-160
IVDDMaximum current into each VDD_x power line (source)(1)100
IVSSMaximum current out of each VSS_x ground line (sink)(1)-100
Output current sunk by any I/O and control pin25
IIOOutput current sourced by any I/O and control pin-25mA
Total output current sunk by sum of all I/O and control pins (2)120
ΣIIOTotal output current sourced by sum of all I/Os and control pins(2)-120
Injected current on FT pins (4)–5/+0
IINJ(PIN) (3)
Injected current on NRST and B pins (4)
ΣIINJ(PIN)Total injected current (sum of all I/O and control pins)(5)±25
    1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
  • 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
    1. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
    1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
    1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

SymbolRatingsValueUnit
TSTGStorage temperature range–65 to +150
TJMaximum junction temperature130°C
TLEADMaximum lead temperature during soldering
(WLCSP49, LQFP64/100, UFQFPN48, UFBGA100)		See note (1)
  1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011).

Thermal Information

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 14: General operating conditions on page 59.

The maximum chip-junction temperature, TJ max., in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max x ΘJA)

Where:

  • TA max is the maximum ambient temperature in °C,
  • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
  • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
  • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$$P_{I/O} \max = \sum (V_{OL} \times I_{OL}) + \sum ((V_{DD} - V_{OH}) \times I_{OH}),$$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

SymbolParameterValueUnit
Thermal resistance junction-ambient
UFQFPN48		32
Thermal resistance junction-ambient
WLCSP49		52
ΘJAThermal resistance junction-ambient
LQFP64		50°C/W
Thermal resistance junction-ambient
LQFP100		42
Thermal resistance junction-ambient
UFBGA100		62
Table 86. Package thermal characteristics

7.6.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

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