STM32F072X8/XB
ARM®-based 32-bit MCUThe STM32F072X8/XB is a arm®-based 32-bit mcu from STMicroelectronics. View the full STM32F072X8/XB datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Category
Microcontrollers (MCU)Overview
The STM32F072x8/xB microcontrollers incorporate the high-performance ARM ® Cortex ® M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (two I 2 Cs, two SPI/I2S, one HDMI CEC and four USARTs), one USB Full speed device (crystalless), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer.
The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of powersaving modes allows the design of low-power applications.
The STM32F072x8/xB microcontrollers include devices in seven different packages ranging from 48 pins to 100 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. The description below provides an overview of the complete range of STM32F072x8/xB peripherals proposed.
These features make the STM32F072x8/xB microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Table 2. STM32F072x8/xB family device features and peripheral counts
| Peripheral | Peripheral | 64 | 64 | 128 | 128 | 128 | 128 | 128 | 128 | 128 | 128 | 128 | 128 | 128 | 128 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 64 | 64 | 1 (16-bit) | 5 (16-bit) 1 (32-bit) | 2 (16-bit) | 2 [2] | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| 4 | 4 1 LQFP48 UFQFPN48 WLCSP49 LQFP64 UFBGA64 LQFP100 UFBGA100 | |||||||||||||||
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Figure 1. Block diagram
Features
- Core: ARM ® 32-bit Cortex ® -M0 CPU, frequency up to 48 MHz
- Memories
- -64 to 128 Kbytes of Flash memory
- -16 Kbytes of SRAM with HW parity
- CRC calculation unit
- Reset and power management
- -Digital and I/O supply: V DD = 2.0 V to 3.6 V
- -Analog supply: V DDA = V DD to 3.6 V
- -Selected I/Os: V DDIO2 = 1.65 V to 3.6 V
- -Power-on/Power down reset (POR/PDR)
- -Programmable voltage detector (PVD)
- -Low power modes: Sleep, Stop, Standby
- -VBAT supply for RTC and backup registers
- Clock management
- -4 to 32 MHz crystal oscillator
- -32 kHz oscillator for RTC with calibration
- -Internal 8 MHz RC with x6 PLL option
- -Internal 40 kHz RC oscillator
- -Internal 48 MHz oscillator with automatic trimming based on ext. synchronization
- Up to 87 fast I/Os
- -All mappable on external interrupt vectors
- -Up to 68 I/Os with 5V tolerant capability and 19 with independent supply V DDIO2
- Seven-channel DMA controller
- One 12-bit, 1.0 μs ADC (up to 16 channels)
- -Conversion range: 0 to 3.6 V
- -Separate analog supply: 2.4 V to 3.6 V
- One 12-bit D/A converter (with 2 channels)
- Two fast low-power analog comparators with programmable input and output
- Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors
Pin Configuration
Figure 3. UFBGA100 package ballout (top view)
Figure 4. LQFP100 100-pin package pinout (top view)
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Figure 5. UFBGA64 package ball-out (top view)
Figure 6. LQFP64 64-pin package pinout (top view)
Figure 7. LQFP48 48-pin package pinout (top view)
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Figure 8. UFQFPN48 48-pin package pinout (top view)
Figure 9. WLCSP49 49-pin package ballout (bottom view)
Table 12. Legend/abbreviations used in the pinout table
| Name | brackets actual | Definition below the pin name, the pin function during and pin name | Abbreviation Pin name Unless otherwise specified in after reset is the same as the |
|---|---|---|---|
| Supply pin | Supply pin | type | type |
| I | pin | Input only pin | Pin I/O Input / output |
| FT | 5 V tolerant I/O | ||
| FTf | 5 V tolerant I/O, FM+ capable | ||
| BOOT0 | pin with I/Os registers | TTa B Dedicated RST | |
| 3.3 V tolerant I/O directly connected to ADC | I/O structure | ||
| TC | Standard 3.3 V I/O Bidirectional reset pin embedded weak pull-up resistor | ||
| Unless otherwise specified by a note, all are set as floating inputs during and after reset. | Notes Pin functions | ||
| Alternate functions | Alternate functions | Functions selected through GPIOx_AFR | Functions selected through GPIOx_AFR |
| Additional functions | Functions directly selected/enabled through peripheral registers | ||
| Additional functions |
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| B2 | 1 | - | - | - | - | PE2 | I/O | FT | - | TSC_G7_IO1, TIM3_ETR | - |
| A1 | 2 | - | - | - | - | PE3 | I/O | FT | - | TSC_G7_IO2, TIM3_CH1 | - |
| B1 | 3 | - | - | - | - | PE4 | I/O | FT | - | TSC_G7_IO3, TIM3_CH2 | - |
| C2 | 4 | - | - | - | - | PE5 | I/O | FT | - | TSC_G7_IO4, TIM3_CH3 | - |
| D2 | 5 | - | - | - | - | PE6 | I/O | FT | - | TIM3_CH4 | WKUP3, RTC_TAMP3 |
| E2 | 6 | B2 | 1 | 1 | B7 | VBAT | S | - | - | Backup power supply | Backup power supply |
Table 13. STM32F072x8/xB pin definitions
42
Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| C1 | 7 | A2 | 2 | 2 | D5 | PC13 | I/O | TC | (1) (2) | - | WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT |
| D1 | 8 | A1 | 3 | 3 | C7 | PC14- OSC32_IN (PC14) | I/O | TC | (1) (2) | - | OSC32_IN |
| E1 | 9 | B1 | 4 | 4 | C6 | PC15- OSC32_OUT (PC15) | I/O | TC | (1) (2) | - | OSC32_OUT |
| F2 | 10 | - | - | - | - | PF9 | I/O | FT | - | TIM15_CH1 | - |
| G2 | 11 | - | - | - | PF10 | I/O | FT | - | TIM15_CH2 | - | |
| F1 | 12 | C1 | 5 | 5 | D7 | PF0-OSC_IN (PF0) | I/O | FT | - | CRS_ SYNC | OSC_IN |
| G1 | 13 | D1 | 6 | 6 | D6 | PF1-OSC_OUT (PF1) | I/O | FT | - | - | OSC_OUT |
| H2 | 14 | E1 | 7 | 7 | E7 | NRST | I/O | RST | - | Device reset input / internal reset output (active low) | Device reset input / internal reset output (active low) |
| H1 | 15 | E3 | 8 | - | - | PC0 | I/O | TTa | - | EVENTOUT | ADC_IN10 |
| J2 | 16 | E2 | 9 | - | - | PC1 | I/O | TTa | - | EVENTOUT | ADC_IN11 |
| J3 | 17 | F2 | 10 | - | - | PC2 | I/O | TTa | - | SPI2_MISO, I2S2_MCK, EVENTOUT | ADC_IN12 |
| K2 | 18 | G1 | 11 | - | - | PC3 | I/O | TTa | - | SPI2_MOSI, I2S2_SD, EVENTOUT | ADC_IN13 |
| J1 | 19 | - | - | - | - | PF2 | I/O | FT | - | EVENTOUT | WKUP8 |
| K1 | 20 | F1 | 12 | 8 | E6 | VSSA | S | - | - | Analog ground | Analog ground |
| M1 | 21 | H1 | 13 | 9 | F7 | VDDA | S | - | - | Analog power supply | Analog power supply |
| L1 | 22 | - | - | - | - | PF3 | I/O | FT | - | EVENTOUT | |
| L2 | 23 | G2 | 14 | 10 | F6 | PA0 | I/O | TTa | - | USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TX | RTC_ TAMP2, WKUP1, ADC_IN0, COMP1_INM6 |
Table 13. STM32F072x8/xB pin definitions (continued)
Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| M2 | 24 | H2 | 15 | 11 | G7 | PA1 | I/O | TTa | - | USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT | ADC_IN1, COMP1_INP |
| K3 | 25 | F3 | 16 | 12 | E5 | PA2 | I/O | TTa | - | USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3 | ADC_IN2, COMP2_INM6, WKUP4 |
| L3 | 26 | G3 | 17 | 13 | E4 | PA3 | I/O | TTa | - | USART2_RX,TIM2_CH4, TIM15_CH2, TSC_G1_IO4 | ADC_IN3, COMP2_INP |
| D3 | 27 | C2 | 18 | - | - | VSS | S | - | - | Ground | Ground |
| H3 | 28 | D2 | 19 | - | - | VDD | S | - | - | Digital power supply | Digital power supply |
| M3 | 29 | H3 | 20 | 14 | G6 | PA4 | I/O | TTa | - | SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK | COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1 |
| K4 | 30 | F4 | 21 | 15 | F5 | PA5 | I/O | TTa | - | SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2 | COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2 |
| L4 | 31 | G4 | 22 | 16 | F4 | PA6 | I/O | TTa | - | SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS | ADC_IN6 |
| M4 | 32 | H4 | 23 | 17 | F3 | PA7 | I/O | TTa | - | SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT | ADC_IN7 |
Table 13. STM32F072x8/xB pin definitions (continued)
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Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| K5 | 33 | H5 | 24 | - | - | PC4 | I/O | TTa | - | EVENTOUT, USART3_TX | ADC_IN14 |
| L5 | 34 | H6 | 25 | - | - | PC5 | I/O | TTa | - | TSC_G3_IO1, USART3_RX | ADC_IN15, WKUP5 |
| M5 | 35 | F5 | 26 | 18 | G5 | PB0 | I/O | TTa | - | TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK | ADC_IN8 |
| M6 | 36 | G5 | 27 | 19 | G4 | PB1 | I/O | TTa | - | TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3 | ADC_IN9 |
| L6 | 37 | G6 | 28 | 20 | G3 | PB2 | I/O | FT | - | TSC_G3_IO4 | - |
| M7 | 38 | - | - | - | - | PE7 | I/O | FT | - | TIM1_ETR | - |
| L7 | 39 | - | - | - | - | PE8 | I/O | FT | - | TIM1_CH1N | - |
| M8 | 40 | - | - | - | - | PE9 | I/O | FT | - | TIM1_CH1 | - |
| L8 | 41 | - | - | - | - | PE10 | I/O | FT | - | TIM1_CH2N | - |
| M9 | 42 | - | - | - | - | PE11 | I/O | FT | - | TIM1_CH2 | - |
| L9 | 43 | - | - | - | - | PE12 | I/O | FT | - | SPI1_NSS, I2S1_WS, TIM1_CH3N | - |
| M10 | 44 | - | - | - | - | PE13 | I/O | FT | - | SPI1_SCK, I2S1_CK, TIM1_CH3 | - |
| M11 | 45 | - | - | - | - | PE14 | I/O | FT | - | SPI1_MISO, I2S1_MCK, TIM1_CH4 | - |
| M12 | 46 | - | - | - | - | PE15 | I/O | FT | - | SPI1_MOSI, I2S1_SD, TIM1_BKIN | - |
| L10 | 47 | G7 | 29 | 21 | E3 | PB10 | I/O | FT | - | SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3 | - |
| L11 | 48 | H7 | 30 | 22 | G2 | PB11 | I/O | FT | - | USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA | - |
| F12 | 49 | D5 | 31 | 23 | D3 | VSS | S | - | - | Ground | Ground |
Table 13. STM32F072x8/xB pin definitions (continued)
Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| G12 | 50 | E5 | 32 | 24 | F2 | VDD | S | - | - | Digital power supply | Digital power supply |
| L12 | 51 | H8 | 33 | 25 | E2 | PB12 | I/O | FT | - | TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT | - |
| K12 | 52 | G8 | 34 | 26 | G1 | PB13 | I/O | FTf | - | SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3 | - |
| K11 | 53 | F8 | 35 | 27 | F1 | PB14 | I/O | FTf | - | SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4 | - |
| K10 | 54 | F7 | 36 | 28 | E1 | PB15 | I/O | FT | - | SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2 | WKUP7, RTC_REFIN |
| K9 | 55 | - | - | - | - | PD8 | I/O | FT | - | USART3_TX | - |
| K8 | 56 | - | - | - | - | PD9 | I/O | FT | - | USART3_RX | - |
| J12 | 57 | - | - | - | - | PD10 | I/O | FT | - | USART3_CK | - |
| J11 | 58 | - | - | - | - | PD11 | I/O | FT | - | USART3_CTS | - |
| J10 | 59 | - | - | - | - | PD12 | I/O | FT | - | USART3_RTS, TSC_G8_IO1 | - |
| H12 | 60 | - | - | - | - | PD13 | I/O | FT | - | TSC_G8_IO2 | - |
| H11 | 61 | - | - | - | - | PD14 | I/O | FT | - | TSC_G8_IO3 | - |
| H10 | 62 | - | - | - | - | PD15 | I/O | FT | - | TSC_G8_IO4, CRS_SYNC | - |
| E12 | 63 | F6 | 37 | - | - | PC6 | I/O | FT | (3) | TIM3_CH1 | - |
| E11 | 64 | E7 | 38 | - | - | PC7 | I/O | FT | (3) | TIM3_CH2 | - |
| E10 | 65 | E8 | 39 | - | - | PC8 | I/O | FT | (3) | TIM3_CH3 | - |
| D12 | 66 | D8 | 40 | - | - | PC9 | I/O | FT | (3) | TIM3_CH4 | - |
Table 13. STM32F072x8/xB pin definitions (continued)
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Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| D11 | 67 | D7 | 41 | 29 | D1 | PA8 | I/O | FT | (3) | USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC | - |
| D10 | 68 | C7 | 42 | 30 | D2 | PA9 | I/O | FT | (3) | USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1 | - |
| C12 | 69 | C6 | 43 | 31 | C2 | PA10 | I/O | FT | (3) | USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2 | - |
| B12 | 70 | C8 | 44 | 32 | C1 | PA11 | I/O | FT | (3) | CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT | USB_DM |
| A12 | 71 | B8 | 45 | 33 | C3 | PA12 | I/O | FT | (3) | CAN_TX,USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT | USB_DP |
| A11 | 72 | A8 | 46 | 34 | B3 | PA13 | I/O | FT | (3) (4) | IR_OUT, SWDIO, USB_NOE | - |
| C11 | 73 | - | - | - | - | PF6 | I/O | FT | (3) | - | - |
| F11 | 74 | D6 | 47 | 35 | B1 | VSS | S | - | - | Ground | Ground |
| G11 | 75 | E6 | 48 | 36 | B2 | VDDIO2 | S | - | - | Digital power supply | Digital power supply |
| A10 | 76 | A7 | 49 | 37 | A1 | PA14 | I/O | FT | (3) (4) | USART2_TX, SWCLK | - |
| A9 | 77 | A6 | 50 | 38 | A2 | PA15 | I/O | FT | (3) | SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT | - |
| B11 | 78 | B7 | 51 | - | - | PC10 | I/O | FT | (3) | USART3_TX, USART4_TX | - |
Table 13. STM32F072x8/xB pin definitions (continued)
Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| C10 | 79 | B6 | 52 | - | - | PC11 | I/O | FT | (3) | USART3_RX, USART4_RX | - |
| B10 | 80 | C5 | 53 | - | - | PC12 | I/O | FT | (3) | USART3_CK, USART4_CK | - |
| C9 | 81 | - | - | - | - | PD0 | I/O | FT | (3) | SPI2_NSS, I2S2_WS, CAN_RX | - |
| B9 | 82 | - | - | - | - | PD1 | I/O | FT | (3) | SPI2_SCK, I2S2_CK, CAN_TX | - |
| C8 | 83 | B5 | 54 | - | - | PD2 | I/O | FT | (3) | USART3_RTS, TIM3_ETR | - |
| B8 | 84 | - | - | - | - | PD3 | I/O | FT | - | SPI2_MISO, I2S2_MCK, USART2_CTS | - |
| B7 | 85 | - | - | - | - | PD4 | I/O | FT | - | SPI2_MOSI, I2S2_SD, USART2_RTS | - |
| A6 | 86 | - | - | - | - | PD5 | I/O | FT | - | USART2_TX | - |
| B6 | 87 | - | - | - | - | PD6 | I/O | FT | - | USART2_RX | - |
| A5 | 88 | - | - | - | - | PD7 | I/O | FT | - | USART2_CK | - |
| A8 | 89 | A5 | 55 | 39 | A3 | PB3 | I/O | FT | - | SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT | - |
| A7 | 90 | A4 | 56 | 40 | A4 | PB4 | I/O | FT | - | SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT | - |
| C5 | 91 | C4 | 57 | 41 | B4 | PB5 | I/O | FT | - | SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 | WKUP6 |
| B5 | 92 | D3 | 58 | 42 | C4 | PB6 | I/O | FTf | - | I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_I03 | - |
Table 13. STM32F072x8/xB pin definitions (continued)
42
Table 13. STM32F072x8/xB pin definitions (continued)
| Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin numbers | Pin functions | Pin functions | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| UFBGA100 | LQFP100 | UFBGA64 | LQFP64 | LQFP48/UFQFPN48 | WLCSP49 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions |
| B4 | 93 | C3 | 59 | 43 | D4 | PB7 | I/O | FTf | - | I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4 | - |
| A4 | 94 | B4 | 60 | 44 | A5 | BOOT0 | I | B | - | Boot memory selection | Boot memory selection |
| A3 | 95 | B3 | 61 | 45 | B5 | PB8 | I/O | FTf | - | I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX | - |
| B3 | 96 | A3 | 62 | 46 | C5 | PB9 | I/O | FTf | - | SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX | - |
| C3 | 97 | - | - | - | - | PE0 | I/O | FT | - | EVENTOUT, TIM16_CH1 | - |
| A2 | 98 | - | - | - | - | PE1 | I/O | FT | - | EVENTOUT, TIM17_CH1 | - |
| D3 | 99 | D4 | 63 | 47 | A6 | VSS | S | - | - | Ground | Ground |
| C4 | 100 | E4 | 64 | 48 | A7 | VDD | S | - | - | Digital power supply | Digital power supply |
- PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
- After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.
- PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os are supplied by VDDIO2.
- After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated.
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
| Pin name | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PA0 | - | USART2_CTS | TIM2_CH1_ETR | TSC_G1_IO1 | USART4_TX | - | - | COMP1_OUT |
| PA1 | EVENTOUT | USART2_RTS | TIM2_CH2 | TSC_G1_IO2 | USART4_RX | TIM15_CH1N | - | - |
| PA2 | TIM15_CH1 | USART2_TX | TIM2_CH3 | TSC_G1_IO3 | - | - | - | COMP2_OUT |
| PA3 | TIM15_CH2 | USART2_RX | TIM2_CH4 | TSC_G1_IO4 | - | - | - | - |
| PA4 | SPI1_NSS, I2S1_WS | USART2_CK | - | TSC_G2_IO1 | TIM14_CH1 | - | - | - |
| PA5 | SPI1_SCK, I2S1_CK | CEC | TIM2_CH1_ETR | TSC_G2_IO2 | - | - | - | - |
| PA6 | SPI1_MISO, I2S1_MCK | TIM3_CH1 | TIM1_BKIN | TSC_G2_IO3 | USART3_CTS | TIM16_CH1 | EVENTOUT | COMP1_OUT |
| PA7 | SPI1_MOSI, I2S1_SD | TIM3_CH2 | TIM1_CH1N | TSC_G2_IO4 | TIM14_CH1 | TIM17_CH1 | EVENTOUT | COMP2_OUT |
| PA8 | MCO | USART1_CK | TIM1_CH1 | EVENTOUT | CRS_SYNC | - | - | - |
| PA9 | TIM15_BKIN | USART1_TX | TIM1_CH2 | TSC_G4_IO1 | - | - | - | - |
| PA10 | TIM17_BKIN | USART1_RX | TIM1_CH3 | TSC_G4_IO2 | - | - | - | - |
| PA11 | EVENTOUT | USART1_CTS | TIM1_CH4 | TSC_G4_IO3 | CAN_RX | - | - | COMP1_OUT |
| PA12 | EVENTOUT | USART1_RTS | TIM1_ETR | TSC_G4_IO4 | CAN_TX | - | - | COMP2_OUT |
| PA13 | SWDIO | IR_OUT | USB_NOE | - | - | - | - | - |
| PA14 | SWCLK | USART2_TX | - | - | - | - | - | - |
| PA15 | SPI1_NSS, I2S1_WS | USART2_RX | TIM2_CH1_ETR | EVENTOUT | USART4_RTS | - | - | - |
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
| Pin name | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 |
|---|---|---|---|---|---|---|
| PB0 | EVENTOUT | TIM3_CH3 | TIM1_CH2N | TSC_G3_IO2 | USART3_CK | - |
| PB1 | TIM14_CH1 | TIM3_CH4 | TIM1_CH3N | TSC_G3_IO3 | USART3_RTS | - |
| PB2 | - | - | - | TSC_G3_IO4 | - | - |
| PB3 | SPI1_SCK, I2S1_CK | EVENTOUT | TIM2_CH2 | TSC_G5_IO1 | - | - |
| PB4 | SPI1_MISO, I2S1_MCK | TIM3_CH1 | EVENTOUT | TSC_G5_IO2 | - | TIM17_BKIN |
| PB5 | SPI1_MOSI, I2S1_SD | TIM3_CH2 | TIM16_BKIN | I2C1_SMBA | - | - |
| PB6 | USART1_TX | I2C1_SCL | TIM16_CH1N | TSC_G5_IO3 | - | - |
| PB7 | USART1_RX | I2C1_SDA | TIM17_CH1N | TSC_G5_IO4 | USART4_CTS | - |
| PB8 | CEC | I2C1_SCL | TIM16_CH1 | TSC_SYNC | CAN_RX | - |
| PB9 | IR_OUT | I2C1_SDA | TIM17_CH1 | EVENTOUT | CAN_TX | SPI2_NSS, I2S2_WS |
| PB10 | CEC | I2C2_SCL | TIM2_CH3 | TSC_SYNC | USART3_TX | SPI2_SCK, I2S2_CK |
| PB11 | EVENTOUT | I2C2_SDA | TIM2_CH4 | TSC_G6_IO1 | USART3_RX | - |
| PB12 | SPI2_NSS, I2S2_WS | EVENTOUT | TIM1_BKIN | TSC_G6_IO2 | USART3_CK | TIM15_BKIN |
| PB13 | SPI2_SCK, I2S2_CK | - | TIM1_CH1N | TSC_G6_IO3 | USART3_CTS | I2C2_SCL |
| PB14 | SPI2_MISO, I2S2_MCK | TIM15_CH1 | TIM1_CH2N | TSC_G6_IO4 | USART3_RTS | I2C2_SDA |
| PB15 | SPI2_MOSI, I2S2_SD | TIM15_CH2 | TIM1_CH3N | TIM15_CH1N | - | - |
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Table 16. Alternate functions selected through GPIOC_AFR registers for port C
| Pin name | AF0 | AF1 |
|---|---|---|
| PC0 | EVENTOUT | - |
| PC1 | EVENTOUT | - |
| PC2 | EVENTOUT | SPI2_MISO, I2S2_MCK |
| PC3 | EVENTOUT | SPI2_MOSI, I2S2_SD |
| PC4 | EVENTOUT | USART3_TX |
| PC5 | TSC_G3_IO1 | USART3_RX |
| PC6 | TIM3_CH1 | - |
| PC7 | TIM3_CH2 | - |
| PC8 | TIM3_CH3 | - |
| PC9 | TIM3_CH4 | - |
| PC10 | USART4_TX | USART3_TX |
| PC11 | USART4_RX | USART3_RX |
| PC12 | USART4_CK | USART3_CK |
| PC13 | - | - |
| PC14 | - | - |
| PC15 | - | - |
Table 17. Alternate functions selected through GPIOD_AFR registers for port D
| Pin name | AF0 | AF1 |
|---|---|---|
| PD0 | CAN_RX | SPI2_NSS, I2S2_WS |
| PD1 | CAN_TX | SPI2_SCK, I2S2_CK |
| PD2 | TIM3_ETR | USART3_RTS |
| PD3 | USART2_CTS | SPI2_MISO, I2S2_MCK |
| PD4 | USART2_RTS | SPI2_MOSI, I2S2_SD |
| PD5 | USART2_TX | - |
| PD6 | USART2_RX | - |
| PD7 | USART2_CK | - |
| PD8 | USART3_TX | - |
| PD9 | USART3_RX | - |
| PD10 | USART3_CK | - |
| PD11 | USART3_CTS | - |
| PD12 | USART3_RTS | TSC_G8_IO1 |
| PD13 | - | TSC_G8_IO2 |
| PD14 | - | TSC_G8_IO3 |
| PD15 | CRS_SYNC | TSC_G8_IO4 |
46
Table 18. Alternate functions selected through GPIOE_AFR registers for port E
| Pin name | AF0 | AF1 |
|---|---|---|
| PE0 | TIM16_CH1 | EVENTOUT |
| PE1 | TIM17_CH1 | EVENTOUT |
| PE2 | TIM3_ETR | TSC_G7_IO1 |
| PE3 | TIM3_CH1 | TSC_G7_IO2 |
| PE4 | TIM3_CH2 | TSC_G7_IO3 |
| PE5 | TIM3_CH3 | TSC_G7_IO4 |
| PE6 | TIM3_CH4 | - |
| PE7 | TIM1_ETR | - |
| PE8 | TIM1_CH1N | - |
| PE9 | TIM1_CH1 | - |
| PE10 | TIM1_CH2N | - |
| PE11 | TIM1_CH2 | - |
| PE12 | TIM1_CH3N | SPI1_NSS, I2S1_WS |
| PE13 | TIM1_CH3 | SPI1_SCK, I2S1_CK |
| PE14 | TIM1_CH4 | SPI1_MISO, I2S1_MCK |
| PE15 | TIM1_BKIN | SPI1_MOSI, I2S1_SD |
Table 19. Alternate functions available on port F
| Pin name | AF |
|---|---|
| PF0 | CRS_SYNC |
| PF1 | - |
| PF2 | EVENTOUT |
| PF3 | EVENTOUT |
| PF6 | - |
| PF9 | TIM15_CH1 |
| PF10 | TIM15_CH2 |
Table 19. Alternate functions available on port F
Electrical Characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and Table 55 , respectively.
Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions .
Table 55. I/O AC characteristics (1)(2)
| OSPEEDRy [1:0] value (1) | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| x0 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 2 | MHz |
| x0 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| x0 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| x0 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 1 | MHz |
| x0 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| x0 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 10 | MHz |
| 01 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 25 | ns |
| 01 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 25 | ns |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 4 | MHz |
| 01 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 62.5 | ns |
| 01 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 62.5 | ns |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 30 pF, V DDIOx 2.7 V | - | 50 | MHz |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2.7 V | - | 30 | MHz |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, 2 V V DDIOx 2.7 V | - | 20 | MHz |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 10 | MHz |
| f(IO)out Output fall time | C L = 30 pF, V DDIOx 2.7 V | - | 5 | |||
| f(IO)out Output fall time | C L = 50 pF, V DDIOx 2.7 V | - | 8 | |||
| t | f(IO)out Output fall time | C L = 50 pF, 2 V V DDIOx 2.7 V | - | 12 | ||
| f(IO)out Output fall time | C L = 50 pF, V DDIOx 2 V | - | 25 | |||
| t r(IO)out | Output rise time | C L = 30 pF, V DDIOx 2.7 V | - | 5 | ns | |
| t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2.7 V | - | 8 | ns | |
| t r(IO)out | Output rise time | C L = 50 pF, 2 V V DDIOx 2.7 V | - | 12 | ns | |
| t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 25 | ns |
Table 55. I/O AC characteristics (1)(2)
105
Table 55. I/O AC characteristics (1)(2) (continued)
| OSPEEDRy [1:0] value (1) | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| Fm+ configuration (4) | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 2 | MHz |
| Fm+ configuration (4) | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 12 | ns |
| Fm+ configuration (4) | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 34 | ns |
| Fm+ configuration (4) | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 0.5 | MHz |
| Fm+ configuration (4) | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 16 | ns |
| Fm+ configuration (4) | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 44 | ns |
| - | t EXTIpw | Pulse width of external signals detected by the EXTI controller | - | 10 | - | ns |
- Guaranteed by design, not tested in production.
- The maximum frequency is defined in Figure 24 .
- When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.
Figure 24. I/O AC characteristics definition
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics , Table 22: Current characteristics and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 21. Voltage characteristics (1)
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DD -V SS | External main supply voltage | -0.3 | 4.0 | V |
| V DDIO2 -V SS | External I/O supply voltage | -0.3 | 4.0 | V |
| V DDA -V SS | External analog supply voltage | -0.3 | 4.0 | V |
| V DD -V DDA | Allowed voltage difference for V DD > V DDA | - | 0.4 | V |
| V BAT -V SS | External backup supply voltage | -0.3 | 4.0 | V |
| V IN (2) | Input voltage on FT and FTf pins | V SS 0.3 | V DDIOx + 4.0 (3) | V |
| V IN (2) | Input voltage on TTa pins | V SS 0.3 | 4.0 | V |
| V IN (2) | BOOT0 | 0 | 9.0 | V |
| V IN (2) | Input voltage on any other pin | V SS 0.3 | 4.0 | V |
| | V DDx | | Variations between different V DD power pins | - | 50 | mV |
| |V SSx V SS | | Variations between all the different ground pins | - | 50 | mV |
| V ESD(HBM) | Electrostatic discharge voltage (human body model) | see Section 6.3.12: Electrical sensitivity characteristics | see Section 6.3.12: Electrical sensitivity characteristics |
105
Table 22. Current characteristics
| Symbol | Ratings | Max. | Unit |
|---|---|---|---|
| I VDD | Total current into sum of all VDDpower lines (source) (1) | 120 | mA |
| I VSS | Total current out of sum of all VSS ground lines (sink) (1) | -120 | mA |
| I VDD(PIN) | Maximum current into each VDD power pin (source) (1) | 100 | mA |
| I VSS(PIN) | Maximum current out of each VSS ground pin (sink) (1) | -100 | mA |
| I IO(PIN) | Output current sunk by any I/O and control pin | 25 | mA |
| I IO(PIN) | Output current source by any I/O and control pin | -25 | mA |
| I IO(PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 80 | mA |
| I IO(PIN) | Total output current sourced by sum of all I/Os and control pins (2) | -80 | mA |
| I IO(PIN) | Total output current sourced by sum of all I/Os supplied by VDDIO2 | -40 | mA |
| I INJ(PIN) (3) | Injected current on B, FT and FTf pins | -5/+0 (4) | mA |
| I INJ(PIN) (3) | Injected current on TC and RST pin | ± 5 | mA |
| I INJ(PIN) (3) | Injected current on TTa pins (5) | ± 5 | mA |
| I INJ(PIN) | Total injected current (sum of all I/O and control pins) (6) | ± 25 | mA |
- This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
- A positive injection is induced by V IN > V DDIOx while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- On these I/Os, a positive injection is induced by V IN > V DDA . Negative injection disturbs the analog performance of the device. See note (2) below Table 59: ADC accuracy .
- When several inputs are submitted to a current injection, the maximum I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).
Table 23. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 150 | °C |
Table 23. Thermal characteristics
Thermal Information
The maximum chip junction temperature (T J max) must never exceed the values given in Table 24: General operating conditions .
The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:T _ { J } max = T _ { A } max + ( P _ { D } max × Θ _ { J A } )$
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.
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| STM32F072XB | STMicroelectronics | — |
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