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STM32F072X8/XB

ARM®-based 32-bit MCU

The STM32F072X8/XB is a arm®-based 32-bit mcu from STMicroelectronics. View the full STM32F072X8/XB datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Overview

The STM32F072x8/xB microcontrollers incorporate the high-performance ARM ® Cortex ® M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (two I 2 Cs, two SPI/I2S, one HDMI CEC and four USARTs), one USB Full speed device (crystalless), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer.

The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of powersaving modes allows the design of low-power applications.

The STM32F072x8/xB microcontrollers include devices in seven different packages ranging from 48 pins to 100 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. The description below provides an overview of the complete range of STM32F072x8/xB peripherals proposed.

These features make the STM32F072x8/xB microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

Table 2. STM32F072x8/xB family device features and peripheral counts

PeripheralPeripheral6464128128128128128128128128128128128128
64641 (16-bit)5 (16-bit) 1 (32-bit)2 (16-bit)2 [2]22222222222
44
1
LQFP48 UFQFPN48 WLCSP49 LQFP64 UFBGA64 LQFP100 UFBGA100
Packages
Packages
Packages
Packages
Packages
Packages

29

Figure 1. Block diagram

Features

  •  Core: ARM ® 32-bit Cortex ® -M0 CPU, frequency up to 48 MHz
  •  Memories
  • -64 to 128 Kbytes of Flash memory
  • -16 Kbytes of SRAM with HW parity
  •  CRC calculation unit
  •  Reset and power management
  • -Digital and I/O supply: V DD = 2.0 V to 3.6 V
  • -Analog supply: V DDA = V DD to 3.6 V
  • -Selected I/Os: V DDIO2 = 1.65 V to 3.6 V
  • -Power-on/Power down reset (POR/PDR)
  • -Programmable voltage detector (PVD)
  • -Low power modes: Sleep, Stop, Standby
  • -VBAT supply for RTC and backup registers
  •  Clock management
  • -4 to 32 MHz crystal oscillator
  • -32 kHz oscillator for RTC with calibration
  • -Internal 8 MHz RC with x6 PLL option
  • -Internal 40 kHz RC oscillator
  • -Internal 48 MHz oscillator with automatic trimming based on ext. synchronization
  •  Up to 87 fast I/Os
  • -All mappable on external interrupt vectors
  • -Up to 68 I/Os with 5V tolerant capability and 19 with independent supply V DDIO2
  •  Seven-channel DMA controller
  •  One 12-bit, 1.0 μs ADC (up to 16 channels)
  • -Conversion range: 0 to 3.6 V
  • -Separate analog supply: 2.4 V to 3.6 V
  •  One 12-bit D/A converter (with 2 channels)
  •  Two fast low-power analog comparators with programmable input and output
  •  Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors

Pin Configuration

Figure 3. UFBGA100 package ballout (top view)

Figure 4. LQFP100 100-pin package pinout (top view)

42

Figure 5. UFBGA64 package ball-out (top view)

Figure 6. LQFP64 64-pin package pinout (top view)

Figure 7. LQFP48 48-pin package pinout (top view)

42

Figure 8. UFQFPN48 48-pin package pinout (top view)

Figure 9. WLCSP49 49-pin package ballout (bottom view)

Table 12. Legend/abbreviations used in the pinout table

Namebrackets actualDefinition below the pin name, the pin function during and pin nameAbbreviation Pin name Unless otherwise specified in after reset is the same as the
Supply pinSupply pintypetype
IpinInput only pinPin I/O Input / output
FT5 V tolerant I/O
FTf5 V tolerant I/O, FM+ capable
BOOT0pin with I/Os registersTTa B Dedicated RST
3.3 V tolerant I/O directly connected to ADCI/O structure
TCStandard 3.3 V I/O
Bidirectional reset pin embedded weak pull-up resistor
Unless otherwise specified by a note, all are set as floating inputs during and after reset.Notes Pin functions
Alternate functionsAlternate functionsFunctions selected through GPIOx_AFRFunctions selected through GPIOx_AFR
Additional functionsFunctions directly selected/enabled through peripheral registers
Additional functions
Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
B21----PE2I/OFT-TSC_G7_IO1, TIM3_ETR-
A12----PE3I/OFT-TSC_G7_IO2, TIM3_CH1-
B13----PE4I/OFT-TSC_G7_IO3, TIM3_CH2-
C24----PE5I/OFT-TSC_G7_IO4, TIM3_CH3-
D25----PE6I/OFT-TIM3_CH4WKUP3, RTC_TAMP3
E26B211B7VBATS--Backup power supplyBackup power supply

Table 13. STM32F072x8/xB pin definitions

42

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
C17A222D5PC13I/OTC(1) (2)-WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT
D18A133C7PC14- OSC32_IN (PC14)I/OTC(1) (2)-OSC32_IN
E19B144C6PC15- OSC32_OUT (PC15)I/OTC(1) (2)-OSC32_OUT
F210----PF9I/OFT-TIM15_CH1-
G211---PF10I/OFT-TIM15_CH2-
F112C155D7PF0-OSC_IN (PF0)I/OFT-CRS_ SYNCOSC_IN
G113D166D6PF1-OSC_OUT (PF1)I/OFT--OSC_OUT
H214E177E7NRSTI/ORST-Device reset input / internal reset output (active low)Device reset input / internal reset output (active low)
H115E38--PC0I/OTTa-EVENTOUTADC_IN10
J216E29--PC1I/OTTa-EVENTOUTADC_IN11
J317F210--PC2I/OTTa-SPI2_MISO, I2S2_MCK, EVENTOUTADC_IN12
K218G111--PC3I/OTTa-SPI2_MOSI, I2S2_SD, EVENTOUTADC_IN13
J119----PF2I/OFT-EVENTOUTWKUP8
K120F1128E6VSSAS--Analog groundAnalog ground
M121H1139F7VDDAS--Analog power supplyAnalog power supply
L122----PF3I/OFT-EVENTOUT
L223G21410F6PA0I/OTTa-USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TXRTC_ TAMP2, WKUP1, ADC_IN0, COMP1_INM6

Table 13. STM32F072x8/xB pin definitions (continued)

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
M224H21511G7PA1I/OTTa-USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUTADC_IN1, COMP1_INP
K325F31612E5PA2I/OTTa-USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3ADC_IN2, COMP2_INM6, WKUP4
L326G31713E4PA3I/OTTa-USART2_RX,TIM2_CH4, TIM15_CH2, TSC_G1_IO4ADC_IN3, COMP2_INP
D327C218--VSSS--GroundGround
H328D219--VDDS--Digital power supplyDigital power supply
M329H32014G6PA4I/OTTa-SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CKCOMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1
K430F42115F5PA5I/OTTa-SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2
L431G42216F4PA6I/OTTa-SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTSADC_IN6
M432H42317F3PA7I/OTTa-SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUTADC_IN7

Table 13. STM32F072x8/xB pin definitions (continued)

42

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
K533H524--PC4I/OTTa-EVENTOUT, USART3_TXADC_IN14
L534H625--PC5I/OTTa-TSC_G3_IO1, USART3_RXADC_IN15, WKUP5
M535F52618G5PB0I/OTTa-TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CKADC_IN8
M636G52719G4PB1I/OTTa-TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3ADC_IN9
L637G62820G3PB2I/OFT-TSC_G3_IO4-
M738----PE7I/OFT-TIM1_ETR-
L739----PE8I/OFT-TIM1_CH1N-
M840----PE9I/OFT-TIM1_CH1-
L841----PE10I/OFT-TIM1_CH2N-
M942----PE11I/OFT-TIM1_CH2-
L943----PE12I/OFT-SPI1_NSS, I2S1_WS, TIM1_CH3N-
M1044----PE13I/OFT-SPI1_SCK, I2S1_CK, TIM1_CH3-
M1145----PE14I/OFT-SPI1_MISO, I2S1_MCK, TIM1_CH4-
M1246----PE15I/OFT-SPI1_MOSI, I2S1_SD, TIM1_BKIN-
L1047G72921E3PB10I/OFT-SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3-
L1148H73022G2PB11I/OFT-USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA-
F1249D53123D3VSSS--GroundGround

Table 13. STM32F072x8/xB pin definitions (continued)

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
G1250E53224F2VDDS--Digital power supplyDigital power supply
L1251H83325E2PB12I/OFT-TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT-
K1252G83426G1PB13I/OFTf-SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3-
K1153F83527F1PB14I/OFTf-SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4-
K1054F73628E1PB15I/OFT-SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2WKUP7, RTC_REFIN
K955----PD8I/OFT-USART3_TX-
K856----PD9I/OFT-USART3_RX-
J1257----PD10I/OFT-USART3_CK-
J1158----PD11I/OFT-USART3_CTS-
J1059----PD12I/OFT-USART3_RTS, TSC_G8_IO1-
H1260----PD13I/OFT-TSC_G8_IO2-
H1161----PD14I/OFT-TSC_G8_IO3-
H1062----PD15I/OFT-TSC_G8_IO4, CRS_SYNC-
E1263F637--PC6I/OFT(3)TIM3_CH1-
E1164E738--PC7I/OFT(3)TIM3_CH2-
E1065E839--PC8I/OFT(3)TIM3_CH3-
D1266D840--PC9I/OFT(3)TIM3_CH4-

Table 13. STM32F072x8/xB pin definitions (continued)

42

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
D1167D74129D1PA8I/OFT(3)USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC-
D1068C74230D2PA9I/OFT(3)USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1-
C1269C64331C2PA10I/OFT(3)USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2-
B1270C84432C1PA11I/OFT(3)CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUTUSB_DM
A1271B84533C3PA12I/OFT(3)CAN_TX,USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUTUSB_DP
A1172A84634B3PA13I/OFT(3) (4)IR_OUT, SWDIO, USB_NOE-
C1173----PF6I/OFT(3)--
F1174D64735B1VSSS--GroundGround
G1175E64836B2VDDIO2S--Digital power supplyDigital power supply
A1076A74937A1PA14I/OFT(3) (4)USART2_TX, SWCLK-
A977A65038A2PA15I/OFT(3)SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT-
B1178B751--PC10I/OFT(3)USART3_TX, USART4_TX-

Table 13. STM32F072x8/xB pin definitions (continued)

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
C1079B652--PC11I/OFT(3)USART3_RX, USART4_RX-
B1080C553--PC12I/OFT(3)USART3_CK, USART4_CK-
C981----PD0I/OFT(3)SPI2_NSS, I2S2_WS, CAN_RX-
B982----PD1I/OFT(3)SPI2_SCK, I2S2_CK, CAN_TX-
C883B554--PD2I/OFT(3)USART3_RTS, TIM3_ETR-
B884----PD3I/OFT-SPI2_MISO, I2S2_MCK, USART2_CTS-
B785----PD4I/OFT-SPI2_MOSI, I2S2_SD, USART2_RTS-
A686----PD5I/OFT-USART2_TX-
B687----PD6I/OFT-USART2_RX-
A588----PD7I/OFT-USART2_CK-
A889A55539A3PB3I/OFT-SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT-
A790A45640A4PB4I/OFT-SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT-
C591C45741B4PB5I/OFT-SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2WKUP6
B592D35842C4PB6I/OFTf-I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_I03-

Table 13. STM32F072x8/xB pin definitions (continued)

42

Table 13. STM32F072x8/xB pin definitions (continued)

Pin numbersPin numbersPin numbersPin numbersPin numbersPin numbersPin functionsPin functions
UFBGA100LQFP100UFBGA64LQFP64LQFP48/UFQFPN48WLCSP49Pin name (function after reset)Pin typeI/O structureNotesAlternate functionsAdditional functions
B493C35943D4PB7I/OFTf-I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4-
A494B46044A5BOOT0IB-Boot memory selectionBoot memory selection
A395B36145B5PB8I/OFTf-I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX-
B396A36246C5PB9I/OFTf-SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX-
C397----PE0I/OFT-EVENTOUT, TIM16_CH1-
A298----PE1I/OFT-EVENTOUT, TIM17_CH1-
D399D46347A6VSSS--GroundGround
C4100E46448A7VDDS--Digital power supplyDigital power supply
  1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:  - The speed should not exceed 2 MHz with a maximum load of 30 pF. 
  • These GPIOs must not be used as current sources (e.g. to drive an LED).
  1. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.
  2. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os are supplied by VDDIO2.
  3. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated.

Table 14. Alternate functions selected through GPIOA_AFR registers for port A

Table 14. Alternate functions selected through GPIOA_AFR registers for port A

Pin nameAF0AF1AF2AF3AF4AF5AF6AF7
PA0-USART2_CTSTIM2_CH1_ETRTSC_G1_IO1USART4_TX--COMP1_OUT
PA1EVENTOUTUSART2_RTSTIM2_CH2TSC_G1_IO2USART4_RXTIM15_CH1N--
PA2TIM15_CH1USART2_TXTIM2_CH3TSC_G1_IO3---COMP2_OUT
PA3TIM15_CH2USART2_RXTIM2_CH4TSC_G1_IO4----
PA4SPI1_NSS, I2S1_WSUSART2_CK-TSC_G2_IO1TIM14_CH1---
PA5SPI1_SCK, I2S1_CKCECTIM2_CH1_ETRTSC_G2_IO2----
PA6SPI1_MISO, I2S1_MCKTIM3_CH1TIM1_BKINTSC_G2_IO3USART3_CTSTIM16_CH1EVENTOUTCOMP1_OUT
PA7SPI1_MOSI, I2S1_SDTIM3_CH2TIM1_CH1NTSC_G2_IO4TIM14_CH1TIM17_CH1EVENTOUTCOMP2_OUT
PA8MCOUSART1_CKTIM1_CH1EVENTOUTCRS_SYNC---
PA9TIM15_BKINUSART1_TXTIM1_CH2TSC_G4_IO1----
PA10TIM17_BKINUSART1_RXTIM1_CH3TSC_G4_IO2----
PA11EVENTOUTUSART1_CTSTIM1_CH4TSC_G4_IO3CAN_RX--COMP1_OUT
PA12EVENTOUTUSART1_RTSTIM1_ETRTSC_G4_IO4CAN_TX--COMP2_OUT
PA13SWDIOIR_OUTUSB_NOE-----
PA14SWCLKUSART2_TX------
PA15SPI1_NSS, I2S1_WSUSART2_RXTIM2_CH1_ETREVENTOUTUSART4_RTS---

Table 14. Alternate functions selected through GPIOA_AFR registers for port A

Table 15. Alternate functions selected through GPIOB_AFR registers for port B

Pin nameAF0AF1AF2AF3AF4AF5
PB0EVENTOUTTIM3_CH3TIM1_CH2NTSC_G3_IO2USART3_CK-
PB1TIM14_CH1TIM3_CH4TIM1_CH3NTSC_G3_IO3USART3_RTS-
PB2---TSC_G3_IO4--
PB3SPI1_SCK, I2S1_CKEVENTOUTTIM2_CH2TSC_G5_IO1--
PB4SPI1_MISO, I2S1_MCKTIM3_CH1EVENTOUTTSC_G5_IO2-TIM17_BKIN
PB5SPI1_MOSI, I2S1_SDTIM3_CH2TIM16_BKINI2C1_SMBA--
PB6USART1_TXI2C1_SCLTIM16_CH1NTSC_G5_IO3--
PB7USART1_RXI2C1_SDATIM17_CH1NTSC_G5_IO4USART4_CTS-
PB8CECI2C1_SCLTIM16_CH1TSC_SYNCCAN_RX-
PB9IR_OUTI2C1_SDATIM17_CH1EVENTOUTCAN_TXSPI2_NSS, I2S2_WS
PB10CECI2C2_SCLTIM2_CH3TSC_SYNCUSART3_TXSPI2_SCK, I2S2_CK
PB11EVENTOUTI2C2_SDATIM2_CH4TSC_G6_IO1USART3_RX-
PB12SPI2_NSS, I2S2_WSEVENTOUTTIM1_BKINTSC_G6_IO2USART3_CKTIM15_BKIN
PB13SPI2_SCK, I2S2_CK-TIM1_CH1NTSC_G6_IO3USART3_CTSI2C2_SCL
PB14SPI2_MISO, I2S2_MCKTIM15_CH1TIM1_CH2NTSC_G6_IO4USART3_RTSI2C2_SDA
PB15SPI2_MOSI, I2S2_SDTIM15_CH2TIM1_CH3NTIM15_CH1N--

Table 15. Alternate functions selected through GPIOB_AFR registers for port B

Table 16. Alternate functions selected through GPIOC_AFR registers for port C

Pin nameAF0AF1
PC0EVENTOUT-
PC1EVENTOUT-
PC2EVENTOUTSPI2_MISO, I2S2_MCK
PC3EVENTOUTSPI2_MOSI, I2S2_SD
PC4EVENTOUTUSART3_TX
PC5TSC_G3_IO1USART3_RX
PC6TIM3_CH1-
PC7TIM3_CH2-
PC8TIM3_CH3-
PC9TIM3_CH4-
PC10USART4_TXUSART3_TX
PC11USART4_RXUSART3_RX
PC12USART4_CKUSART3_CK
PC13--
PC14--
PC15--

Table 17. Alternate functions selected through GPIOD_AFR registers for port D

Pin nameAF0AF1
PD0CAN_RXSPI2_NSS, I2S2_WS
PD1CAN_TXSPI2_SCK, I2S2_CK
PD2TIM3_ETRUSART3_RTS
PD3USART2_CTSSPI2_MISO, I2S2_MCK
PD4USART2_RTSSPI2_MOSI, I2S2_SD
PD5USART2_TX-
PD6USART2_RX-
PD7USART2_CK-
PD8USART3_TX-
PD9USART3_RX-
PD10USART3_CK-
PD11USART3_CTS-
PD12USART3_RTSTSC_G8_IO1
PD13-TSC_G8_IO2
PD14-TSC_G8_IO3
PD15CRS_SYNCTSC_G8_IO4

46

Table 18. Alternate functions selected through GPIOE_AFR registers for port E

Pin nameAF0AF1
PE0TIM16_CH1EVENTOUT
PE1TIM17_CH1EVENTOUT
PE2TIM3_ETRTSC_G7_IO1
PE3TIM3_CH1TSC_G7_IO2
PE4TIM3_CH2TSC_G7_IO3
PE5TIM3_CH3TSC_G7_IO4
PE6TIM3_CH4-
PE7TIM1_ETR-
PE8TIM1_CH1N-
PE9TIM1_CH1-
PE10TIM1_CH2N-
PE11TIM1_CH2-
PE12TIM1_CH3NSPI1_NSS, I2S1_WS
PE13TIM1_CH3SPI1_SCK, I2S1_CK
PE14TIM1_CH4SPI1_MISO, I2S1_MCK
PE15TIM1_BKINSPI1_MOSI, I2S1_SD

Table 19. Alternate functions available on port F

Pin nameAF
PF0CRS_SYNC
PF1-
PF2EVENTOUT
PF3EVENTOUT
PF6-
PF9TIM15_CH1
PF10TIM15_CH2

Table 19. Alternate functions available on port F

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 24 and Table 55 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions .

Table 55. I/O AC characteristics (1)(2)

OSPEEDRy [1:0] value (1)SymbolParameterConditionsMinMaxUnit
x0f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-2MHz
x0t f(IO)outOutput fall timeC L = 50 pF, V DDIOx  2 V-125ns
x0t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-125ns
x0f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-1MHz
x0t f(IO)outOutput fall timeC L = 50 pF, V DDIOx  2 V-125ns
x0t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-125ns
01f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-10MHz
01t f(IO)outOutput fall timeC L = 50 pF, V DDIOx  2 V-25ns
01t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-25ns
01f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-4MHz
01t f(IO)outOutput fall timeC L = 50 pF, V DDIOx  2 V-62.5ns
01t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-62.5ns
11f max(IO)outMaximum frequency (3)C L = 30 pF, V DDIOx  2.7 V-50MHz
11f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2.7 V-30MHz
11f max(IO)outMaximum frequency (3)C L = 50 pF, 2 V  V DDIOx  2.7 V-20MHz
11f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-10MHz
f(IO)out Output fall timeC L = 30 pF, V DDIOx  2.7 V-5
f(IO)out Output fall timeC L = 50 pF, V DDIOx  2.7 V-8
tf(IO)out Output fall timeC L = 50 pF, 2 V  V DDIOx  2.7 V-12
f(IO)out Output fall timeC L = 50 pF, V DDIOx  2 V-25
t r(IO)outOutput rise timeC L = 30 pF, V DDIOx  2.7 V-5ns
t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2.7 V-8ns
t r(IO)outOutput rise timeC L = 50 pF, 2 V  V DDIOx  2.7 V-12ns
t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-25ns

Table 55. I/O AC characteristics (1)(2)

105

Table 55. I/O AC characteristics (1)(2) (continued)

OSPEEDRy [1:0] value (1)SymbolParameterConditionsMinMaxUnit
Fm+ configuration (4)f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-2MHz
Fm+ configuration (4)t f(IO)outOutput fall timeC L = 50 pF, V DDIOx  2 V-12ns
Fm+ configuration (4)t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-34ns
Fm+ configuration (4)f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx  2 V-0.5MHz
Fm+ configuration (4)t f(IO)outOutput fall timeC L = 50 pF, V DDIOx  2 V-16ns
Fm+ configuration (4)t r(IO)outOutput rise timeC L = 50 pF, V DDIOx  2 V-44ns
-t EXTIpwPulse width of external signals detected by the EXTI controller-10-ns
  1. Guaranteed by design, not tested in production.
  2. The maximum frequency is defined in Figure 24 .
  3. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.

Figure 24. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics , Table 22: Current characteristics and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 21. Voltage characteristics (1)

SymbolRatingsMinMaxUnit
V DD -V SSExternal main supply voltage-0.34.0V
V DDIO2 -V SSExternal I/O supply voltage-0.34.0V
V DDA -V SSExternal analog supply voltage-0.34.0V
V DD -V DDAAllowed voltage difference for V DD > V DDA-0.4V
V BAT -V SSExternal backup supply voltage-0.34.0V
V IN (2)Input voltage on FT and FTf pinsV SS  0.3V DDIOx + 4.0 (3)V
V IN (2)Input voltage on TTa pinsV SS  0.34.0V
V IN (2)BOOT009.0V
V IN (2)Input voltage on any other pinV SS  0.34.0V
|  V DDx |Variations between different V DD power pins-50mV
|V SSx  V SS |Variations between all the different ground pins-50mV
V ESD(HBM)Electrostatic discharge voltage  (human body model)see Section 6.3.12: Electrical sensitivity characteristicssee Section 6.3.12: Electrical sensitivity characteristics

105

Table 22. Current characteristics

SymbolRatingsMax.Unit
 I VDDTotal current into sum of all VDDpower lines (source) (1)120mA
 I VSSTotal current out of sum of all VSS ground lines (sink) (1)-120mA
I VDD(PIN)Maximum current into each VDD power pin (source) (1)100mA
I VSS(PIN)Maximum current out of each VSS ground pin (sink) (1)-100mA
I IO(PIN)Output current sunk by any I/O and control pin25mA
I IO(PIN)Output current source by any I/O and control pin-25mA
 I IO(PIN)Total output current sunk by sum of all I/Os and control pins (2)80mA
 I IO(PIN)Total output current sourced by sum of all I/Os and control pins (2)-80mA
 I IO(PIN)Total output current sourced by sum of all I/Os supplied by VDDIO2-40mA
I INJ(PIN) (3)Injected current on B, FT and FTf pins-5/+0 (4)mA
I INJ(PIN) (3)Injected current on TC and RST pin± 5mA
I INJ(PIN) (3)Injected current on TTa pins (5)± 5mA
 I INJ(PIN)Total injected current (sum of all I/O and control pins) (6)± 25mA
  1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
  2. A positive injection is induced by V IN > V DDIOx while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
  3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  4. On these I/Os, a positive injection is induced by V IN > V DDA . Negative injection disturbs the analog performance of the device. See note (2) below Table 59: ADC accuracy .
  5. When several inputs are submitted to a current injection, the maximum  I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 23. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

Table 23. Thermal characteristics

Thermal Information

The maximum chip junction temperature (T J max) must never exceed the values given in Table 24: General operating conditions .

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:T _ { J } max = T _ { A } max + ( P _ { D } max × Θ _ { J A } )$

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.

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