STM32F072RBT6
ARM®-based 32-bit MCUThe STM32F072RBT6 is a arm®-based 32-bit mcu from STMicroelectronics. View the full STM32F072RBT6 datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.
Key Specifications
| Parameter | Value |
|---|---|
| Connectivity | CANbus, HDMI-CEC, I2C, IrDA, LINbus, SPI, UART/USART, USB |
| Core Processor | ARM® Cortex®-M0 |
| Core Size | 32-Bit |
| Data Converters | A/D 19x12b; D/A 1x12b |
| DigiKey Programmable | Not Verified |
| DigiKey Programmable | Not Verified |
| DigiKey Programmable | Not Verified |
| Mounting Type | Surface Mount |
| Number of I/O | 51 |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Oscillator Type | Internal |
| Oscillator Type | Internal |
| Oscillator Type | Internal |
| Package / Case | 64-LQFP |
| Peripherals | DMA, I2S, POR, PWM, WDT |
| Flash Memory Size | 128KB (128K x 8) |
| Program Memory Type | FLASH |
| RAM Size | 16K x 8 B |
| Clock Speed | 48MHz |
| Supplier Device Package | 64-LQFP (10x10) |
| Supplier Device Package | 64-LQFP (10x10) |
| Supplier Device Package | 64-LQFP (10x10) |
| Supply Voltage | 1.65V ~ 3.6V |
Overview
Part: STM32F072x8 STM32F072xB
Type: ARM®-based 32-bit MCU
Description: ARM®-based 32-bit MCU with a Cortex®-M0 CPU up to 48 MHz, featuring up to 128 KB Flash, 16 KB SRAM, crystal-less USB FS 2.0, CAN, 12 timers, 12-bit ADC, 12-bit DAC, and various communication interfaces, operating from 2.0 V to 3.6 V.
Operating Conditions:
- Supply voltage: 2.0 V to 3.6 V
- Operating temperature: -40 to +105 °C (Junction)
- Max CPU frequency: 48 MHz
Absolute Maximum Ratings:
- Max supply voltage: 4.0 V
- Max junction/storage temperature: +150 °C
Key Specs:
- Core: ARM® 32-bit Cortex®-M0 CPU
- Max CPU frequency: 48 MHz
- Flash memory: 64 to 128 Kbytes
- SRAM: 16 Kbytes
- ADC resolution: 12-bit, 1.0 μs
- DAC resolution: 12-bit, 2 channels
- I2C interface speed: 1 Mbit/s (Fast Mode Plus)
- SPI interface speed: 18 Mbit/s
- Run mode current consumption: 12.5 mA (Typ. @ 48 MHz, HSI, VDD=3.6V, TA=25°C)
Features:
- Crystal-less USB 2.0 full-speed interface with BCD and LPM support
- Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors
- Two I2C interfaces supporting Fast Mode Plus (1 Mbit/s)
- Four USARTs with master synchronous SPI and modem control
- CAN interface
- 12 timers including advanced-control, general-purpose, and watchdog timers
- Seven-channel DMA controller
- Serial wire debug (SWD)
Package:
- UFQFPN48 7x7 mm
- LQFP100 14x14 mm
- LQFP64 10x10 mm
- LQFP48 7x7 mm
- UFBGA100 7x7 mm
- UFBGA64 5x5 mm
- WLCSP49 3.277x3.109 mm
Features
- Core: ARM ® 32-bit Cortex ® -M0 CPU, frequency up to 48 MHz
- Memories
- -64 to 128 Kbytes of Flash memory
- -16 Kbytes of SRAM with HW parity
- CRC calculation unit
- Reset and power management
- -Digital and I/O supply: V DD = 2.0 V to 3.6 V
- -Analog supply: V DDA = V DD to 3.6 V
- -Selected I/Os: V DDIO2 = 1.65 V to 3.6 V
- -Power-on/Power down reset (POR/PDR)
- -Programmable voltage detector (PVD)
- -Low power modes: Sleep, Stop, Standby
- -VBAT supply for RTC and backup registers
- Clock management
- -4 to 32 MHz crystal oscillator
- -32 kHz oscillator for RTC with calibration
- -Internal 8 MHz RC with x6 PLL option
- -Internal 40 kHz RC oscillator
- -Internal 48 MHz oscillator with automatic trimming based on ext. synchronization
- Up to 87 fast I/Os
- -All mappable on external interrupt vectors
- -Up to 68 I/Os with 5V tolerant capability and 19 with independent supply V DDIO2
- Seven-channel DMA controller
- One 12-bit, 1.0 μs ADC (up to 16 channels)
- -Conversion range: 0 to 3.6 V
- -Separate analog supply: 2.4 V to 3.6 V
- One 12-bit D/A converter (with 2 channels)
- Two fast low-power analog comparators with programmable input and output
- Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors
Pin Configuration
STM32F072RBT6 LQFP-64 Pinout
| Pin | Name | Type | I/O Structure | Description |
|---|---|---|---|---|
| 1 | VBAT | S | - | Backup power supply |
| 2 | PC13 | I/O | TC | GPIO; WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT |
| 3 | PC14-OSC32_IN | I/O | TC | GPIO (OSC32_IN) |
| 4 | PC15-OSC32_OUT | I/O | TC | GPIO (OSC32_OUT) |
| 5 | PF0-OSC_IN | I/O | FT | GPIO (OSC_IN); CRS_SYNC |
| 6 | PF1-OSC_OUT | I/O | FT | GPIO (OSC_OUT) |
| 7 | NRST | I/O | RST | Device reset input / internal reset output (active low) |
| 8 | PC0 | I/O | TTa | GPIO; EVENTOUT; ADC_IN10 |
| 9 | PC1 | I/O | TTa | GPIO; EVENTOUT; ADC_IN11 |
| 10 | PC2 | I/O | TTa | GPIO; SPI2_MISO, I2S2_MCK, EVENTOUT; ADC_IN12 |
| 11 | PC3 | I/O | TTa | GPIO; SPI2_MOSI, I2S2_SD, EVENTOUT; ADC_IN13 |
| 12 | VSSA | S | - | Analog ground |
| 13 | VDDA | S | - | Analog power supply |
| 14 | PA0 | I/O | TTa | GPIO; USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TX; RTC_TAMP2, WKUP1, ADC_IN0, COMP1_INM6 |
| 15 | PA1 | I/O | TTa | GPIO; USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT; ADC_IN1, COMP1_INP |
| 16 | PA2 | I/O | TTa | GPIO; USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3; ADC_IN2, COMP2_INM6, WKUP4 |
| 17 | PA3 | I/O | TTa | GPIO; USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4; ADC_IN3, COMP2_INP |
| 18 | VSS | S | - | Ground |
| 19 | VDD | S | - | Digital power supply |
| 20 | PA4 | I/O | TTa | GPIO; SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK; COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1 |
| 21 | PA5 | I/O | TTa | GPIO; SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2; COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2 |
| 22 | PA6 | I/O | TTa | GPIO; SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS; ADC_IN6 |
| 23 | PA7 | I/O | TTa | GPIO; SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT; ADC_IN7 |
| 24 | PC4 | I/O | TTa | GPIO; EVENTOUT, USART3_TX; ADC_IN14 |
| 25 | PC5 | I/O | TTa | GPIO; TSC_G3_IO1, USART3_RX; ADC_IN15, WKUP5 |
| 26 | PB0 | I/O | TTa | GPIO; TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK; ADC_IN8 |
| 27 | PB1 | I/O | TTa | GPIO; TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3; ADC_IN9 |
| 28 | PB2 | I/O | FT | GPIO; TSC_G3_IO4 |
| 29 | PB10 | I/O | FT | GPIO; SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3 |
| 30 | PB11 | I/O | FT | GPIO; USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA |
| 31 | VSS | S | - | Ground |
| 32 | VDD | S | - | Digital power supply |
| 33 | PB12 | I/O | FT | GPIO; TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT |
| 34 | PB13 | I/O | FTf | GPIO; SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3 |
| 35 | PB14 | I/O | FTf | GPIO; SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4 |
| 36 | PB15 | I/O | FT | GPIO; SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2; WKUP7, RTC_REFIN |
| 37 | PC6 | I/O | FT | GPIO; TIM3_CH1 |
| 38 | PC7 | I/O | FT | GPIO; TIM3_CH2 |
| 39 | PC8 | I/O | FT | GPIO; TIM3_CH3 |
| 40 | PC9 | I/O | FT | GPIO; TIM3_CH4 |
| 41 | PA8 | I/O | FT | GPIO; USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC |
| 42 | PA9 | I/O | FT | GPIO; USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1 |
| 43 | PA10 | I/O | FT | GPIO; USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2 |
| 44 | PA11 | I/O | FT | GPIO; CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT; USB_DM |
| 45 | PA12 | I/O | FT | GPIO; CAN_TX, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT; USB_DP |
| 46 | PA13 | I/O | FT | GPIO; IR_OUT, SWDIO, USB_NOE |
| 47 | VSS | S | - | Ground |
| 48 | VDDIO2 | S | - | Digital power supply (I/O bank 2) |
| 49 | PA14 | I/O | FT | GPIO; USART2_TX, SWCLK |
| 50 | PA15 | I/O | FT | GPIO; SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT |
| 51 | PC10 | I/O | FT | GPIO; USART3_TX, USART4_TX |
| 52 | PC11 | I/O | FT | GPIO; USART3_RX, USART4_RX |
| 53 | PC12 | I/O | FT | GPIO; USART3_CK, USART4_CK |
| 54 | PD2 | I/O | FT | GPIO; USART3_RTS, TIM3_ETR |
| 55 | PB3 | I/O | FT | GPIO; SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT |
| 56 | PB4 | I/O | FT | GPIO; SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT |
| 57 | PB5 | I/O | FT | GPIO; SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2; WKUP6 |
| 58 | PB6 | I/O | FTf | GPIO; I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3 |
| 59 | PB7 | I/O | FTf | GPIO; I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4 |
| 60 | BOOT0 | I | B | Boot memory selection |
| 61 | PB8 | I/O | FTf | GPIO; I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX |
| 62 | PB9 | I/O | FTf | GPIO; SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX |
| 63 | VSS | S | - | Ground |
| 64 | VDD | S | - | Digital power supply |
Notes
- PC13, PC14, PC15: Limited output capability (3 mA max sink current). Speed limited to 2 MHz with max 30 pF load. Must not be used as current sources. Operate as GPIOs after first RTC domain power-up; function depends on RTC register content.
- VDDIO2 (Pin 48): Separate power supply for I/O bank 2 (pins PC6-PC9, PA8-PA15, PC10-PC12, PD2).
- PA13, PA14: Configured as SWDIO and SWCLK after reset with internal pull-up (PA13) and pull-down (PA14) activated.
- FT pins: 5V-tolerant I/O.
- FTf pins: 5V-tolerant I/O with FM+ (Fast Mode Plus) I2C capability.
- TTa pins: 3.3V-tolerant I/O with direct ADC connection capability.
- TC pins: Standard 3.3V I/O with embedded weak pull-up (RTC domain).
Electrical Characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and Table 55 , respectively.
Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions .
Table 55. I/O AC characteristics (1)(2)
| OSPEEDRy [1:0] value (1) | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| x0 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 2 | MHz |
| x0 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| x0 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| x0 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 1 | MHz |
| x0 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| x0 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 125 | ns |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 10 | MHz |
| 01 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 25 | ns |
| 01 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 25 | ns |
| 01 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 4 | MHz |
| 01 | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 62.5 | ns |
| 01 | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 62.5 | ns |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 30 pF, V DDIOx 2.7 V | - | 50 | MHz |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2.7 V | - | 30 | MHz |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, 2 V V DDIOx 2.7 V | - | 20 | MHz |
| 11 | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 10 | MHz |
| f(IO)out Output fall time | C L = 30 pF, V DDIOx 2.7 V | - | 5 | |||
| f(IO)out Output fall time | C L = 50 pF, V DDIOx 2.7 V | - | 8 | |||
| t | f(IO)out Output fall time | C L = 50 pF, 2 V V DDIOx 2.7 V | - | 12 | ||
| f(IO)out Output fall time | C L = 50 pF, V DDIOx 2 V | - | 25 | |||
| t r(IO)out | Output rise time | C L = 30 pF, V DDIOx 2.7 V | - | 5 | ns | |
| t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2.7 V | - | 8 | ns | |
| t r(IO)out | Output rise time | C L = 50 pF, 2 V V DDIOx 2.7 V | - | 12 | ns | |
| t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 25 | ns |
Table 55. I/O AC characteristics (1)(2)
105
Table 55. I/O AC characteristics (1)(2) (continued)
| OSPEEDRy [1:0] value (1) | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| Fm+ configuration (4) | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 2 | MHz |
| Fm+ configuration (4) | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 12 | ns |
| Fm+ configuration (4) | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 34 | ns |
| Fm+ configuration (4) | f max(IO)out | Maximum frequency (3) | C L = 50 pF, V DDIOx 2 V | - | 0.5 | MHz |
| Fm+ configuration (4) | t f(IO)out | Output fall time | C L = 50 pF, V DDIOx 2 V | - | 16 | ns |
| Fm+ configuration (4) | t r(IO)out | Output rise time | C L = 50 pF, V DDIOx 2 V | - | 44 | ns |
| - | t EXTIpw | Pulse width of external signals detected by the EXTI controller | - | 10 | - | ns |
- Guaranteed by design, not tested in production.
- The maximum frequency is defined in Figure 24 .
- When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.
Figure 24. I/O AC characteristics definition
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics , Table 22: Current characteristics and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 21. Voltage characteristics (1)
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DD -V SS | External main supply voltage | -0.3 | 4.0 | V |
| V DDIO2 -V SS | External I/O supply voltage | -0.3 | 4.0 | V |
| V DDA -V SS | External analog supply voltage | -0.3 | 4.0 | V |
| V DD -V DDA | Allowed voltage difference for V DD > V DDA | - | 0.4 | V |
| V BAT -V SS | External backup supply voltage | -0.3 | 4.0 | V |
| V IN (2) | Input voltage on FT and FTf pins | V SS 0.3 | V DDIOx + 4.0 (3) | V |
| V IN (2) | Input voltage on TTa pins | V SS 0.3 | 4.0 | V |
| V IN (2) | BOOT0 | 0 | 9.0 | V |
| V IN (2) | Input voltage on any other pin | V SS 0.3 | 4.0 | V |
| \ | V DDx \ | Variations between different V DD power pins | - | |
| \ | V SSx V SS \ | Variations between all the different ground pins | - | |
| V ESD(HBM) | Electrostatic discharge voltage (human body model) | see Section 6.3.12: Electrical sensitivity characteristics | see Section 6.3.12: Electrical sensitivity characteristics |
105
Table 22. Current characteristics
| Symbol | Ratings | Max. | Unit |
|---|---|---|---|
| I VDD | Total current into sum of all VDDpower lines (source) (1) | 120 | mA |
| I VSS | Total current out of sum of all VSS ground lines (sink) (1) | -120 | mA |
| I VDD(PIN) | Maximum current into each VDD power pin (source) (1) | 100 | mA |
| I VSS(PIN) | Maximum current out of each VSS ground pin (sink) (1) | -100 | mA |
| I IO(PIN) | Output current sunk by any I/O and control pin | 25 | mA |
| I IO(PIN) | Output current source by any I/O and control pin | -25 | mA |
| I IO(PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 80 | mA |
| I IO(PIN) | Total output current sourced by sum of all I/Os and control pins (2) | -80 | mA |
| I IO(PIN) | Total output current sourced by sum of all I/Os supplied by VDDIO2 | -40 | mA |
| I INJ(PIN) (3) | Injected current on B, FT and FTf pins | -5/+0 (4) | mA |
| I INJ(PIN) (3) | Injected current on TC and RST pin | ± 5 | mA |
| I INJ(PIN) (3) | Injected current on TTa pins (5) | ± 5 | mA |
| I INJ(PIN) | Total injected current (sum of all I/O and control pins) (6) | ± 25 | mA |
- This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
- A positive injection is induced by V IN > V DDIOx while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- On these I/Os, a positive injection is induced by V IN > V DDA . Negative injection disturbs the analog performance of the device. See note (2) below Table 59: ADC accuracy .
- When several inputs are submitted to a current injection, the maximum I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).
Table 23. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 150 | °C |
Table 23. Thermal characteristics
Thermal Information
The maximum chip junction temperature (T J max) must never exceed the values given in Table 24: General operating conditions .
The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:T _ { J } max = T _ { A } max + ( P _ { D } max × Θ _ { J A } )
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32F072C8 | STMicroelectronics | — |
| STM32F072CB | STMicroelectronics | — |
| STM32F072CX | STMicroelectronics | — |
| STM32F072R8 | STMicroelectronics | — |
| STM32F072RB | STMicroelectronics | — |
| STM32F072RX | STMicroelectronics | — |
| STM32F072V8 | STMicroelectronics | — |
| STM32F072VB | STMicroelectronics | — |
| STM32F072VX | STMicroelectronics | — |
| STM32F072X8 | STMicroelectronics | — |
| STM32F072X8/XB | STMicroelectronics | — |
| STM32F072XB | STMicroelectronics | — |
| STM32F072XX | STMicroelectronics | — |
Get structured datasheet data via API
Get started free