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STM32F072RBT6

ARM®-based 32-bit MCU

The STM32F072RBT6 is a arm®-based 32-bit mcu from STMicroelectronics. View the full STM32F072RBT6 datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Package

64-LQFP

Key Specifications

ParameterValue
ConnectivityCANbus, HDMI-CEC, I2C, IrDA, LINbus, SPI, UART/USART, USB
Core ProcessorARM® Cortex®-M0
Core Size32-Bit
Data ConvertersA/D 19x12b; D/A 1x12b
DigiKey ProgrammableNot Verified
DigiKey ProgrammableNot Verified
DigiKey ProgrammableNot Verified
Mounting TypeSurface Mount
Number of I/O51
Operating Temperature-40°C ~ 85°C (TA)
Oscillator TypeInternal
Oscillator TypeInternal
Oscillator TypeInternal
Package / Case64-LQFP
PeripheralsDMA, I2S, POR, PWM, WDT
Flash Memory Size128KB (128K x 8)
Program Memory TypeFLASH
RAM Size16K x 8 B
Clock Speed48MHz
Supplier Device Package64-LQFP (10x10)
Supplier Device Package64-LQFP (10x10)
Supplier Device Package64-LQFP (10x10)
Supply Voltage1.65V ~ 3.6V

Overview

Part: STM32F072x8 STM32F072xB

Type: ARM®-based 32-bit MCU

Description: ARM®-based 32-bit MCU with a Cortex®-M0 CPU up to 48 MHz, featuring up to 128 KB Flash, 16 KB SRAM, crystal-less USB FS 2.0, CAN, 12 timers, 12-bit ADC, 12-bit DAC, and various communication interfaces, operating from 2.0 V to 3.6 V.

Operating Conditions:

  • Supply voltage: 2.0 V to 3.6 V
  • Operating temperature: -40 to +105 °C (Junction)
  • Max CPU frequency: 48 MHz

Absolute Maximum Ratings:

  • Max supply voltage: 4.0 V
  • Max junction/storage temperature: +150 °C

Key Specs:

  • Core: ARM® 32-bit Cortex®-M0 CPU
  • Max CPU frequency: 48 MHz
  • Flash memory: 64 to 128 Kbytes
  • SRAM: 16 Kbytes
  • ADC resolution: 12-bit, 1.0 μs
  • DAC resolution: 12-bit, 2 channels
  • I2C interface speed: 1 Mbit/s (Fast Mode Plus)
  • SPI interface speed: 18 Mbit/s
  • Run mode current consumption: 12.5 mA (Typ. @ 48 MHz, HSI, VDD=3.6V, TA=25°C)

Features:

  • Crystal-less USB 2.0 full-speed interface with BCD and LPM support
  • Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors
  • Two I2C interfaces supporting Fast Mode Plus (1 Mbit/s)
  • Four USARTs with master synchronous SPI and modem control
  • CAN interface
  • 12 timers including advanced-control, general-purpose, and watchdog timers
  • Seven-channel DMA controller
  • Serial wire debug (SWD)

Package:

  • UFQFPN48 7x7 mm
  • LQFP100 14x14 mm
  • LQFP64 10x10 mm
  • LQFP48 7x7 mm
  • UFBGA100 7x7 mm
  • UFBGA64 5x5 mm
  • WLCSP49 3.277x3.109 mm

Features

  • Core: ARM ® 32-bit Cortex ® -M0 CPU, frequency up to 48 MHz
  • Memories
  • -64 to 128 Kbytes of Flash memory
  • -16 Kbytes of SRAM with HW parity
  • CRC calculation unit
  • Reset and power management
  • -Digital and I/O supply: V DD = 2.0 V to 3.6 V
  • -Analog supply: V DDA = V DD to 3.6 V
  • -Selected I/Os: V DDIO2 = 1.65 V to 3.6 V
  • -Power-on/Power down reset (POR/PDR)
  • -Programmable voltage detector (PVD)
  • -Low power modes: Sleep, Stop, Standby
  • -VBAT supply for RTC and backup registers
  • Clock management
  • -4 to 32 MHz crystal oscillator
  • -32 kHz oscillator for RTC with calibration
  • -Internal 8 MHz RC with x6 PLL option
  • -Internal 40 kHz RC oscillator
  • -Internal 48 MHz oscillator with automatic trimming based on ext. synchronization
  • Up to 87 fast I/Os
  • -All mappable on external interrupt vectors
  • -Up to 68 I/Os with 5V tolerant capability and 19 with independent supply V DDIO2
  • Seven-channel DMA controller
  • One 12-bit, 1.0 μs ADC (up to 16 channels)
  • -Conversion range: 0 to 3.6 V
  • -Separate analog supply: 2.4 V to 3.6 V
  • One 12-bit D/A converter (with 2 channels)
  • Two fast low-power analog comparators with programmable input and output
  • Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors

Pin Configuration

STM32F072RBT6 LQFP-64 Pinout

PinNameTypeI/O StructureDescription
1VBATS-Backup power supply
2PC13I/OTCGPIO; WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT
3PC14-OSC32_INI/OTCGPIO (OSC32_IN)
4PC15-OSC32_OUTI/OTCGPIO (OSC32_OUT)
5PF0-OSC_INI/OFTGPIO (OSC_IN); CRS_SYNC
6PF1-OSC_OUTI/OFTGPIO (OSC_OUT)
7NRSTI/ORSTDevice reset input / internal reset output (active low)
8PC0I/OTTaGPIO; EVENTOUT; ADC_IN10
9PC1I/OTTaGPIO; EVENTOUT; ADC_IN11
10PC2I/OTTaGPIO; SPI2_MISO, I2S2_MCK, EVENTOUT; ADC_IN12
11PC3I/OTTaGPIO; SPI2_MOSI, I2S2_SD, EVENTOUT; ADC_IN13
12VSSAS-Analog ground
13VDDAS-Analog power supply
14PA0I/OTTaGPIO; USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TX; RTC_TAMP2, WKUP1, ADC_IN0, COMP1_INM6
15PA1I/OTTaGPIO; USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT; ADC_IN1, COMP1_INP
16PA2I/OTTaGPIO; USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3; ADC_IN2, COMP2_INM6, WKUP4
17PA3I/OTTaGPIO; USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4; ADC_IN3, COMP2_INP
18VSSS-Ground
19VDDS-Digital power supply
20PA4I/OTTaGPIO; SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK; COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1
21PA5I/OTTaGPIO; SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2; COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2
22PA6I/OTTaGPIO; SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS; ADC_IN6
23PA7I/OTTaGPIO; SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT; ADC_IN7
24PC4I/OTTaGPIO; EVENTOUT, USART3_TX; ADC_IN14
25PC5I/OTTaGPIO; TSC_G3_IO1, USART3_RX; ADC_IN15, WKUP5
26PB0I/OTTaGPIO; TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK; ADC_IN8
27PB1I/OTTaGPIO; TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3; ADC_IN9
28PB2I/OFTGPIO; TSC_G3_IO4
29PB10I/OFTGPIO; SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3
30PB11I/OFTGPIO; USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA
31VSSS-Ground
32VDDS-Digital power supply
33PB12I/OFTGPIO; TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT
34PB13I/OFTfGPIO; SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3
35PB14I/OFTfGPIO; SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4
36PB15I/OFTGPIO; SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2; WKUP7, RTC_REFIN
37PC6I/OFTGPIO; TIM3_CH1
38PC7I/OFTGPIO; TIM3_CH2
39PC8I/OFTGPIO; TIM3_CH3
40PC9I/OFTGPIO; TIM3_CH4
41PA8I/OFTGPIO; USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC
42PA9I/OFTGPIO; USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1
43PA10I/OFTGPIO; USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2
44PA11I/OFTGPIO; CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT; USB_DM
45PA12I/OFTGPIO; CAN_TX, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT; USB_DP
46PA13I/OFTGPIO; IR_OUT, SWDIO, USB_NOE
47VSSS-Ground
48VDDIO2S-Digital power supply (I/O bank 2)
49PA14I/OFTGPIO; USART2_TX, SWCLK
50PA15I/OFTGPIO; SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT
51PC10I/OFTGPIO; USART3_TX, USART4_TX
52PC11I/OFTGPIO; USART3_RX, USART4_RX
53PC12I/OFTGPIO; USART3_CK, USART4_CK
54PD2I/OFTGPIO; USART3_RTS, TIM3_ETR
55PB3I/OFTGPIO; SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT
56PB4I/OFTGPIO; SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT
57PB5I/OFTGPIO; SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2; WKUP6
58PB6I/OFTfGPIO; I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3
59PB7I/OFTfGPIO; I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4
60BOOT0IBBoot memory selection
61PB8I/OFTfGPIO; I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX
62PB9I/OFTfGPIO; SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX
63VSSS-Ground
64VDDS-Digital power supply

Notes

  • PC13, PC14, PC15: Limited output capability (3 mA max sink current). Speed limited to 2 MHz with max 30 pF load. Must not be used as current sources. Operate as GPIOs after first RTC domain power-up; function depends on RTC register content.
  • VDDIO2 (Pin 48): Separate power supply for I/O bank 2 (pins PC6-PC9, PA8-PA15, PC10-PC12, PD2).
  • PA13, PA14: Configured as SWDIO and SWCLK after reset with internal pull-up (PA13) and pull-down (PA14) activated.
  • FT pins: 5V-tolerant I/O.
  • FTf pins: 5V-tolerant I/O with FM+ (Fast Mode Plus) I2C capability.
  • TTa pins: 3.3V-tolerant I/O with direct ADC connection capability.
  • TC pins: Standard 3.3V I/O with embedded weak pull-up (RTC domain).

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 24 and Table 55 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions .

Table 55. I/O AC characteristics (1)(2)

OSPEEDRy [1:0] value (1)SymbolParameterConditionsMinMaxUnit
x0f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-2MHz
x0t f(IO)outOutput fall timeC L = 50 pF, V DDIOx 2 V-125ns
x0t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-125ns
x0f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-1MHz
x0t f(IO)outOutput fall timeC L = 50 pF, V DDIOx 2 V-125ns
x0t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-125ns
01f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-10MHz
01t f(IO)outOutput fall timeC L = 50 pF, V DDIOx 2 V-25ns
01t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-25ns
01f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-4MHz
01t f(IO)outOutput fall timeC L = 50 pF, V DDIOx 2 V-62.5ns
01t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-62.5ns
11f max(IO)outMaximum frequency (3)C L = 30 pF, V DDIOx 2.7 V-50MHz
11f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2.7 V-30MHz
11f max(IO)outMaximum frequency (3)C L = 50 pF, 2 V V DDIOx 2.7 V-20MHz
11f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-10MHz
f(IO)out Output fall timeC L = 30 pF, V DDIOx 2.7 V-5
f(IO)out Output fall timeC L = 50 pF, V DDIOx 2.7 V-8
tf(IO)out Output fall timeC L = 50 pF, 2 V V DDIOx 2.7 V-12
f(IO)out Output fall timeC L = 50 pF, V DDIOx 2 V-25
t r(IO)outOutput rise timeC L = 30 pF, V DDIOx 2.7 V-5ns
t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2.7 V-8ns
t r(IO)outOutput rise timeC L = 50 pF, 2 V V DDIOx 2.7 V-12ns
t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-25ns

Table 55. I/O AC characteristics (1)(2)

105

Table 55. I/O AC characteristics (1)(2) (continued)

OSPEEDRy [1:0] value (1)SymbolParameterConditionsMinMaxUnit
Fm+ configuration (4)f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-2MHz
Fm+ configuration (4)t f(IO)outOutput fall timeC L = 50 pF, V DDIOx 2 V-12ns
Fm+ configuration (4)t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-34ns
Fm+ configuration (4)f max(IO)outMaximum frequency (3)C L = 50 pF, V DDIOx 2 V-0.5MHz
Fm+ configuration (4)t f(IO)outOutput fall timeC L = 50 pF, V DDIOx 2 V-16ns
Fm+ configuration (4)t r(IO)outOutput rise timeC L = 50 pF, V DDIOx 2 V-44ns
-t EXTIpwPulse width of external signals detected by the EXTI controller-10-ns
  1. Guaranteed by design, not tested in production.
  2. The maximum frequency is defined in Figure 24 .
  3. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.

Figure 24. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics , Table 22: Current characteristics and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 21. Voltage characteristics (1)

SymbolRatingsMinMaxUnit
V DD -V SSExternal main supply voltage-0.34.0V
V DDIO2 -V SSExternal I/O supply voltage-0.34.0V
V DDA -V SSExternal analog supply voltage-0.34.0V
V DD -V DDAAllowed voltage difference for V DD > V DDA-0.4V
V BAT -V SSExternal backup supply voltage-0.34.0V
V IN (2)Input voltage on FT and FTf pinsV SS 0.3V DDIOx + 4.0 (3)V
V IN (2)Input voltage on TTa pinsV SS 0.34.0V
V IN (2)BOOT009.0V
V IN (2)Input voltage on any other pinV SS 0.34.0V
\V DDx \Variations between different V DD power pins-
\V SSx V SS \Variations between all the different ground pins-
V ESD(HBM)Electrostatic discharge voltage (human body model)see Section 6.3.12: Electrical sensitivity characteristicssee Section 6.3.12: Electrical sensitivity characteristics

105

Table 22. Current characteristics

SymbolRatingsMax.Unit
I VDDTotal current into sum of all VDDpower lines (source) (1)120mA
I VSSTotal current out of sum of all VSS ground lines (sink) (1)-120mA
I VDD(PIN)Maximum current into each VDD power pin (source) (1)100mA
I VSS(PIN)Maximum current out of each VSS ground pin (sink) (1)-100mA
I IO(PIN)Output current sunk by any I/O and control pin25mA
I IO(PIN)Output current source by any I/O and control pin-25mA
I IO(PIN)Total output current sunk by sum of all I/Os and control pins (2)80mA
I IO(PIN)Total output current sourced by sum of all I/Os and control pins (2)-80mA
I IO(PIN)Total output current sourced by sum of all I/Os supplied by VDDIO2-40mA
I INJ(PIN) (3)Injected current on B, FT and FTf pins-5/+0 (4)mA
I INJ(PIN) (3)Injected current on TC and RST pin± 5mA
I INJ(PIN) (3)Injected current on TTa pins (5)± 5mA
I INJ(PIN)Total injected current (sum of all I/O and control pins) (6)± 25mA
  1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
  2. A positive injection is induced by V IN > V DDIOx while a negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
  3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  4. On these I/Os, a positive injection is induced by V IN > V DDA . Negative injection disturbs the analog performance of the device. See note (2) below Table 59: ADC accuracy .
  5. When several inputs are submitted to a current injection, the maximum I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 23. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

Table 23. Thermal characteristics

Thermal Information

The maximum chip junction temperature (T J max) must never exceed the values given in Table 24: General operating conditions .

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:T _ { J } max = T _ { A } max + ( P _ { D } max × Θ _ { J A } )

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.

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