STM32F072X8/XB

STM32F072x8 STM32F072xB

Overview

Part: STM32F072x8 STM32F072xB Type: ARM®-based 32-bit MCU

Key Specs:

Core frequency: up to 48 MHz
Flash memory: 64 to 128 Kbytes
SRAM: 16 Kbytes
Digital and I/O supply (VDD): 2.0 V to 3.6 V
Analog supply (VDDA): VDD to 3.6 V
Selected I/Os supply (VDDIO2): 1.65 V to 3.6 V
ADC: 12-bit, 1.0 μs (up to 16 channels)
DAC: 12-bit (with 2 channels)
SPI speed: 18 Mbit/s
I2C speed: 1 Mbit/s

Features:

Core: ARM® 32-bit Cortex®-M0 CPU
CRC calculation unit
Reset and power management: Power-on/Power down reset (POR/PDR), Programmable voltage detector (PVD), Low power modes (Sleep, Stop, Standby), VBAT supply for RTC and backup registers
Clock management: 4 to 32 MHz crystal oscillator, 32 kHz oscillator for RTC, Internal 8 MHz RC with x6 PLL option, Internal 40 kHz RC oscillator, Internal 48 MHz oscillator with automatic trimming
Up to 87 fast I/Os, up to 68 with 5V tolerant capability and 19 with independent supply VDDIO2
Seven-channel DMA controller
Two fast low-power analog comparators with programmable input and output
Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors
Calendar RTC with alarm and periodic wakeup from Stop/Standby
12 timers: One 16-bit advanced-control timer, One 32-bit and seven 16-bit timers, Independent and system watchdog timers, SysTick timer
Communication interfaces: Two I2C, Four USARTs, Two SPIs with I2S interface multiplexed, CAN interface, USB 2.0 full-speed interface (crystal-less, BCD and LPM support)
HDMI CEC wakeup on header reception
Serial wire debug (SWD)
96-bit unique ID
All packages ECOPACK®2

Applications:

null

Package:

UFBGA100
LQFP100
UFBGA64
LQFP64
WLCSP49
LQFP48
UFQFPN48

Features

Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz
Memories
- 64 to 128 Kbytes of Flash memory
- 16 Kbytes of SRAM with HW parity
CRC calculation unit
Reset and power management
- Digital and I/O supply: VDD = 2.0 V to 3.6 V
- Analog supply: VDDA = VDD to 3.6 V
- Selected I/Os: VDDIO2 = 1.65 V to 3.6 V
- Power-on/Power down reset (POR/PDR)
- Programmable voltage detector (PVD)
- Low power modes: Sleep, Stop, Standby
- VBAT supply for RTC and backup registers
Clock management
- 4 to 32 MHz crystal oscillator
- 32 kHz oscillator for RTC with calibration
- Internal 8 MHz RC with x6 PLL option
- Internal 40 kHz RC oscillator
- Internal 48 MHz oscillator with automatic trimming based on ext. synchronization
Up to 87 fast I/Os
- All mappable on external interrupt vectors
- Up to 68 I/Os with 5V tolerant capability and 19 with independent supply VDDIO2
Seven-channel DMA controller
One 12-bit, 1.0 μs ADC (up to 16 channels)
- Conversion range: 0 to 3.6 V
- Separate analog supply: 2.4 V to 3.6 V
One 12-bit D/A converter (with 2 channels)
Two fast low-power analog comparators with programmable input and output
Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors

Calendar RTC with alarm and periodic wakeup from Stop/Standby
12 timers
- One 16-bit advanced-control timer for six-channel PWM output
- One 32-bit and seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding or DAC control
- Independent and system watchdog timers
- SysTick timer
Communication interfaces
- Two I2C interfaces supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink; one supporting SMBus/PMBus and wakeup
- Four USARTs supporting master synchronous SPI and modem control; two with ISO7816 interface, LIN, IrDA, auto baud rate detection and wakeup feature
- Two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames, and with I2S interface multiplexed
- CAN interface
- USB 2.0 full-speed interface, able to run from internal 48 MHz oscillator and with BCD and LPM support
HDMI CEC wakeup on header reception
Serial wire debug (SWD)
96-bit unique ID
All packages ECOPACK®2

Table 1. Device summary

Reference	Part number
STM32F072xx	STM32F072C8, STM32F072R8, STM32F072V8, STM32F072CB, STM32F072RB, STM32F072VB

Pin Configuration

Figure 3. UFBGA100 package ballout (top view)

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Figure 4. LQFP100 100-pin package pinout (top view)

Figure 5. UFBGA64 package ball-out (top view)

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Figure 6. LQFP64 64-pin package pinout (top view)

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VDD VSS PB9 PB8 BOOT0 PB7 47 46 45 44 43 42 41 40 39 38 VDDIO2 VBAT 35C VSS PC13 PC14-OSC32_IN 13 34 PA13 33 PA12 PC15-OSC32_OUT C24 PF0-OSC_IN L35 32 PA11 31 PF1-OSC_OUT L⊇6 PA10 UFQFPN48 30 NRST L27 PA9 29 PA8 VSSA L⊃8 28C PB15 VDDA 27 C PA0 PB14 10 **‡⊃**11 26 🧲 PA1 PB13 PA2 12 PB12 PA3 PA4 PA5 PA6 PA7 PB0 ■ I/O pin supplied by VDDIO2 MS32166V1

Figure 8. UFQFPN48 48-pin package pinout (top view)

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Table 12. Legend/abbreviations used in the pinout table

	Name	Abbreviation	Definition
Pin name			Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
		S Supply pin
Pin type		I	Input only pin
		I/O	Input / output pin
		FT	5 V tolerant I/O
		FTf	5 V tolerant I/O, FM+ capable
		TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure		TC Standard 3.3 V I/O
		B	Dedicated BOOT0 pin
		RST	Bidirectional reset pin with embedded weak pull-up resistor
Notes		Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.
Pin	Alternate functions		Functions selected through GPIOx_AFR registers
functions	Additional functions	Functions directly selected/enabled through peripheral registers

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
B2	1	-	-	-	-	PE2	I/O	FT	-	TSC_G7_IO1, TIM3_ETR
A1	2	-	-	-	-	PE3	I/O	FT	-	TSC_G7_IO2, TIM3_CH1
B1	3	-	-	-	-	PE4	I/O	FT	-	TSC_G7_IO3, TIM3_CH2
C2	4	-	-	-	-	PE5	I/O	FT	-	TSC_G7_IO4, TIM3_CH3
D2	5	-	-	-	-	PE6	I/O	FT	-	TIM3_CH4
E2	6	B2	1	1	B7	VBAT	S	-	-	Backup power supply

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
C1	7	A2	2	2	D5	PC13	I/O	TC	(1) (2)	-
D1	8	A1	3	3	C7	PC14- OSC32_IN (PC14)	I/O	TC	(1) (2)	-
E1	9	B1	4	4	C6	PC15- OSC32_OUT (PC15)	I/O	TC	(1) (2)	-
F2	10	-	-	-	-	PF9	I/O	FT	-	TIM15_CH1
G2	11		-	-	-	PF10	I/O	FT	-	TIM15_CH2
F1	12	C1	5	5	D7	PF0-OSC_IN (PF0)	I/O	FT	-	CRS_ SYNC
G1	13	D1	6	6	D6	PF1-OSC_OUT (PF1)	I/O	FT	-	-
H2	14	E1	7	7	E7	NRST	I/O	RST	-	Device reset input / internal reset output (active low)
H1	15	E3	8	-	-	PC0	I/O	TTa	-	EVENTOUT
J2	16	E2	9	-	-	PC1	I/O	TTa	-	EVENTOUT
J3	17	F2	10	-	-	PC2	I/O	TTa	-	SPI2_MISO, I2S2_MCK, EVENTOUT
K2	18	G1	11	-	-	PC3	I/O	TTa	-	SPI2_MOSI, I2S2_SD, EVENTOUT
J1	19	-	-	-	-	PF2	I/O	FT	-	EVENTOUT
K1	20	F1	12	8	E6	VSSA	S	-	-	Analog ground
M1	21	H1	13	9	F7	VDDA	S	-	-	Analog power supply
L1	22	-	-	-	-	PF3	I/O	FT	-	EVENTOUT
L2	23	G2	14	10	F6	PA0	I/O	TTa	-	USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TX

Table 13. STM32F072x8/xB pin definitions (continued)

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
M2	24	H2	15	11	G7	PA1	I/O	TTa	-	USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT
K3	25	F3	16	12	E5	PA2	I/O	TTa	-	USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3
L3	26	G3	17	13	E4	PA3	I/O	TTa	-	USART2_RX,TIM2_CH4, TIM15_CH2, TSC_G1_IO4
D3	27	C2	18	-	-	VSS	S	-	-	Ground
H3	28	D2	19	-	-	VDD	S	-	-	Digital power supply
M3	29	H3	20	14	G6	PA4	I/O	TTa	-	SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK
K4	30	F4	21	15	F5	PA5	I/O	TTa	-	SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2
L4	31	G4	22	16	F4	PA6	I/O	TTa	-	SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS
M4	32	H4	23	17	F3	PA7	I/O	TTa	-	SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT

Table 13. STM32F072x8/xB pin definitions (continued)

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
K5	33	H5	24	-	-	PC4	I/O	TTa	-	EVENTOUT, USART3_TX
L5	34	H6	25	-	-	PC5	I/O	TTa	-	TSC_G3_IO1, USART3_RX
M5	35	F5	26	18	G5	PB0	I/O	TTa	-	TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK
M6	36	G5	27	19	G4	PB1	I/O	TTa	-	TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3
L6	37	G6	28	20	G3	PB2	I/O	FT	-	TSC_G3_IO4
M7	38	-	-	-	-	PE7	I/O	FT	-	TIM1_ETR
L7	39	-	-	-	-	PE8	I/O	FT	-	TIM1_CH1N
M8	40	-	-	-	-	PE9	I/O	FT	-	TIM1_CH1
L8	41	-	-	-	-	PE10	I/O	FT	-	TIM1_CH2N
M9	42	-	-	-	-	PE11	I/O	FT	-	TIM1_CH2
L9	43	-	-	-	-	PE12	I/O	FT	-	SPI1_NSS, I2S1_WS, TIM1_CH3N
M10	44	-	-	-	-	PE13	I/O	FT	-	SPI1_SCK, I2S1_CK, TIM1_CH3
M11	45	-	-	-	-	PE14	I/O	FT	-	SPI1_MISO, I2S1_MCK, TIM1_CH4
M12	46	-	-	-	-	PE15	I/O	FT	-	SPI1_MOSI, I2S1_SD, TIM1_BKIN
L10	47	G7	29	21	E3	PB10	I/O	FT	-	SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3
L11	48	H7	30	22	G2	PB11	I/O	FT	-	USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA
F12	49	D5	31	23	D3	VSS	S	-	-	Ground

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
G12	50	E5	32	24	F2	VDD	S	-	-	Digital power supply
L12	51	H8	33	25	E2	PB12	I/O	FT	-	TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT
K12	52	G8	34	26	G1	PB13	I/O	FTf	-	SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3
K11	53	F8	35	27	F1	PB14	I/O	FTf	-	SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4
K10	54	F7	36	28	E1	PB15	I/O	FT	-	SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2
K9	55	-	-	-	-	PD8	I/O	FT	-	USART3_TX
K8	56	-	-	-	-	PD9	I/O	FT	-	USART3_RX
J12	57	-	-	-	-	PD10	I/O	FT	-	USART3_CK
J11	58	-	-	-	-	PD11	I/O	FT	-	USART3_CTS
J10	59	-	-	-	-	PD12	I/O	FT	-	USART3_RTS, TSC_G8_IO1
H12	60	-	-	-	-	PD13	I/O	FT	-	TSC_G8_IO2
H11	61	-	-	-	-	PD14	I/O	FT	-	TSC_G8_IO3
H10	62	-	-	-	-	PD15	I/O	FT	-	TSC_G8_IO4, CRS_SYNC
E12	63	F6	37	-	-	PC6	I/O	FT	(3)	TIM3_CH1
E11	64	E7	38	-	-	PC7	I/O	FT	(3)	TIM3_CH2
E10	65	E8	39	-	-	PC8	I/O	FT	(3)	TIM3_CH3
D12	66	D8	40	-	-	PC9	I/O	FT	(3)	TIM3_CH4

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Table 13. STM32F072x8/xB pin definitions (continued)

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
D11	67	D7	41	29	D1	PA8	I/O	FT	(3)	USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC
D10	68	C7	42	30	D2	PA9	I/O	FT	(3)	USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1
C12	69	C6	43	31	C2	PA10	I/O	FT	(3)	USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2
B12	70	C8	44	32	C1	PA11	I/O	FT	(3)	CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT
A12	71	B8	45	33	C3	PA12	I/O	FT	(3)	CAN_TX, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT
A11	72	A8	46	34	B3	PA13	I/O	FT	(3) (4)	IR_OUT, SWDIO, USB_NOE
C11	73	-	-	-	-	PF6	I/O	FT	(3)	-
F11	74	D6	47	35	B1	VSS	S	-	-	Ground
G11	75	E6	48	36	B2	VDDIO2	S	-	-	Digital power supply
A10	76	A7	49	37	A1	PA14	I/O	FT	(3) (4)	USART2_TX, SWCLK
A9	77	A6	50	38	A2	PA15	I/O	FT	(3)	SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT
B11	78	B7	51	-	-	PC10	I/O	FT	(3)	USART3_TX, USART4_TX

Table 13. STM32F072x8/xB pin definitions (continued)

		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
C10	79	B6	52	-	-	PC11	I/O	FT	(3)	USART3_RX, USART4_RX
B10	80	C5	53	-	-	PC12	I/O	FT	(3)	USART3_CK, USART4_CK
C9	81	-	-	-	-	PD0	I/O	FT	(3)	SPI2_NSS, I2S2_WS, CAN_RX
B9	82	-	-	-	-	PD1	I/O	FT	(3)	SPI2_SCK, I2S2_CK, CAN_TX
C8	83	B5	54	-	-	PD2	I/O	FT	(3)	USART3_RTS, TIM3_ETR
B8	84	-	-	-	-	PD3	I/O	FT	-	SPI2_MISO, I2S2_MCK, USART2_CTS
B7	85	-	-	-	-	PD4	I/O	FT	-	SPI2_MOSI, I2S2_SD, USART2_RTS
A6	86	-	-	-	-	PD5	I/O	FT	-	USART2_TX
B6	87	-	-	-	-	PD6	I/O	FT	-	USART2_RX
A5	88	-	-	-	-	PD7	I/O	FT	-	USART2_CK
A8	89	A5	55	39	A3	PB3	I/O	FT	-	SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT
A7	90	A4	56	40	A4	PB4	I/O	FT	-	SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT
C5	91	C4	57	41	B4	PB5	I/O	FT	-	SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2
B5	92	D3	58	42	C4	PB6	I/O	FTf	-	I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_I03

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		Pin numbers								Pin functions
UFBGA100	LQFP100	UFBGA64	LQFP64	LQFP48/UFQFPN48	WLCSP49	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
B4	93	C3	59	43	D4	PB7	I/O	FTf	-	I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4
A4	94	B4	60	44	A5	BOOT0	I	B	-	Boot memory selection
A3	95	B3	61	45	B5	PB8	I/O	FTf	-	I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX
B3	96	A3	62	46	C5	PB9	I/O	FTf	-	SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX
C3	97	-	-	-	-	PE0	I/O	FT	-	EVENTOUT, TIM16_CH1
A2	98	-	-	-	-	PE1	I/O	FT	-	EVENTOUT, TIM17_CH1
D3	99	D4	63	47	A6	VSS	S	-	-	Ground
C4	100	E4	64	48	A7	VDD	S	-	-	Digital power supply

^1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

^- The speed should not exceed 2 MHz with a maximum load of 30 pF.

^- These GPIOs must not be used as current sources (e.g. to drive an LED).

^2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.

^3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os are supplied by VDDIO2.

^4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated.

Table 14. Alternate functions selected through GPIOA_AFR registers for port A

P in na me	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
P A 0	-	U S A R T 2_ C T S	T I M 2_ C H 1_ E T R	T S C_ G 1_ I O 1	U S A R T 4_ T X	-	-	C O M P 1_ O U T
P A 1	E V E N T O U T	U S A R T 2_ R T S	T I M 2_ C H 2	T S C_ G 1_ I O 2	U S A R T 4_ R X	T I M 1 5_ C H 1 N	-	-
P A 2	C T I M 1 5_ H 1	S U A R T 2_ T X	C T I M 2_ H 3	S C_ G O T 1_ I 3	-	-	-	C O O M P 2_ U T
P A 3	T I M 1 5_ C H 2	U S A R T 2_ R X	T I M 2_ C H 4	T S C_ G 1_ I O 4	-	-	-	-
P A 4	S P I 1_ N S S, I 2 S 1_ W S	U S A R T 2_ C K	-	T S C_ G 2_ I O 1	T I M 1 4_ C H 1	-	-	-
P A 5	S P I 1_ S C K, I 2 S 1_ C K	C E C	T I M 2_ C H 1_ E T R	T S C_ G 2_ I O 2	-	-	-	-
P A 6	S S O, S C P I 1_ M I I 2 1_ M K	C T I M 3_ H 1	T I M 1_ B K I N	S C_ G O T 2_ I 3	S C S U A R T 3_ T	C T I M 1 6_ H 1	O E V E N T U T	C O O M P 1_ U T
P A 7	S P I 1_ M O S I, I 2 S 1_ S D	T I M 3_ C H 2	T I M 1_ C H 1 N	T S C_ G 2_ I O 4	T I M 1 4_ C H 1	T I M 1 7_ C H 1	E V E N T O U T	C O M P 2_ O U T
P A 8	M C O	U S A R T 1_ C K	T I M 1_ C H 1	E V E N T O U T	C R S_ S Y N C	-	-	-
P A 9	T I M 1 B K I N 5_	U S A R T 1_ T X	T I M 1_ C H 2	T S C_ G 4_ I O 1	-	-	-	-
P A 1 0	T I M 1 7_ B K I N	S U A R T 1_ R X	C T I M 1_ H 3	S C_ G O T 4_ I 2	-	-	-	-
P A 1 1	E V E N T O U T	U S A R T 1_ C T S	T I M 1_ C H 4	T S C_ G 4_ I O 3	C A N_ R X	-	-	C O M P 1_ O U T
P A 1 2	E V E N T O U T	U S A R T 1_ R T S	T I M 1_ E T R	T S C_ G 4_ I O 4	C A N_ T X	-	-	C O M P 2_ O U T
1 3 P A	S O W D I	O I R_ U T	S O U B_ N E	-	-	-	-	-
P A 1 4	S W C L K	U S A R T 2_ T X	-	-	-	-	-	-
P A 1 5	S P I 1_ N S S, I 2 S 1_ W S	U S A R T 2_ R X	T I M 2_ C H 1_ E T R	E V E N T O U T	U S A R T 4_ R T S	-	-	-

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Table 16. Alternate functions selected through GPIOC_AFR registers for port C

Pin name	AF0	AF1
PC0	EVENTOUT	-
PC1	EVENTOUT	-
PC2	EVENTOUT	SPI2_MISO, I2S2_MCK
PC3	EVENTOUT	SPI2_MOSI, I2S2_SD
PC4	EVENTOUT	USART3_TX
PC5	TSC_G3_IO1	USART3_RX
PC6	TIM3_CH1	-
PC7	TIM3_CH2	-
PC8	TIM3_CH3	-
PC9	TIM3_CH4	-
PC10	USART4_TX	USART3_TX
PC11	USART4_RX	USART3_RX
PC12	USART4_CK	USART3_CK
PC13	-	-
PC14	-	-
PC15	-	-

Table 17. Alternate functions selected through GPIOD_AFR registers for port D

Pin name	AF0	AF1
PD0	CAN_RX	SPI2_NSS, I2S2_WS
PD1	CAN_TX	SPI2_SCK, I2S2_CK
PD2	TIM3_ETR	USART3_RTS
PD3	USART2_CTS	SPI2_MISO, I2S2_MCK
PD4	USART2_RTS	SPI2_MOSI, I2S2_SD
PD5	USART2_TX	-
PD6	USART2_RX	-
PD7	USART2_CK	-
PD8	USART3_TX	-
PD9	USART3_RX	-
PD10	USART3_CK	-
PD11	USART3_CTS	-
PD12	USART3_RTS	TSC_G8_IO1
PD13	-	TSC_G8_IO2
PD14	-	TSC_G8_IO3
PD15	CRS_SYNC	TSC_G8_IO4

Table 18. Alternate functions selected through GPIOE_AFR registers for port E

Pin name	AF0	AF1
PE0	TIM16_CH1	EVENTOUT
PE1	TIM17_CH1	EVENTOUT
PE2	TIM3_ETR	TSC_G7_IO1
PE3	TIM3_CH1	TSC_G7_IO2
PE4	TIM3_CH2	TSC_G7_IO3
PE5	TIM3_CH3	TSC_G7_IO4
PE6	TIM3_CH4	-
PE7	TIM1_ETR	-
PE8	TIM1_CH1N	-
PE9	TIM1_CH1	-
PE10	TIM1_CH2N	-
PE11	TIM1_CH2	-
PE12	TIM1_CH3N	SPI1_NSS, I2S1_WS
PE13	TIM1_CH3	SPI1_SCK, I2S1_CK
PE14	TIM1_CH4	SPI1_MISO, I2S1_MCK
PE15	TIM1_BKIN	SPI1_MOSI, I2S1_SD

Table 19. Alternate functions available on port F

Pin name	AF
PF0	CRS_SYNC
PF1	-
PF2	EVENTOUT
PF3	EVENTOUT
PF6	-
PF9	TIM15_CH1
PF10	TIM15_CH2

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 24 and Table 55, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions.

Table 55. I/O AC characteristics(1)(2)

OSPEEDRy [1:0] value(1)	Symbol	Parameter	Conditions	Min	Max	Unit
	fmax(IO)out	Maximum frequency(3)		-	2	MHz
	tf(IO)out	Output fall time	CL = 50 pF, VDDIOx  2 V	-	125
	tr(IO)out	Output rise time		-	125	ns
x0	fmax(IO)out	Maximum frequency(3)		-	1	MHz
	tf(IO)out	Output fall time	CL = 50 pF, VDDIOx  2 V	-	125	ns
	tr(IO)out	Output rise time		-	125
	fmax(IO)out	Maximum frequency(3)		-	10	MHz
01	tf(IO)out	Output fall time	CL = 50 pF, VDDIOx  2 V		25
	tr(IO)out	Output rise time			25	ns
	fmax(IO)out	Maximum frequency(3)		-	4	MHz
	tf(IO)out	Output fall time	CL = 50 pF, VDDIOx  2 V	-	62.5	ns
	tr(IO)out	Output rise time		-	62.5
			CL = 30 pF, VDDIOx  2.7 V	-	50
		Maximum frequency(3)	 CL = 50 pF, VDDIOx 2.7 V	-	30	MHz
	fmax(IO)out		CL = 50 pF, 2 V VDDIOx  2.7 V	-	20
			CL = 50 pF, VDDIOx  2 V	-	10
			CL = 30 pF, VDDIOx  2.7 V	-	5
11		Output fall time	CL = 50 pF, VDDIOx  2.7 V	-	8
	tf(IO)out		CL = 50 pF, 2 V VDDIOx  2.7 V	-	12
			CL = 50 pF, VDDIOx  2 V	-	25
			CL = 30 pF, VDDIOx  2.7 V	-	5	ns
		Output rise time	CL = 50 pF, VDDIOx  2.7 V	-	8
	tr(IO)out		CL = 50 pF, 2 V VDDIOx  2.7 V	-	12
			CL = 50 pF, VDDIOx  2 V	-	25

OSPEEDRy [1:0] value ⁽¹⁾	Symbol	Parameter	Conditions	Min	Max	Unit
	f _max(IO)out	Maximum frequency ⁽³⁾			2	MHz
Fm+ configuration	t _f(IO)out	Output fall time	C_L = 50 \text{ pF}, V_{DDIOx} \ge 2 \text{ V}$	-	12	ns
	t _r(IO)out	Output rise time			34	115
(4)	f _max(IO)out	Maximum frequency ⁽³⁾		-	0.5	MHz
	t _f(IO)out	Output fall time	$C_L = 50 pF, V_{DDIOx} < 2 V	-	16	ne
	t _r(IO)out	Output rise time		-	44	ns
-	t _EXTIpw	Pulse width of external signals detected by the EXTI controller	-	10	-	ns

Table 55. I/O AC characteristics⁽¹⁾⁽²⁾ (continued)

The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register.
1. Guaranteed by design, not tested in production.
1. The maximum frequency is defined in Figure 24.
When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.

![](_page₈7_Figure₈.jpeg)

Figure 24. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics, Table 22: Current characteristics and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 21. Voltage characteristics(1)

Symbol	Ratings	Min	Max	Unit
VDD–VSS	External main supply voltage	-0.3	4.0	V
VDDIO2–VSS	External I/O supply voltage	-0.3	4.0	V
VDDA–VSS	External analog supply voltage	-0.3	4.0	V
VDD–VDDA	Allowed voltage difference for VDD > VDDA	-	0.4	V
VBAT–VSS	External backup supply voltage	-0.3	4.0	V
	Input voltage on FT and FTf pins	VSS  0.3	VDDIOx + 4.0(3)	V
VIN(2)	Input voltage on TTa pins	VSS  0.3	4.0	V
	BOOT0	0	9.0	V
	Input voltage on any other pin	VSS 0.3	4.0	V
VDDx	Variations between different VDD power pins	-	50	mV
VSSx VSS	Variations between all the different ground pins	-	50	mV
VESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.12: Electrical sensitivity characteristics

^2. VIN maximum must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected current values.

^3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V.

Table 22. Current characteristics

Symbol	Ratings		Unit
IVDD	Total current into sum of all VDD power lines (source)(1)	120
IVSS	Total current out of sum of all VSS ground lines (sink)(1)	-120
IVDD(PIN)	Maximum current into each VDD power pin (source)(1)	100
IVSS(PIN)	Maximum current out of each VSS ground pin (sink)(1)	-100
	Output current sunk by any I/O and control pin	25
IIO(PIN)	Output current source by any I/O and control pin
	Total output current sunk by sum of all I/Os and control pins(2)	80
IIO(PIN)	Total output current sourced by sum of all I/Os and control pins(2)	-80	mA
	Total output current sourced by sum of all I/Os supplied by VDDIO2	-40
	Injected current on B, FT and FTf pins	-5/+0(4)
IINJ(PIN)(3)	Injected current on TC and RST pin	± 5
	Injected current on TTa pins(5)	± 5
IINJ(PIN)	Total injected current (sum of all I/O and control pins)(6)	± 25

Table 23. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature		°C

![](_page₅3_Picture₁2.jpeg)

Thermal Information

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 24: General operating conditions.

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:T_J max = T_A max + (P_D max x Θ_JA)$

Where:

TA max is the maximum ambient temperature in °C,
JA is the package junction-to-ambient thermal resistance, in C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$P_I/O$ max = $\Sigma (V_{OL} \times I_{OL}) + \Sigma ((V_{DDIOx} - V_{OH}) \times I_{OH}),

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol	Parameter	Value	Unit
	Thermal resistance junction-ambient UFBGA100 - 7 × 7 mm	55
	Thermal resistance junction-ambient LQFP100 - 14 × 14 mm	42
	Thermal resistance junction-ambient UFBGA64 - 5 × 5 mm / 0.5 mm pitch	65
JA	Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch	44	°C/W
	Thermal resistance junction-ambient LQFP48 - 7 × 7 mm	54
	Thermal resistance junction-ambient UFQFPN48 - 7 × 7 mm	32
	Thermal resistance junction-ambient WLCSP49 - 0.4 mm pitch	49

7.8.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org

7.8.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering.

![](_page₁27_Picture₂1.jpeg)

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F072x8/xB at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum temperatureT_{Amax}$ = 82 °C (measured according to JESD51-2), $I_{DDmax}$ = 50 mA, $V_{DD}$ = 3.5 V, maximum 20 I/Os used at the same time in output at low level with $I_{OL}$ = 8 mA, $V_{OL}$ = 0.4 V and maximum 8 I/Os used at the same time in output at low level with $I_{OL}$ = 20 mA, $V_{OL}$ = 1.3 V

$P_{INTmax} = 50 \text{ mA} \times 3.5 \text{ V} = 175 \text{ mW}$

$P_{IOmax} = 20 \times 8 \text{ mA} \times 0.4 \text{ V} + 8 \times 20 \text{ mA} \times 1.3 \text{ V} = 272 \text{ mW}$

This gives: P_INTmax = 175 mW and P_IOmax = 272 mW:

$P_{Dmax} = 175 + 272 = 447 \text{ mW}$

Using the values obtained in Table 80 T_Jmax is calculated as follows:

For LQFP64, 45 °C/W

$T_lmax$ = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C

This is within the range of the suffix 6 version parts ( $-40 < T_J < 105$ °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Part numbering).

Note:

With this given $P_{Dmax}$ we can find the $T_{Amax}$ allowed for a given device temperature range (order code suffix 6 or 7).

Suffix 6: $T_Amax = T_Jmax$

$(45^{\circ}\text{C/W} \times 447 \text{ mW}) = 105\text{-}20.115 = 84.885 ^{\circ}\text{C}$
Suffix 7: $T_{Amax} = T_{Jmax}$ - $(45^{\circ}\text{C/W} \times 447 \text{ mW}) = 125\text{-}20.115 = 104.885 ^{\circ}\text{C}$

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high temperatures with a low dissipation, as long as junction temperature $T_J$ remains within the specified range.

Assuming the following application conditions:

Maximum temperature $T_{Amax}$ = 100 °C (measured according to JESD51-2), $I_{DDmax}$ = 20 mA, $V_{DD}$ = 3.5 V, maximum 20 I/Os used at the same time in output at low level with $I_{OL}$ = 8 mA, $V_{OL}$ = 0.4 V

$P_{INTmax} = 20 \text{ mA} \times 3.5 \text{ V} = 70 \text{ mW}$

$P_{IOmax} = 20 \times 8 \text{ mA} \times 0.4 \text{ V} = 64 \text{ mW}$

This gives: $P_{INTmax} = 70 \text{ mW}$ and $P_{IOmax} = 64 \text{ mW}$ :

$P_{Dmax} = 70 + 64 = 134 \text{ mW}Thus: P_Dmax = 134 mW

![](_page₁28_Picture₂9.jpeg)

Using the values obtained inTable 80 T_{Jmax}$ is calculated as follows:

For LQFP64, 45 °C/W

$T_Jmax$ = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C

This is above the range of the suffix 6 version parts ( $-40 < T_J < 105$ °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Part numbering) unless we reduce the power dissipation in order to be able to use suffix 6 parts.

Refer to Figure 55 to select the required temperature range (suffix 6 or 7) according to your temperature or power requirements.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
STM32F072C8	—	—
STM32F072CB	—	—
STM32F072CX	—	—
STM32F072R8	—	—
STM32F072RB	—	—
STM32F072RBT6		LQFP-64(10x10)
STM32F072RX	—	—
STM32F072V8	—	—
STM32F072VB	—	—
STM32F072VX	—	—
STM32F072X8	—	—
STM32F072XB	—	—
STM32F072XX	—	—

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