STM32F030F4P6

Part: STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC

Type: Value-line ARM®-based 32-bit MCU

Key Specs:

• Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz
• Flash memory: 16 to 256 Kbytes
• SRAM: 4 to 32 Kbytes
• Digital & I/Os supply (VDD): 2.4 V to 3.6 V
• ADC: 12-bit, 1.0 μs (up to 16 channels)
• SPI speed: 18 Mbit/s

Features:

• CRC calculation unit
• Power-on/Power down reset (POR/PDR)
• Low power modes: Sleep, Stop, Standby
• Clock management: 4 to 32 MHz crystal oscillator, 32 kHz oscillator, internal 8 MHz RC with x6 PLL option, internal 40 kHz RC oscillator
• Up to 55 fast I/Os, up to 55 I/Os with 5V tolerant capability
• 5-channel DMA controller
• Calendar RTC with alarm and periodic wakeup from Stop/Standby
• 11 timers: one 16-bit advanced-control timer, up to seven 16-bit timers, independent and system watchdog timers, SysTick timer
• Up to two I2C interfaces (Fast Mode Plus, SMBus/PMBus support)
• Up to six USARTs (master synchronous SPI, modem control, auto baud rate detection)
• Up to two SPIs with 4 to 16 programmable bit frames
• Serial wire debug (SWD)
• All packages ECOPACK®2

Applications:

• null

Package:

• LQFP64: null
• LQFP48: null
• LQFP32: null
• TSSOP20: null

• Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz
• Memories
  • 16 to 256 Kbytes of Flash memory
  • 4 to 32 Kbytes of SRAM with HW parity
• CRC calculation unit
• Reset and power management
  • Digital & I/Os supply: VDD = 2.4 V to 3.6 V
  • Analog supply: VDDA = VDD to 3.6 V
  • Power-on/Power down reset (POR/PDR)
  • Low power modes: Sleep, Stop, Standby
• Clock management
  • 4 to 32 MHz crystal oscillator
  • 32 kHz oscillator for RTC with calibration
  • Internal 8 MHz RC with x6 PLL option
  • Internal 40 kHz RC oscillator
• Up to 55 fast I/Os
  • All mappable on external interrupt vectors
  • Up to 55 I/Os with 5V tolerant capability
• 5-channel DMA controller
• One 12-bit, 1.0 μs ADC (up to 16 channels)
  • Conversion range: 0 to 3.6 V
  • Separate analog supply: 2.4 V to 3.6 V
• Calendar RTC with alarm and periodic wakeup from Stop/Standby
• 11 timers
  • One 16-bit advanced-control timer for six-channel PWM output
  • Up to seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding
  • Independent and system watchdog timers
  • SysTick timer

Datasheet - production data

• Communication interfaces
  • Up to two I2C interfaces
    • Fast Mode Plus (1 Mbit/s) support on one or two I/Fs, with 20 mA current sink
    • SMBus/PMBus support (on single I/F)
  • Up to six USARTs supporting master synchronous SPI and modem control; one with auto baud rate detection
  • Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames
• Serial wire debug (SWD)

• All packages ECOPACK®2

Table 1. Device summary

Reference	Part number
STM32F030x4	STM32F030F4
STM32F030x6	STM32F030C6, STM32F030K6
STM32F030x8	STM32F030C8, STM32F030R8
STM32F030xC	STM32F030CC, STM32F030RC

This is information on a product in full production.

Figure 3. LQFP64 64-pin package pinout (top view), for STM32F030x4/6/8 devices

24/91 DocID024849 Rev 3

Figure 5. LQFP48 48-pin package pinout (top view), for STM32F030x4/6/8 devices

Figure 7. LQFP32 32-pin package pinout (top view)

Name		Abbreviation Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
		S
Pin type		I
		I/O
		FT FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure		TC Standard 3.3 V I/O B Dedicated BOOT0 pin
		RST
Notes		Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.
Pin functions	Alternate functions	Functions selected through GPIOx_AFR registers
	Additional functions
Table 10. Legend/abbreviations used in the pinout table
---------------------------------------------------------	--	--
---------------------------------------------------------	--	--

Table 11. STM32F030x4/6/8/C pin definitions

LQFP64	LQFP48	LQFP32	TSSOP20	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
1	1	-	-	VDD	S	-	-	Complementary power supply	-
2	2	-	-	PC13	I/O	TC	(1)	-	RTC_TAMP1, RTC_TS, RTC_

Pin number								Pin functions
LQFP64	LQFP48	LQFP32	TSSOP20	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
8	-	-	-	PC0	I/O	TTa	-	EVENTOUT, USART6_TX(5)
9	-	-	-	PC1	I/O	TTa	-	EVENTOUT, USART6_RX(5)
10	-	-	-	PC2	I/O	TTa	-	SPI2_MISO(5), EVENTOUT
11	-	-	-	PC3	I/O	TTa	-	SPI2_MOSI(5), EVENTOUT
12	8	-	-	VSSA	S	-	-	Analog ground
13	9	5	5	VDDA	S	-	-	Analog power supply
14	10	6	6	PA0	I/O	TTa	-	USART1_CTS(2), USART2_CTS(3)(5), USART4_TX(5)
15	11	7	7	PA1	I/O	TTa	-	USART1_RTS(2), USART2_RTS(3)(5), EVENTOUT, USART4_RX(5)
16	12	8	8	PA2	I/O	TTa	-	USART1_TX(2), USART2_TX(3)(5), TIM15_CH1(3)(5)
17	13	9	9	PA3	I/O	TTa	-	USART1_RX(2), USART2_RX(3)(5), TIM15_CH2(3)(5)
18(4)	-	-	-	PF4	I/O	FT	(4)	EVENTOUT
18(5)	-	-	-	VSS	S	-	(5)	Ground
19(4)	-	-	-	PF5	I/O	FT	(4)	EVENTOUT
19(5)	-	-	-	VDD	-	-	(5)	Complementary power supply
20	14	10	10	PA4	I/O	TTa	-	SPI1_NSS, USART1_CK(2) USART2_CK(3)(5), TIM14_CH1, USART6_TX(5)
21	15	11	11	PA5	I/O	TTa	-	SPI1_SCK, USART6_RX(5)

Pin number								Pin functions
LQFP64	LQFP48	LQFP32	TSSOP20	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
22	16	12	12	PA6	I/O	TTa	-	SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT USART3_CTS(5)
23	17	13	13	PA7	I/O	TTa	-	SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT
24	-	-	-	PC4	I/O	TTa	-	EVENTOUT, USART3_TX(5)
25	-	-	-	PC5	I/O	TTa	-	USART3_RX(5)
26	18	14	-	PB0	I/O	TTa	-	TIM3_CH3, TIM1_CH2N, EVENTOUT, USART3_CK(5)
27	19	15	14	PB1	I/O	TTa	-	TIM3_CH4, TIM14_CH1, TIM1_CH3N, USART3_RTS(5)
28	20	-	-	PB2	I/O	FT	(6)	-
29	21	-	-	PB10	I/O	FT	-	SPI2_SCK(5), I2C1_SCL(2), I2C2_SCL(3)(5), USART3_TX(5)
30	22	-	-	PB11	I/O	FT	-	I2C1_SDA(2), I2C2_SDA(3)(5), EVENTOUT, USART3_RX(5)
31	23	16	-	VSS	S	-	-	Ground
32	24	17	16	VDD	S	-	-	Digital power supply
33	25	-	-	PB12	I/O	FT	-	SPI1_NSS(2), SPI2_NSS(3)(5), TIM1_BKIN, EVENTOUT, USART3_CK(5)

Pin number								Pin functions
LQFP64	LQFP48	LQFP32	TSSOP20	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
34	26	-	-	PB13	I/O	FT	-	SPI1_SCK(2), SPI2_SCK(3)(5), I2C2_SCL(5), TIM1_CH1N, USART3_CTS(5)
35	27	-	-	PB14	I/O	FT	-	SPI1_MISO(2), SPI2_MISO(3)(5), I2C2_SDA(5), TIM1_CH2N, TIM15_CH1(3)(5), USART3_RTS(5)
36	28	-	-	PB15	I/O	FT	-	SPI1_MOSI(2), SPI2_MOSI(3)(5), TIM1_CH3N, TIM15_CH1N(3)(5), TIM15_CH2(3)(5)
37	-	-	-	PC6	I/O	FT	-	TIM3_CH1
38	-	-	-	PC7	I/O	FT	-	TIM3_CH2
39	-	-	-	PC8	I/O	FT	-	TIM3_CH3
40	-	-	-	PC9	I/O	FT	-	TIM3_CH4
41	29	18	-	PA8	I/O	FT	-	USART1_CK, TIM1_CH1, EVENTOUT, MCO
42	30	19	17	PA9	I/O	FT	-	USART1_TX, TIM1_CH2, TIM15_BKIN(3)(5) I2C1_SCL(2)(5)
43	31	20	18	PA10	I/O	FT	-	USART1_RX, TIM1_CH3, TIM17_BKIN I2C1_SDA(2)(5)
44	32	21	-	PA11	I/O	FT	-	USART1_CTS, TIM1_CH4, EVENTOUT, I2C2_SCL(5)
45	33	22	-	PA12	I/O	FT	-	USART1_RTS, TIM1_ETR, EVENTOUT, I2C2_SDA(5)

Pin number								Pin functions
LQFP64	LQFP48	LQFP32	TSSOP20	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
46	34	23	19	PA13 (SWDIO)	I/O	FT	(7)	IR_OUT, SWDIO
47(4)	35(4)	-	-	PF6	I/O	FT	(4)	I2C1_SCL(2), I2C2_SCL(3)
47(5)	35(5)	-	-	VSS	S	-	(5)	Ground
48(4)	36(4)	-	-	PF7	I/O	FT	(4)	I2C1_SDA(2), I2C2_SDA(3)
48(5)	36(5)	-	-	VDD	S	-	(5)	Complementary power supply
49	37	24	20	PA14 (SWCLK)	I/O	FT	(7)	USART1_TX(2), USART2_TX(3)(5), SWCLK
50	38	25	-	PA15	I/O	FT	-	SPI1_NSS, USART1_RX(2), USART2_RX(3)(5), USART4_RTS(5), EVENTOUT
51	-	-	-	PC10	I/O	FT	-	USART3_TX(5), USART4_TX(5)
52	-	-	-	PC11	I/O	FT	-	USART3_RX(5), USART4_RX(5)
53	-	-	-	PC12	I/O	FT	-	USART3_CK(5), USART4_CK(5), USART5_TX(5)
54	-	-	-	PD2	I/O	FT	-	TIM3_ETR, USART3_RTS(5), USART5_RX(5)
55	39	26	-	PB3	I/O	FT	-	SPI1_SCK, EVENTOUT, USART5_TX(5)
56	40	27	-	PB4	I/O	FT	-	SPI1_MISO, TIM3_CH1, EVENTOUT, TIM17_BKIN(5), USART5_RX(5)
57	41	28	-	PB5	I/O	FT	-	SPI1_MOSI, I2C1_SMBA, TIM16_BKIN, TIM3_CH2, USART5_CK_RTS(5)

Pin number								Pin functions
LQFP64	LQFP48	LQFP32	TSSOP20	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
58	42	29	-	PB6	I/O	FTf	-	I2C1_SCL, USART1_TX, TIM16_CH1N
59	43	30	-	PB7	I/O	FTf	-	I2C1_SDA, USART1_RX, TIM17_CH1N, USART4_CTS(5)
60	44	31	1	BOOT0	I	B	-	Boot memory selection
61	45	-	-	PB8	I/O	FTf	(6)	I2C1_SCL, TIM16_CH1
62	46	-	-	PB9	I/O	FTf	-	I2C1_SDA, IR_OUT, SPI2_NSS(5), TIM17_CH1, EVENTOUT
63	47	32	15	VSS	S	-	-	Ground
64	48	1	16	VDD	S	-	-	Digital power supply

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF.

• These GPIOs must not be used as current sources (e.g. to drive an LED).

1. This feature is available on STM32F030x6 and STM32F030x4 devices only.

2. This feature is available on STM32F030x8 devices only.

3. For STM32F030x4/6/8 devices only.

4. For STM32F030xC devices only.

5. On LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the package, they are not forced to a defined level by hardware).

6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on SWDIO pin and internal pull-down on SWCLK pin are activated.

P in na me	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6
P A 0		( 2) U S A R T 1_ C T S			( 1) S A R T T X
	-	( 1) ( 3) U S A R T C T S 2_	-	-	U 4_	-	-
		( 2) S S U A R T 1_ R T		-	( 1) U S A R T 4_ R X	( 1) T I M 1 C H 1 N 5_
P A 1	E V E N T O U T	( 1) ( 3) U S A R T 2_ R T S	-				-
	( 1) ( 3)	( 2) S U A R T 1_ T X		-	-	-	-
P A 2	C T I M 1 5_ H 1 ( 1) ( 3)	( 1) ( 3) U S A R T 2_ T X ( 2) U S A R T R X 1_	-
P A 3	C T I M 1 5_ H 2	( 1) ( 3) S U A R T 2_ R X	-	-	-	-	-
		( 2) U S A R T 1_ C K		-	T I M C H 1 4_ 1	( 1) U S A R T T X 6_	-
P A 4	S P I N S S 1_	( 1) ( 3) S C U A R T 2_ K	-
P A 5	S P I 1_ S C K	-	-	-	-	( 1) U S A R T 6_ R X	-
P A 6	S P I M I S O 1_	T I M C H 3_ 1	T I M B K I N 1_	-	( 1) U S A R T C T S 3_	T I M C H 1 6_ 1	E V E N T O U T
P A 7	S O S P I 1_ M I	C T I M 3_ H 2	C T I M 1_ H 1 N	-	C T I M 1 4_ H 1	C T I M 1 7_ H 1	O E V E N T U T
P A 8	M C O	U S A R T 1_ C K	T I M 1_ C H 1	E V E N T O U T	-	-	-
P A 9	( 1) ( 3) T I M 1 5_ B K I N	S U A R T 1_ T X	C T I M 1_ H 2	-	( 1) ( 2) C S C I 2 1_ L	( 1) C O M	-
P A 1 0	T I M 1 7_ B K I N	U S A R T 1_ R X	T I M 1_ C H 3	-	( 1) ( 2) I 2 C 1_ S D A	-	-
P A 1 1	E V E N T O U T	U S A R T C T S 1_	T I M C H 1_ 4	-	-	S C L	-

Table 12. Alternate functions selected through GPIOA_AFR registers for port A

Table 12. Alternate functions selected through GPIOA_AFR registers for port A (continued)

	Ta b le 1 2. A l fu io lec d hr h G P I O A_ A F R is fo A ( in d ) te te t te t te t t rn a nc ns s e ou g re g rs r p or co n ue
P in na me	A F 0
P A 1 2	E V E N T O U T
P A 1 3	S W D I O
P A 1 4
	S W C L K
P A 1 5	S S S P I 1_ N
1. Th is f tur ea	e is aila ble ST M3 av on
2. Th is f tur ea	e is aila ble ST M3 av on
3. Th is f e is aila ble ST M3 2F 03 0x 8 d ice tur ea av on ev s.
	Ta b le 1
in P na me	A F 0
P B 0	E V E N T O U T

• P
  B
  1

---

• P
  B
  2

• P
  B
  3

• P
  B
  4

• P
  B
  5

• P
  B
  6

• P
  B
  7

• P
  in
  na
  me

• P
  B
  8

• P
  B
  9

• P
  B
  1
  0

• P
  B
  1
  1

• P
  B
  1
  2

• P
  B
  1
  3

• P
  B
  1
  4

• P
  B
  1
  5

1. This feature is available on STM32F030xC devices.

2. This feature is available on STM32F030x4 and STM32F030x6 devices.

3. This feature is available on STM32F030x8 devices.

Pin name	AF0	AF1(1)	AF2(1)
PC0	EVENTOUT	-	USART6_TX
PC1	EVENTOUT	-	USART6_RX
PC2	EVENTOUT	SPI2_MISO	-
PC3	EVENTOUT	SPI2_MOSI	-
PC4	EVENTOUT	USART3_TX	-
PC5	-	USART3_RX	-
PC6	TIM3_CH1	-	-
PC7	TIM3_CH2	-	-
PC8	TIM3_CH3	-	-
PC9	TIM3_CH4	-	-
PC10	USART4_TX(1)	USART3_TX	-
PC11	USART4_RX(1)	USART3_RX	-
PC12	USART4_CK(1)	USART3_CK	USART5_TX
PC13	-	-	-
PC14	-	-	-
PC15	-	-	-

Table 14. Alternate functions selected through GPIOC_AFR registers for port C

1. Available on STM32F030xC devices only.

Table 15. Alternate functions selected through GPIOD_AFR registers for port D
-------------------------------------------------------------------------------

Pin name	AF0	AF1(1)	AF2(1)
PD2	TIM3_ETR	USART3_RTS	USART5_RX

1. Available on STM32F030xC devices only.

Table 16. Alternate functions selected through GPIOF_AFR registers for port F

Pin name	AF0	AF1(1)
PF0	-	I2C1_SDA
PF1	-	I2C1_SCL

1. Available on STM32F030xC devices only.

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

6.1.6 Power supply scheme

Figure 12. Power supply scheme

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

6.1.7 Current consumption measurement

Figure 13. Current consumption measurement scheme

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD–VSS	External main supply voltage	-0.3	4.0	V
VDDA–VSS	External analog supply voltage	-0.3	4.0	V
VDD–VDDA	Allowed voltage difference for VDD > VDDA	-	0.4	V
VIN(2)	Input voltage on FT and FTf pins	VSS - 0.3	VDDIOx + 4.0 (3)	V
	Input voltage on TTa pins	VSS - 0.3	4.0	V
	BOOT0	0	VDDIOx + 4.0 (3)	V
	Input voltage on any other pin	VSS -0.3	4.0	V
ΔVDDx	Variations between different VDD power pins	-	50	mV
VSSx -VSS	Variations between all the different ground pins	-	50	mV
VESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.12: Electrical sensitivity characteristics		-

Table 18. Voltage characteristics(1)
--------------------------------------

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values.

3. VDDIOx is internally connected with VDD pin.

Symbol	Ratings	Max.	Unit
ΣIVDD	Total current into sum of all VDD power lines (source)(1)	120
ΣIVSS	Total current out of sum of all VSS ground lines (sink)(1)	-120
IVDD(PIN)	Maximum current into each VDD power pin (source)(1)	100
IVSS(PIN)	Maximum current out of each VSS ground pin (sink)(1)	-100
IIO(PIN)	Output current sunk by any I/O and control pin	25
	Output current source by any I/O and control pin	-25	mA
ΣIIO(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	80
	Total output current sourced by sum of all I/Os and control pins(2)	-80
IINJ(PIN)(3)	Injected current on FT and FTf pins	-5/+0(4)
	Injected current on TC and RST pin	± 5
	Injected current on TTa pins(5)	± 5
ΣIINJ(PIN)	Total injected current (sum of all I/O and control pins)(6)	± 25

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the device. See note (2) below Table 52: ADC accuracy.

6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	150	°C

6.3 Operating conditions

6.3.1 General operating conditions

Symbol	Parameter	Conditions	Min	Max	Unit
f_HCLK	Internal AHB clock frequency	-	0	48	MHz
f_PCLK	Internal APB clock frequency	-	0	48	MHz
V_DD	Standard operating voltage	-	2.4	3.6	V

Symbol	Parameter	Conditions	Min	Max	Unit
fHCLK	Internal AHB clock frequency	-	0	48	MHz
fPCLK	Internal APB clock frequency	-	0	48	MHz
VDD	Standard operating voltage	-	2.4	3.6	V

Symbol	Parameter	Conditions	Min	Max	Unit
VDDA	Analog operating voltage	Must have a potential equal to or higher than VDD	2.4	3.6	V
VIN	I/O input voltage	TC and RST I/O	-0.3	VDDIOx+0.3	V
		TTa I/O	-0.3	VDDA+0.3(2)
		FT and FTf I/O	-0.3	5.5(2)
		BOOT0	0	5.5
PD	Power dissipation at TA = 85 °C for suffix 6 (1)	LQFP64	-	455
		LQFP48	-	364	mW
		LQFP32	-	357
		TSSOP20	-	263
TA	Ambient temperature for the suffix 6 version	Maximum power dissipation	-40	85
		Low power dissipation(2)	-40	105	°C
TJ	Junction temperature range	Suffix 6 version	-40	105	°C

Table 21. General operating conditions (continued)

1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.

2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics).

6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21.

Symbol	Parameter	Conditions	Min	Max	Unit
tVDD	VDD rise time rate	-	0	∞	μs/V
	VDD fall time rate	-	20	∞
tVDDA	VDDA rise time rate	-	0	∞
	VDDA fall time rate	-	20	∞

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 23 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

	Table 23. Embedded reset and power control block characteristics
--	------------------------------------------------------------------

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VPOR/PDR(1)	Power on/power down reset threshold	Falling edge(2)	1.80	1.88	1.96(3)	V
		Rising edge	1.84(3)	1.92	2.00	V

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VPOR/PDR⁽¹⁾	Power on/power down reset threshold	Falling edge⁽²⁾	1.80	1.88	1.96⁽³⁾	V
		Rising edge	1.84⁽³⁾	1.92	2.00	V

Table 23. Embedded reset and power control block characteristics (continued)

1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector monitors only VDD.

2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.

3. Data based on characterization results, not tested in production.

4. Guaranteed by design, not tested in production.

6.3.4 Embedded reference voltage

The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltage	-40°C < TA < +85°C	1.2	1.23	1.25	V
tSTART	ADC_IN17 buffer startup time	-	-	-	10(1)	μs
tS_vrefint	ADC sampling time when reading the internal reference voltage	-	4 (1)	-	-	μs
ΔVREFINT	Internal reference voltage spread over the temperature range	VDDA = 3 V	-	-	10(1)	mV
TCoeff	Temperature coefficient	-	-100(1)	-	100(1)	ppm/°C

Table 24. Embedded internal reference voltage

1. Guaranteed by design, not tested in production.

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 13: Current consumption measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the fHCLK frequency:
  • 0 wait state and Prefetch OFF from 0 to 24 MHz
  • 1 wait state and Prefetch ON above 24 MHz
• When the peripherals are enabled fPCLK = fHCLK

The parameters given in Table 25 to Table 27 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6 V(1)

Symbol	Parameter	Conditions	fHCLK	Typ	Max @ TA(2)	Unit
				All peripherals enabled
					85 °C
IDD	Supply current in Run mode, code executing from Flash	HSI or HSE clock, PLL on	48 MHz	22.0	22.8	mA
			48 MHz	26.8	30.2
			24 MHz	12.2	13.2

1. The gray shading is used to distinguish the values for STM32F030xC devices.

2. Data based on characterization results, not tested in production unless otherwise specified.

Symbol	Parameter	Conditions(2)	fHCLK	Typ	Max @ TA(3) (85 °C)	Unit
IDDA	Supply current in Run or Sleep mode, code executing from Flash memory or RAM	HSE bypass, PLL on	48 MHz	175	215	µA
			48 MHz	160	192
		HSE bypass, PLL off	8 MHz	3.9	4.9
			8 MHz	3.7	4.6

Table 26. Typical and maximum current consumption from the VDDA supply(1)

1. The gray shading is used to distinguish the values for STM32F030xC devices.

2. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, IDDA is independent of the frequency.

3. Data based on characterization results, not tested in production.

Symbol	Parameter	Conditions	Typ @VDD (VDD = VDDA)	Max(1)	Unit
			3.6 V	TA = 85 °C
IDD	Supply current in Stop mode	Regulator in run mode, all oscillators OFF	19	48
	Stop mode	Regulator in low-power mode, all oscillators OFF	5	32
	Supply current in Standby mode	LSI
Table 27. Typical and maximum consumption in Stop and Standby modes

1. Data based on characterization results, not tested in production unless otherwise specified.

Typical current consumption

The MCU is placed under the following conditions:

• VDD = VDDA = 3.3 V
• All I/O pins are in analog input configuration
• The Flash access time is adjusted to fHCLK frequency:
  • 0 wait state and Prefetch OFF from 0 to 24 MHz
  • 1 wait state and Prefetch ON above 24 MHz
• When the peripherals are enabled, fPCLK = fHCLK
• PLL is used for frequencies greater than 8 MHz
• AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and 500 kHz respectively

Symbol	Parameter	Conditions	Typ @VDD (VDD = VDDA) (3.6 V)	Max(1) (TA = 85 °C)	Unit
IDD	Supply current in Stop mode	Regulator in run mode, all oscillators OFF	19	48
		Regulator in low-power mode, all oscillators OFF	5	32
	Supply current in Standby mode	LSI ON and IWDG ON	2	-
IDDA	Supply current in Stop mode	VDD A monitoring ON, Regulator in run or low-power mode, all oscillators OFF	2.9	3.5
	Supply current in Standby mode	VDD A monitoring ON, LSI ON and IWDG ON	3.3	-	µA
		VDD A monitoring ON, LSI OFF and IWDG OFF	2.8	3.5
	Supply current in Stop mode	VDD A monitoring OFF, Regulator in run or low-power mode, all oscillators OFF	1.7	-
	Supply current in Standby mode	VDD A monitoring OFF, LSI ON and IWDG ON	2.3	-
		VDD A monitoring OFF, LSI OFF and IWDG OFF	1.4	-

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 46: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously, the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

$mathsf{I}_mathsf{SW} = mathsf{V}_mathsf{DDIME} × mathsf{f}_mathsf{SW} × mathsf{C}

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage

fSW is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

Symbol	Parameter	Conditions(1)	I/O toggling frequency (fSW)	Typ	Unit
ISW	I/O current consumption	VDDIOx = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS	4 MHz	0.18	mA
			8 MHz	0.37
			16 MHz	0.76
			24 MHz	1.39
			48 MHz

1. CS = 7 pF (estimated value).

6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 30 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode. The wakeup source from Standby mode is the WKUP1 pin (PA0).

All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Symbol	Parameter	Conditions	Typ @VDD = VDDA	Max	Unit
			= 3.3 V
tWUSTOP	Wakeup from Stop mode	Regulator in run mode	2.8	5
tWUSTANDBY	Wakeup from Standby mode	-	51	-	μs
tWUSLEEP	Wakeup from Sleep mode	-	4 SYSCLK cycles	-

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 14: High-speed external clock source AC timing diagram.

Symbol	Parameter(1)	Min	Typ	Max	Unit
fHSEext	User external clock source frequency	1	8	32	MHz
VHSEH	OSCIN input pin high level voltage	0.7 VDDIOx	-	VDDIOx
VHSEL	OSCIN input pin low level voltage	VSS	-	0.3 VDDIOx	V
tw(HSEH) tw(HSEL)	OSCIN high or low time	15	-	-
tr(HSE) tf(HSE)	OSCIN rise or fall time	-	-	20	ns

1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15.

Symbol	Parameter(1)	Min	Typ	Max	Unit
fLSE_ext	User external clock source frequency	-	32.768	1000	kHz
VLSEH	OSC32_IN input pin high level voltage	0.7 VDDIOx	-	VDDIOx	V
VLSEL	OSC32_IN input pin low level voltage	VSS	-	0.3 VDDIOx	V
tw(LSEH) tw(LSEL)	OSC32_IN high or low time	450	-	-	ns
tr(LSE) tf(LSE)	OSC32_IN rise or fall time	-	-	50	ns

1. Guaranteed by design, not tested in production.

Figure 15. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 33. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Conditions(1)	Min(2)	Typ	Max(2)	Unit
fOSC_IN	Oscillator frequency	-	4	8	32	MHz
RF	Feedback resistor	-	-	200	-	kΩ

Symbol	Parameter	Conditions(1)	Min(2)	Typ	Max(2)	Unit
fOSC_IN	Oscillator frequency	-	4	8	32	MHz
RF	Feedback resistor	-	-	200	-	kΩ

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time

4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results

obtained with typical external components specified in Table 34. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Conditions(1)	Min(2)	Typ	Max(2)	Unit
IDD	LSE current consumption	low drive capability	-	0.5	0.9
		medium-low drive capability	-	-	1
		medium-high drive capability	-	-	1.3	μA
		high drive capability	-	-	1.6
gm	Oscillator transconductance	low drive capability	5	-	-
		medium-low drive capability	8	-	-
		medium-high drive capability	15	-	-	μA/V
		high drive capability	25	-	-
tSU(LSE)(3)	Startup time	VDDIOx is stabilized	-	2	-	s

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers".

2. Guaranteed by design, not tested in production.

3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

Figure 17. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

6.3.8 Internal clock source characteristics

The parameters given in Table 35 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI) RC oscillator

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI	Frequency	-	-	8	-	MHz
TRIM	HSI user trimming step	-	-	1(2)	-	%
DuCyHSI	Duty cycle	-	45(2)	-	55(2)	%
ACCHSI	Accuracy of the HSI oscillator (factory calibrated)	TA = -40 to 85°C	-	±5	-	%
		TA = 25°C	-	±1(3)	-	%
tSU(HSI)	HSI oscillator startup time	-	1(2)	-	2(2)	μs
IDDA(HSI)	HSI oscillator power consumption	-	-	80	-	μA

Table 35. HSI oscillator characteristics(1)

1. VDDA = 3.3 V, TA = -40 to 85°C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. With user calibration.

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 36. HSI14 oscillator characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI14	Frequency	-	-	14	-	MHz
TRIM	HSI14 user-trimming step	-	-	-	1(2)	%
DuCy(HSI14)	Duty cycle	-	45(2)	-	55(2)	%
ACCHSI14	Accuracy of the HSI14 oscillator (factory calibrated)	TA = –40 to 85 °C	-	±5	-	%
tsu(HSI14)	HSI14 oscillator startup time	-	1(2)	-	2(2)	μs
IDDA(HSI14)	HSI14 oscillator power consumption	-	-	100	-	μA

1. VDDA = 3.3 V, TA = -40 to 85 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

Low-speed internal (LSI) RC oscillator

Table 37. LSI oscillator characteristics(1)

Symbol	Parameter	Min	Typ	Max	Unit
fLSI	Frequency	30	40	50	kHz

Table 37. LSI oscillator characteristics(1)

Symbol	Parameter	Min	Typ	Max	Unit
fLSI	Frequency	30	40	50	kHz

1. VDDA = 3.3 V, TA = -40 to 85 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

6.3.9 PLL characteristics

The parameters given in Table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Symbol	Parameter	Min	Typ	Max	Unit
fPLLIN	PLL input clock(1)	1(2)	8.0	24(2)	MHz
	PLL input clock duty cycle	40(2)	-	60(2)	%
fPLLOUT	PLL multiplier output clock	16(2)	-	48	MHz
tLOCK	PLL lock time	-	-	200(2)	μs
JitterPLL	Cycle-to-cycle jitter	-	-	300(2)	ps

Table 38. PLL characteristics

1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by fPLL_OUT.

2. Guaranteed by design, not tested in production.

6.3.10 Memory characteristics

Flash memory

The characteristics are given at TA = -40 to 85 °C unless otherwise specified.

Symbol	Parameter	Conditions	Min	Typ	Max(1)	Unit
tprog	16-bit programming time	TA = -40 to +85 °C	-	53.5	-	μs
tERASE	Page erase time(2)	TA = -40 to +85 °C	-	30	-	ms
tME	Mass erase time	TA = -40 to +85 °C	-	30	-	ms
IDD	Supply current	Write mode	-	-	10	mA
		Erase mode	-	-	12	mA
Vprog	Programming voltage	-	2.4	-	3.6	V

Table 39. Flash memory characteristics
----------------------------------------

1. Guaranteed by design, not tested in production.

2. Page size is 1KB for STM32F030x4/6/8 devices and 2KB for STM32F030xC devices

Symbol	Parameter	Conditions	Min(1)	Unit
NEND	Endurance	TA = -40 to +85 °C	1	kcycle
tRET	Data retention	1 kcycle(2) at TA = 85 °C	20	Years

Table 40. Flash memory endurance and data retention

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709.

Symbol	Parameter	Conditions	Level/ Class
VFESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	VDD = 3.3V, LQFP48, TA = +25 °C, fHCLK = 48 MHz, conforming to IEC 61000-4-2	3B
VEFTB	Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance	VDD = 3.3V, LQFP48, TA = +25°C, fHCLK = 48 MHz, conforming to IEC 61000-4-4	4B

Table 41. EMS characteristics

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol	Parameter	Conditions	Monitored frequency band	Max vs. [fHSE/fHCLK] 8/48 MHz	Unit
SEMI	Peak level	VDD = 3.6 V, TA = 25 °C, LQFP100 package compliant with IEC 61967-2	0.1 to 30 MHz	-3
			30 to 130 MHz 130 MHz to 1 GHz	23 17	dBμV
			EMI Level	4	-

Table 42. EMI characteristics

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol	Ratings	Conditions	Packages	Class	Maximum value(1)	Unit
VESD(HBM)	Electrostatic discharge voltage (human body model)	TA = +25 °C, conforming to JESD22-A114	All	2	2000	V
VESD(CDM)	Electrostatic discharge voltage (charge device model)	TA = +25 °C, conforming to ANSI/ESD STM5.3.1	All	C4(2) C3(3)	500(2) 250(3)	V

Table 43. ESD absolute maximum ratings

1. Data based on characterization results, not tested in production.

2. Applicable to STM32F030xC

3. Applicable to STM32F030x4, STM32F030x6, and STM32F030x8

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 44. Electrical sensitivities

Symbol	Parameter	Conditions	Class
LU	Static latch-up class	TA = +105 °C conforming to JESD78A	II level A

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 μA/+0 μA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in Table 45.

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol	Description	Negative injection	Positive injection	Unit
IINJ	Injected current on BOOT0 and PF1 pins	-0	NA	mA
	Injected current on PA9, PB3, PB13, PF11 pins with induced leakage current on adjacent pins less than 50 μA	-5	NA
	Injected current on PA11 and PA12 pins with induced leakage current on adjacent pins less than -1 mA	-5	NA
	Injected current on all other FT and FTf pins	-5	NA
	Injected current on PB0 and PB1 pins	-5	NA
	Injected current on PC0 pin	-0	+5
	Injected current on all other TTa, TC and RST pins	-5	+5

6.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VIL	Low level input voltage	TC and TTa I/O	-	-	0.3 VDDIOx+0.07(1)	V
		FT and FTf I/O	-	-	0.475 VDDIOx–0.2(1)
		BOOT0	-	-	0.3 VDDIOx–0.3(1)
		All I/Os except BOOT0 pin	-	-	0.3 VDDIOx
VIH	High level input voltage	TC and TTa I/O	0.445 VDDIOx+0.398(1)	-	-	V
		FT and FTf I/O	0.5 VDDIOx+0.2(1)	-	-
		BOOT0	0.2 VDDIOx+0.95(1)	-	-
		All I/Os except BOOT0 pin	0.7 VDDIOx	-	-
Vhys	Schmitt trigger hysteresis	TC and TTa I/O	-	200(1)	-	mV
		FT and FTf I/O	-	100(1)	-
		BOOT0	-	300(1)	-

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Ilkg	Input leakage current(2)	TC, FT and FTf I/O TTa in digital mode VSS ≤ VIN ≤ VDDIOx	-	-	± 0.1	μA
		TTa in digital mode VDDIOx ≤ VIN ≤ VDDA	-	-	1
		TTa in analog mode VSS ≤ VIN ≤ VDDA	-	-	± 0.2
		FT and FTf I/O (3) VDDIOx ≤ VIN ≤ 5 V	-	-	10
RPU	Weak pull-up equivalent resistor (4)	VIN = VSS	25	40	55	kΩ
RPD	Weak pull-down equivalent resistor(4)	VIN = VDDIOx	25	40	55	kΩ
CIO	I/O pin capacitance	-	-	5	-	pF

Table 46. I/O static characteristics (continued)

1. Data based on design simulation only. Not tested in production.

2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 45: I/O current injection susceptibility.

3. To sustain a voltage higher than VDDIOx + 0.3 V, the internal pull-up/pull-down resistors must be disabled.

4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 for standard I/Os, and in Figure 19 for 5 V tolerant I/Os. The following curves are design simulation results, not tested in production.

Figure 18. TC and TTa I/O input characteristics

Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics

62/91 DocID024849 Rev 3

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH).

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2:

• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 18: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or TC unless otherwise specified).

Symbol	Parameter	Conditions	Min	Max	Unit
VOL	Output low level voltage for an I/O pin	|IIO| = 8 mA	-	0.4	V
VOH	Output high level voltage for an I/O pin	VDDIOx ≥ 2.7 V	VDDIOx–0.4	-	V
VOL$^{(2)}$	Output low level voltage for an I/O pin	|IIO| = 20 mA	-	1.3	V
VOH$^{(2)}$	Output high level

Table 47. Output voltage characteristics(1)

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO.

2. Data based on characterization results. Not tested in production.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 20 and Table 48, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

OSPEEDRy [1:0] value(1)	Symbol	Parameter	Conditions	Min	Max	Unit
x0	fmax(IO)out	Maximum frequency(3)		-	2	MHz
	tf(IO)out	Output fall time	CL = 50 pF, VDDIOx ≥ 2.4 V	-	125	ns
	tr(IO)out	Output rise time		-	125
01	fmax(IO)out	Maximum frequency
Table 48. I/O AC characteristics(1)(2)

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0360 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design, not tested in production.

3. The maximum frequency is defined in Figure 20.

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0360 for a detailed description of Fm+ I/O configuration.

Figure 20. I/O AC characteristics definition

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VIL(NRST)	NRST input low level voltage	-	-	-	0.3 VDD+0.07(1)	V
VIH(NRST)	NRST input high level voltage	-	0.445 VDD+0.398(1)	-	-	V
Vhys(NRST)	NRST Schmitt trigger voltage hysteresis	-	-	200	-	mV
RPU	Weak pull-up equivalent resistor(2)	VIN = VSS	25	40	55	kΩ
VF(NRST)	NRST input filtered pulse	-	-	-	100(1)	ns
VNF(NRST)	NRST input not filtered pulse	2.7 < VDD < 3.6	300(3)	-	-	ns
		2.4 < VDD < 3.6	500(3)	-	-

1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

3. Data based on design simulation only. Not tested in production.

Figure 21. Recommended NRST pin protection

• 1. The external capacitor protects the device against parasitic resets.
• 1. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

6.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 50 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 21: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VDDA	Analog supply voltage for ADC ON	-	2.4	-	3.6	V
IDDA (ADC)	Current consumption of the ADC(1)	VDD = VDDA = 3.3 V	-	0.9	-	mA
fADC	ADC clock frequency	-	0.6	-	14	MHz
fS(2)	Sampling rate	-	0.05	-	1	MHz
fTRIG(2)	External trigger frequency	fADC = 14 MHz	-	-	823	kHz
		-	-	-	17	1/fADC
VAIN	Conversion voltage range	-	0	-	VDDA	V
RAIN(2)	External input impedance	See Equation 1 and Table 51 for details	-	-	50	kΩ
RADC(2)	Sampling switch resistance	-	-	-	1	kΩ
CADC(2)	Internal sample and hold capacitor	-	-	-	8	pF

Table 50. ADC characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VDD A	Analog supply voltage for ADC ON	-	2.4	-	3.6	V
IDDA (ADC)	Current consumption of the ADC$^{(1)}$	VDD = VDDA = 3.3 V	-	0.9	-	mA
fADC	ADC clock frequency	-	0.6	-	14	MHz
fS$^{(2)}$	Sampling rate	-	0.05	-	1	MHz
fTRIG$^{(2)}$	External trigger frequency	fADC = 14 MHz	-	-	823	kHz
VAIN	Conversion voltage range	-	0	-	VDDA	V
RAIN$^{(2)}$	External input impedance	See Equation 1 and Table 51 for details	-	-	50	kΩ
RADC$^{(2)}$	Sampling switch resistance	-	-	-	1	kΩ
CADC$^{(2)}$	Internal sample and hold capacitor	-	-	-	8	pF

Table 50. ADC characteristics (continued)

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 μA on IDDA and 60 μA on IDD should be taken into account.

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

Equation 1: RAIN max formulamathsf{R}_mathsf{AIN} < frac{mathsf{L}^mathsf{L∞} mathsf{T}_mathsf{S}}{mathsf{t}_mathsf{ADC} × mathsf{C}_mathsf{ADC} × ln(mathsf{2}^mathsf{N+2})} - mathsf{R}_mathsf{ADC}The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

• (1)
  Ts (cycles)
  tS (μs)
  RAIN max (kΩ)
• 1.5 0.11 0.4
• 7.5 0.54 5.9
• 13.5 0.96 11.4
• 28.5 2.04 25.2
• 41.5 2.96 37.2
• 55.5 3.96 50
• 71.5 5.11 NA
• 239.5 17.1 NA

Table 51. RAIN max for fADC = 14 MHz

1. Guaranteed by design, not tested in production.

Symbol	Parameter	Test conditions	Typ	Max(4)	Unit
ET	Total unadjusted error	fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.7 V to 3.6 V TA = -40 to 85 °C	±3.3	±4
EO	Offset error		±1.9	±2.8
EG	Gain error		±2.8	±3	LSB
ED	Differential linearity error		±0.7	±1.3
EL	Integral linearity error		±1.2	±1.7

Table 52. ADC accuracy(1)(2)(3)

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy.

1. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.

2. Data based on characterization results, not tested in production.

Figure 22. ADC accuracy characteristics

1. Refer to Table 50: ADC characteristics for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 12: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

6.3.17 Temperature sensor characteristics

Symbol	Parameter	Min	Typ	Max	Unit
TL(1)	VSENSE linearity with temperature	-	±1	±2	°C
Avg_Slope(1)	Average slope	4.0	4.3	4.6	mV/°C
V30	Voltage at 30 °C (± 5 °C)(2)	1.34	1.43	1.52	V
tSTART(1)	ADC_IN16 buffer startup time	-	-	10	μs
tS_temp(1)	ADC sampling time when reading the temperature	4	-	-	μs

1. Guaranteed by design, not tested in production.

2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3: Temperature sensor calibration values.

6.3.18 Timer characteristics

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tres(TIM)	Timer resolution	-	-	1	-	tTIMxCLK
		fTIMxCLK = 48 MHz	-	20.8	-	ns
	Timer external clock frequency on CH1 to CH4	-	-	fTIMxCLK/2	-	MHz
fEXT		fTIMxCLK = 48 MHz	-	24	-	MHz
	16-bit timer maximum period	-	-

Table 54. TIMx characteristics

Prescaler divider	PR[2:0] bits	Min timeout RL[11:0]= 0x000	Max timeout RL[11:0]= 0xFFF	Unit
/4	0	0.1	409.6
/8	1	0.2	819.2
/16	2	0.4	1638.4
/32	3	0.8	3276.8	ms
/64	4	1.6	6553.6
/128	5	3.2	13107.2
/256	6 or 7	6.4	26214.4

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler	WDGTB	Min timeout value	Max timeout value	Unit
1	0	0.0853	5.4613
2	1	0.1706	10.9226
4	2	0.3413	21.8453	ms
8	3	0.6826	43.6906

6.3.19 Communication interfaces

I 2 C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Symbol	Parameter	Min	Max	Unit
tAF	Maximum pulse width of spikes that are suppressed by the analog filter	50(2)	260(3)	ns

Table 57. I2C analog filter characteristics(1)
------------------------------------------------

1. Guaranteed by design, not tested in production.

2. Spikes with widths below tAF(min) are filtered.

3. Spikes with widths above tAF(max) are not filtered

SPI characteristics

Unless otherwise specified, the parameters given in Table 58 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics.

Symbol	Parameter	Conditions	Min	Max	Unit
fSCK 1/tc(SCK)		Master mode	-	18	MHz
	SPI clock frequency	Slave mode	-	18
tr(SCK) tf(SCK)	SPI clock rise and fall time	Capacitive load: C = 15 pF	-	6	ns
tsu(NSS)	NSS setup time	Slave mode 4Tpclk		-
th(NSS)	NSS hold time	Slave mode	2Tpclk + 10	- Tpclk/2 + 1
tw(SCKH) tw(SCKL)	SCK high and low time	Master mode, fPCLK = 36 MHz, presc = 4	Tpclk/2 -2
tsu(MI)		Master mode	4	-
tsu(SI)	Data input setup time	Slave mode	5	-
th(MI)		Master mode	4	-
th(SI)	Data input hold time	Slave mode	5	-	ns
ta(SO)(2)	Data output access time	Slave mode, fPCLK = 20 MHz	0	3Tpclk
tdis(SO)(3)	Data output disable time	Slave mode	0	18
tv(SO)	Data output valid time	Slave mode (after enable edge)	-	22.5
tv(MO)	Data output valid time	Master mode (after enable edge)	-	6
th(SO)	Data output hold time	Slave mode (after enable edge)	11.5	-
th(MO)		Master mode (after enable edge)	2	-
DuCy(SCK)	SPI slave input clock duty cycle	Slave mode	25	75	%

Table 58. SPI characteristics(1)

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

Figure 24. SPI timing diagram - slave mode and CPHA = 0

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

Figure 26. SPI timing diagram - master mode

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD–VSS	External main supply voltage	-0.3	4.0	V
VDDA–VSS	External analog supply voltage	-0.3	4.0	V
VDD–VDDA	Allowed voltage difference for VDD > VDDA	-	0.4	V
VIN(2)	Input voltage on FT and FTf pins	VSS - 0.3	VDDIOx + 4.0 (3)	V
	Input voltage on TTa pins	VSS - 0.3	4.0	V
	BOOT0	0	VDDIOx + 4.0 (3)	V
	Input voltage on any other pin	VSS -0.3	4.0	V
ΔVDDx	Variations between different VDD power pins	-	50	mV
VSSx -VSS	Variations between all the different ground pins	-	50	mV
VESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.12: Electrical sensitivity characteristics		-

Table 18. Voltage characteristics(1)
--------------------------------------

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values.

3. VDDIOx is internally connected with VDD pin.

Symbol	Ratings	Max.	Unit
ΣIVDD	Total current into sum of all VDD power lines (source)(1)	120
ΣIVSS	Total current out of sum of all VSS ground lines (sink)(1)	-120
IVDD(PIN)	Maximum current into each VDD power pin (source)(1)	100
IVSS(PIN)	Maximum current out of each VSS ground pin (sink)(1)	-100
IIO(PIN)	Output current sunk by any I/O and control pin	25
	Output current source by any I/O and control pin	-25	mA
ΣIIO(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	80
	Total output current sourced by sum of all I/Os and control pins(2)	-80
IINJ(PIN)(3)	Injected current on FT and FTf pins	-5/+0(4)
	Injected current on TC and RST pin	± 5
	Injected current on TTa pins(5)	± 5
ΣIINJ(PIN)	Total injected current (sum of all I/O and control pins)(6)	± 25

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the device. See note (2) below Table 52: ADC accuracy.

6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	150	°C

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	150	°C