STM32C011

Contents

Microcontroller

The STM32C011 is a microcontroller from STMicroelectronics. Contents. View the full STM32C011 datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Overview

Part: STMicroelectronics STM32C011x4/x6

Type: Arm Cortex-M0+ 32-bit MCU

Description: 32-bit Arm Cortex-M0+ MCU operating at up to 48 MHz with up to 32 KB Flash, 6 KB SRAM, and a wide range of integrated peripherals for consumer, industrial, appliance, and IoT applications.

Operating Conditions:

Supply voltage: 2.0 V to 3.6 V
Operating temperature: -40 to 125 °C
Max CPU frequency: 48 MHz

Absolute Maximum Ratings:

Max supply voltage: 4.0 V
Max continuous current: null
Max junction/storage temperature: 150 °C

Key Specs:

CPU: Arm Cortex-M0+ up to 48 MHz
Flash Memory: Up to 32 Kbytes with protection
SRAM: 6 Kbytes with hardware parity check
ADC: 12-bit, 0.4 μs, up to 13 external channels, 0 to 3.6 V conversion range
I/Os: Up to 18 fast I/Os, multiple 5 V-tolerant
Communication Interfaces: 1x I2C (1 Mbit/s), 2x USARTs (with master/slave synchronous SPI), 1x SPI (24 Mbit/s)
Timers: 1x 16-bit advanced motor control, 4x 16-bit general-purpose, 2x watchdogs, SysTick
Low-power modes: Sleep, Stop, Standby, Shutdown

Features:

Arm 32-bit Cortex-M0+ CPU up to 48 MHz
Memory Protection Unit (MPU)
CRC calculation unit
Multiple low-power modes
3-channel DMA controller
Calendar RTC with alarm
Serial Wire Debug (SWD) support

Applications:

Consumer domains
Industrial domains
Appliance domains
Internet of Things (IoT) solutions

Package:

SO8N (8 pins)
WLCSP12 (12 pins)
TSSOP20 (20 pins)
UFQFPN20 (20 pins)

Features

Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 48 MHz
-40°C to 85°C/105°C/125°C operating temperature
Memories
- Up to 32 Kbytes of flash memory with protection
- 6 Kbytes of SRAM with HW parity check
CRC calculation unit
Reset and power management
- Voltage range: 2.0 V to 3.6 V
- Power-on/Power-down reset (POR/PDR)
- Programmable Brownout reset (BOR)
- Low-power modes:Sleep, Stop, Standby, Shutdown
Clock management
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator with calibration
- Internal 48 MHz RC oscillator (±1 %)
- Internal 32 kHz RC oscillator (±5 %)
Up to 18 fast I/Os
- All mappable on external interrupt vectors
- Multiple 5 V-tolerant I/Os
3-channel DMA controller with flexible mapping
12-bit, 0.4 μs ADC (up to 13 ext. channels)
- Conversion range: 0 to 3.6 V
8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
Calendar RTC with alarm

Communication interfaces
- One I²C-bus interface supporting Fastmode Plus (1 Mbit/s) with extra current sink, supporting SMBus/PMBus and wakeup from Stop mode
- Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
- One SPI (24 Mbit/s) with 4- to 16-bit programmable bitframe, multiplexed with I²S interface
Development support: serial wire debug (SWD)
All packages ECOPACK 2 compliant

Table 1. Device summary

Reference	Part number
STM32C011x4	STM32C011F4, STM32C011J4
STM32C011x6	STM32C011F6, STM32C011J6, STM32C011D6

Contents STM32C011x4/x6

Pin Configuration

Figure 3. STM32C011JxM SO8N pinout

Figure 4. STM32C011DxY WLCSP12 ballout

Figure 5. STM32C011FxP TSSOP20 pinout

Figure 6. STM32C011FxU UFQFPN20 pinout

Table 11. Terms and symbols used in Table 12

Column	Symbol	Definition
Pin name	parenthesis under the pin name.	Terminal name corresponds to its by-default function at reset, unless otherwise specified in
	S	Supply pin
Pin type	I I/O Input / output pin	Input only pin
	FT RST Bidirectional reset pin with embedded weak pull-up resistor	5 V tolerant I/O Options for FT I/Os
I/O structure	_f	I/O, Fm+ capable
	_a	I/O, with analog switch function

	Column Symbol		Definition
	Note		Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Alternate functions Pin		Functions selected through GPIOx_AFR registers
functions	Additional functions		Functions directly selected/enabled through peripheral registers

		Pin
SO8N	WLCSP12	TSSOP20
1	B3	2
8	A4	3
2	C4	4
3	E4	5
4	F3	6
4	F3	7
4	F3	8
4	F3	9
-	F1	10
-	F1	11

Table 12. Pin assignment and description (continued)

		Pin
SO8N	WLCSP12	TSSOP20
-	F1	12
-	F1	13
-	E2	14
5	D1	15
-	-	-
-	-	-
5	D1	16
6	E2	17
7	B1	18
8	C2	19

Table 12. Pin assignment and description (continued)

		Pin
SO8N	WLCSP12	TSSOP20
8	A2	20
1	D3	1

^1. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.

^2. Upon reset, these pins are configured as SWD alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

			Table 13. Port A	alternate functi	on mapping (AF	0 to AF7)
Port	AF0	AF1	AF2	AF3	AF4	AF5
PA0	-	USART2_CTS	TIM16_CH1	-	USART1_TX	TIM1_CH1
PA1	SPI1_SCK/I2S1_ CK	USART2_RTS_ DE_CK	TIM17_CH1	-	USART1_RX	TIM1_CH2
PA2	SPI1_MOSI/I2S1 _SD	USART2_TX	TIM16_CH1N	TIM3_ETR	-	TIM1_CH3
PA3	-	USART2_RX	TIM1_CH1N	-	-	TIM1_CH4
PA4	SPI1_NSS/I2S1_ WS	USART2_TX	TIM1_CH2N	-	TIM14_CH1	TIM17_CH1N
PA5	SPI1_SCK/I2S1_ CK	USART2_RX	TIM1_CH3N	-	-	TIM1_CH1
PA6	SPI1_MISO/I2S1 _MCK	TIM3_CH1	TIM1_BKIN	-	-	TIM16_CH1
PA7	SPI1_MOSI/I2S1 _SD	TIM3_CH2	TIM1_CH1N	-	TIM14_CH1	TIM17_CH1
PA8	MCO	USART2_TX	TIM1_CH1	-	-	-
PA9	MCO	USART1_TX	TIM1_CH2	TIM3_ETR	-
PA10	-	USART1_RX	TIM1_CH3	MCO2	-	TIM17_BKIN
PA11	SPI1_MISO/I2S1 _MCK	USART1_CTS	TIM1_CH4	-	-	TIM1_BKIN2
PA12	SPI1_MOSI/I2S1 _SD	USART1_RTS_ DE_CK	TIM1_ETR	-	-	I2S_CKIN
PA13	SWDIO	IR_OUT	-	TIM3_ETR	USART2_RX	-
PA14	SWCLK	USART2_TX	-	-	-	-

Table 14. Port A alternate function mapping (AF8 to AF15)

					• .	•
Port	AF8	AF9	AF10	AF11	AF12	AF13
PA8	SPI1_NSS/I2S1_ WS	TIM1_CH2N	TIM1_CH3N	TIM3_CH3	TIM3_CH4	TIM14_CH1
PA14	SPI1_NSS/I2S1_ WS	USART2_RX	TIM1_CH1	MCO2	USART1_RTS_ DE_CK	-

Table 15. Port B alternate function mapping (AF0 to AF7)

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
PB6	USART1_TX	TIM1_CH3	TIM16_CH1N	TIM3_CH3	USART1_RTS_ DE_CK	USART1_CTS	I2C1_SCL	I2C1_SMBA
PB7	USART1_RX	TIM1_CH4	TIM17_CH1N	TIM3_CH4	-	-	I2C1_SDA	EVENTOUT

Table 16. Port B alternate function mapping (AF8 to AF15)

Port	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
PB6	SPI1_MOSI/I2S1 _SD	SPI1_MISO/I2S1 _MCK	SPI1_SCK/I2S1_ CK	TIM1_CH2	TIM3_CH1	TIM3_CH2	TIM16_BKIN	TIM17_BKIN
PB7	-	USART2_CTS	TIM16_CH1	TIM3_CH1	-	-	I2C1_SCL	-

Table 17. Port C alternate function mapping (AF0 to AF7)

-					i	i
Port	AF0	AF1	AF2	AF3	AF4	AF5
PC14	USART1_TX	TIM1_ETR	TIM1_BKIN2	-	-	-
PC15	OSC32_EN	OSC_EN	TIM1_ETR	TIM3_CH3	-	-

Table 18. Port C alternate function mapping (AF8 to AF15)

Port	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
PC14	IR_OUT	USART2_RTS_ DE_CK	TIM17_CH1	TIM3_CH2	-	-	I2C1_SDA	EVENTOUT

Table 19.	Port F	alternate	function	mapping
-----------	--------	-----------	----------	---------

	*		Ta b le 1 9.	Po t F l te te r a rn a	fu t io nc n m ap p	in g
Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5
P F 2	M C O	T I M 1_ C H 4	-	-	-	-

Electrical Characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.

5.1.6 Power supply scheme

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 20, Table 21 and Table 22 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

All voltages are defined with respect to VSS.

Table 20. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD - VSS	External supply voltage	-0.3	4.0
(1) VIN	Input voltage on pin	-0.3	VDD + 4.0(2)	V

^1. VIN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values.

Table 21. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)	100
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)	100
	Output current sunk by any I/O and control pin	20
IIO(PIN)	Output current sourced by any I/O and control pin	20
	Total output current sunk by sum of all I/Os and control pins(1)	80	mA
∑I(PIN)	Total output current sourced by sum of all I/Os and control pins(1)	80
IINJ(PIN)(1)(2)	Injected current on a FT_xx pin	-5 / 0
∑IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(3)	-25

^2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.
When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 22. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	130	°C

5.3 Operating conditions

5.3.1 General operating conditions

Table 23. General operating conditions

Symbol	Parameter	Conditions	Min	Max	Unit
VDD	Standard operating voltage	-	2.0(1)	3.6	V
VIN	I/O input voltage	-	-0.3	Min (VDD + 3.6, 5.5)(2)	V
fPCLK	APB clock frequency	-	-	48	MHz
		Suffix 6(4)	-40	85
TA	Ambient temperature(3)	(4) Suffix 7	-40	105	°C
		Suffix 3(4)	-40	125
		Suffix 6(4)	-40	105
TJ	Junction temperature	(4) Suffix 7	-40	125	°C
		Suffix 3(4)	-40	130

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 24 are derived from tests performed under the ambient temperature condition summarized in Table 23.

Table 24. Operating conditions at power-up / power-down

Symbol	Parameter	Min	Max	Unit
	VDD rise time rate	0	∞	μs/V
tVDD	VDD fall time rate	10	∞

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 25 are derived from tests performed under the ambient temperature conditions summarized in Table 23.

Table 25. Embedded reset and power control block characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tRSTTEMPO(1)	POR temporization when VDD crosses VPOR	VDD rising	-	270	500	μs
VPOR(1)	Power-on reset threshold	-	1.9	1.94	1.98	V
VPDR(1)	Power-down reset threshold	-	1.88	1.92	1.96	V

^2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.

^3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.5: Thermal characteristics.

^4. Temperature range digit in the order code. See Section 7: Ordering information.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	Brownout reset threshold 1	VDD rising	2.05	2.10	2.18	V
VBOR1		VDD falling	1.95	2.00	2.08
		VDD rising	2.20	2.31	2.38
VBOR2	Brownout reset threshold 2	VDD falling	2.10	2.21	2.28	V
		VDD rising	2.50	2.62	2.68
VBOR3	Brownout reset threshold 3	VDD falling	2.40	2.52	2.58	V
		VDD rising	2.80	2.91	3.00

VDD falling 2.70 2.81 2.90

Table 25. Embedded reset and power control block characteristics (continued)

5.3.4 Embedded voltage reference

VBOR4 Brownout reset threshold 4

The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltage	-	1.182	1.212	1.232	V
(1)(2) tS_vrefint	ADC sampling time when reading the internal reference voltage	-	4	-	-	μs
tstart_vrefint(2)	Start time of reference voltage buffer when ADC is enable	-	-	8	12	μs
IDD(VREFINTBUF)(2)	VREFINT buffer consumption from VDD when converted by ADC	-	9	13.5	23	μA
∆VREFINT(2)	Internal reference voltage spread over the temperature range	VDD = 3 V	-	30	50	mV
TCoeff	Averange temperature coefficient	-	-	20	70	ppm/°C
ACoeff	Long term stability	1000 hours, T = 25 °C	-	300	1000	ppm

Table 26. Embedded internal voltage reference

Vhyst_POR_PDR Hysteresis of VPOR and VPDR - - 20 - mV Vhyst_BOR Hysteresis of VBORx - - 100 - mV IDD(BOR)(1) BOR consumption - - 2.2 2.5 μA

^1. Specified by design – Not tested in production.

^1. The shortest sampling time can be determined in the application by multiple iterations.

^2. Specified by design – Not tested in production.

Figure 11. VREFINT vs. temperature

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 10: Current consumption measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:

All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table "Number of wait states according to CPU clock (HCLK) frequency" available in the RM0490 reference manual).
When the peripherals are enabled fPCLK = fHCLK
For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS

Unless otherwise stated, values given in Table 27 through Table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Table 27. Current consumption in Run mode from flash memory at different die temperatures

Cor ditions Ty /p Ma x ⁽¹⁾
Symbol Parameter General ⁽²⁾ f _HCLK Fetch
from ⁽³⁾ 25
°C 85
°C 105
°C 125
°C 25
°C 85
°C 105
°C 125
°C Unit
48 MHz 3.05 3.15 3.25 3.35 3.60 3.80 4.10 4.60
32 MHz 2.10 2.15 2.25 2.35 2.50 2.70 3.00 3.50
24 MHz 1.80 1.85 1.90 2.05 2.10 2.40 2.70 3.20
16 MHz 1.25 1.30 1.35 1.45 1.50 1.70 2.00 2.50
8 MHz 0.655 0.710 0.765 0.865 0.790 1.10 1.40 1.90
4 MHz 0.3654 0.420 0.470 0.570 0.460 0.700 0.980 1.50
2 MHz 0.225 0.270 0.325 0.425 0.290 0.540 0.820 1.40
1 MHz 0.150 0.200 0.250 0.350 0.200 0.450 0.730 1.30
500 kHz 0.115 0.160 0.215 0.315 0.160 0.410 0.690 1.20
l · Supply current in 125 kHz Flash 0.0875 0.135 0.185 0.285 0.130 0.380 0.650 1.20 mA
I _DD(Run) Run mode 32.768 kHz memory 0.082 0.130 0.180 0.280 0.120 0.370 0.650 1.20 ШA
48 MHz 3.40 3.50 3.55 3.60 3.90 4.10 4.40 4.90
24 MHz 2.25 2.30 2.35 2.45 2.60 2.80 3.10 3.60
12 MHz 1.45 1.50 1.55 1.65 1.70 1.90 2.20 2.70
f _HCLK = f _HSI48/HSIDIV 6 MHz 1.05 1.10 1.15 1.20 1.20 1.40 1.70 2.20
( > 32 kHz),
f _HCLK = f _LSI 3 MHz 0.855 0.880 0.925 1.00 0.960 1.20 1.50 2.00
( = 32 kHz) 1.5 MHz 0.750 0.780 0.825 0.915 0.840 1.10 1.40 1.90
750 kHz 0.700 0.730 0.775 0.865 0.780 1.00 1.30 1.80
375 kHz 0.675 0.705 0.750 0.840 0.760 0.970 1.30 1.80
32 kHz 0.082 0.130 0.180 0.280 0.120 0.370 0.650 1.20

^1. Evaluated by characterization – Not tested in production.

^2. V_DD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

^3. Prefetch and cache enabled when fetching from flash memory.

Table 28. Current consumption in Run mode from SRAM at different die temperatures

		Co n	d i t ion s			Ty	p		( 1) Ma x
Sy bo l m	Pa te ra me r	( 2) Ge l ne ra	fHC LK	h fro Fe tc ( 3) m	2 5 °C	8 5 °C	1 0 5 °C	1 2 5 °C	2 5 °C
			4 8 M Hz		2. 8 0	2. 9 0	2. 9 5	3. 0 5	3. 2 0
			3 2 M Hz		1. 9 0	1. 9 5	2. 0 0	2. 1 0	2. 2 0
		fHC fHS = LK E_ byp ass	2 4 M Hz		1. 4 5	1. 0 5	1. 5 5	1. 6 5	1. 0 7
			1 6 M Hz		0. 9 9 0	1. 0 5	1. 1 0	1. 2 0	1. 2 0
			8 M Hz		0. 5 3 5	0. 5 8 5	0. 6 3 5	0. 7 3 5	0. 6 3 0
	( >3 2. 7 6 8 k Hz ), fHC fLS = LK E_ byp ass ( =3 2. 7 6 8 k Hz )	4 M Hz 2 M Hz		0. 3 0 5	0. 3 5 5	0. 4 0 5	0. 5 0 5	0. 3 8 0	0. 6 3 0
				0. 1 9 5	0. 2 4 0	0. 2 9 5	0. 3 9 0	0. 2 0 5	0. 0 0 5
			1 M Hz		0. 1 3 5	0. 1 8 5	0. 2 3 5	0. 3 3 5	0. 1 8 0
			5 0 0 k Hz		0. 1 1 0	0. 1 5 5	0. 2 0 5	0. 3 0 5	0. 1 5 0
IDD	Su ly p p in t cu rre n
( Ru n)	Ru de n m o		3 2. 6 8 7 k Hz		0. 0 8 2	0. 1 3 0	0. 1 8 0	0. 2 8 0	0. 1 2 0
			4 8 M Hz		3. 1 5	3. 2 0	3. 2 5	3. 3 0	3. 5 0
			2 4 M Hz		1. 9 0	1. 9 5	2. 0 0	2. 0 5	2. 1 0
			1 2 M Hz		1. 3 0	1. 3 0	1. 3 5	1. 4 5	1. 0 5
		fHC fHS = LK I48 /HS IDI V	6 M Hz		0. 9 6 5	0. 9 9 5	1. 0 5	1. 1 5	1. 1 5
	( ), 3 2 k Hz > fHC fLS = LK I	3 M Hz		0. 8 1 0	0. 8 3 5	0. 8 8 0	0. 9 7 0	0. 9 0 0	1. 2 0
	( ) 3 2 k Hz =	1. 5 M Hz		0. 7 3 0	0. 7 6 0	0. 8 0 0	0. 8 9 0	0. 8 1 0	1. 1 0
			0 k Hz 7 5		0. 6 9 0	0. 2 0 7	0. 6 7 5	0. 8 5 5	0. 0 7 7
			3 7 5 k Hz		0. 6 7 0	0. 7 0 0	0. 7 4 5	0. 8 3 5	0. 7 5 0
			3 2 k Hz		0. 0 8 2	0. 1 3 0	0. 1 8 0	0. 2 8 0	0. 1 2 0

^2. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

^3. Code compiled with high optimization for space in SRAM.

Table 29. Typical current consumption in Run depending on code executed

		C	onditions		Typ		Typ
Symbol	Parameter	General ⁽¹⁾	Code Reduced code ⁽³⁾	Fetch from ⁽²⁾	25 °C 3.40	Unit	25 °C 70.8
			Coremark	]	3.15		65.6
			Dhrystone Fibonacci	Flash memory	3.20 2.40		66.7 50.0
		f _HCLK = f _{HSE_bypass} =	WhileLoop		1.80		37.5
		48 MHz	Reduced code ⁽³⁾ Coremark		2.80 2.70		58.3 56.3
			Dhrystone Fibonacci	SRAM	2.70 2.85		56.3 59.4
			WhileLoop		2.15	mA	44.8
			Reduced code ⁽³⁾		1.25	ШA	78.1
			Coremark	Flash memory	1.15		71.9
		f _HCLK = f _{HSE_bypass} =	Dhrystone Fibonacci		1.15 0.835		71.9 52.2
l	Supply current in		WhileLoop		0.645		40.3
I _DD(Run)	Run mode	16 MHz	Reduced code ⁽³⁾ Coremark		0.990 0.950		61.9 59.4
			Dhrystone	SRAM	0.945		59.1
			Fibonacci WhileLoop Reduced code ⁽³⁾ Coremark		1.00 0.775 0.225 0.210		62.5 48.4 112.5 105.0
			Dhrystone Fibonacci	Flash memory	0.210 0.175		105.0 87.5
		f _HCLK = f _{HSE_bypass} =	WhileLoop		0.150	μA	75.0
		2 MHz	Reduced code ⁽³⁾ Coremark		0.195 0.190	μΑ	97.5 95.0
			Dhrystone Fibonacci WhileLoop	SRAM	0.190 0.195 0.165		95.0 97.5 82.5

		C	onditions		Typ		Typ	,
Symbol	Parameter	General ⁽¹⁾ f _HCLK = f _HSI48/HSIDIV = 48 MHz (HSIDIV = 1)	Code Reduced code ⁽³⁾ Coremark Dhrystone Fibonacci WhileLoop Reduced code ⁽³⁾ Coremark Dhrystone Fibonacci	Fetch from ⁽²⁾ Floob Flash memory SRAM	25 °C 3.75 3.50 3.55 2.75 2.15 3.15 3.05 3.05 3.20	Unit	25 °C 78.1 72.9 74.0 57.3 44.8 65.6 63.5 63.5 66.7	Unit
			WhileLoop		2.50	mA	52.1	110/MHz
	Supply	f _HCLK = f _HSI48/HSIDIV = 12 MHz	Reduced code ⁽³⁾ Coremark Dhrystone Fibonacci WhileLoop	Flash memory	1.45 1.40 1.40 1.15 1.00	ШA	120.8 116.7 116.7 95.8 83.3	μΑ/MHz
I _DD(Run)	current in Run mode rtarrinodo	(HSIDIV = 4) f _HCLK = f _HSI48/HSIDIV = 3 MHz	Reduced code ⁽³⁾ Coremark Dhrystone Fibonacci WhileLoop Reduced code ⁽³⁾ Coremark Dhrystone Fibonacci WhileLoop	SRAM Flash memory	1.30 1.25 1.25 1.30 1.10 0.855 0.835 0.835 0.780 0.745		108.3 104.2 104.2 108.3 91.7 285.0 278.3 278.3 260.0 248.3
		= 3 MHz (HSIDIV = 16)	Reduced code ⁽³⁾		0.810	μΑ	270.0	μΑ/MHz
		(1.0.0.14	Coremark Dhrystone Fibonacci WhileLoop	SRAM	0.800 0.800 0.810 0.770		266.7 266.7 270.0 256.7	7

^2. Prefetch and cache enabled when fetching from flash

^3. Reduced code used for characterization results provided in Table 27.

Table 30. Current consumption in Sleep mode

Symbol Parameter		Conditions			Ty	/p		Max ⁽¹⁾
Symbol	Parameter	Ge	neral	f _HCLK	25 °C	85 °C	105 °C	125 °C
				48 MHz	1.20	1.20	1.25	1.35
		All peripherals		24 MHz	0.92	0.95	0.99	1.10
		disabled,		12 MHz	0.79	0.81	0.86	0.95
		f_HCLK = f_HSI48/HSIDIV ( > 32 kHz),		6 MHz	0.72	0.75	0.79	0.88
		f _HCLK = f _LSI		1.5 MHz	0.67	0.70	0.74	0.83
		( = 32 kHz)		375 kHz	0.66	0.69	0.73	0.82
				32 kHz	0.08	0.13	0.18	0.28
			Flash memory enabled	48 MHz	0.820	0.875	0.930	1.05
Supply			32 MHz	0.575	0.630	0.680	0.785	0.800
			24 MHz	0.450	0.500	0.555	0.655	0.630
			16 MHz	0.325	0.380	0.430	0.535	0.460
I _DD(Sleep)	current in Sleep
	mode			2 MHz	0.110	0.160	0.210	0.310
		All peripherals disabled,		500 kHz	0.0875	0.135	0.185	0.285
		f _HCLK = f _{HSE_bypass}		32.768 kHz	0.0805	0.125	0.180	0.280
		( > 32.768 kHz),		48 MHz	0.815	0.870	0.925	1.05
		f _HCLK = f _{LSE_bypass} ( = 32.768 kHz)		32 MHz	0.570	0.620	0.675	0.775
		,		24 MHz	0.445	0.495	0.545	0.650
		Flash memory disabled (flash memory power-	16 MHz	0.320	0.375	0.425	0.525	0.460
		down sleep mode)	8 MHz	0.200	0.245	0.295	0.395	0.290
			2 MHz	0.105	0.150	0.205	0.300	0.160
				500 kHz	0.0815	0.130	0.180	0.280
				32.768 kHz	0.0745	0.120	0.170	0.270

Table 31. Current consumption in Stop mode

Ty /p Ma x ⁽¹⁾
Symbol Parameter Conditions V _DD 25
°C 85
°C 105
°C 125
°C 25
°C 85
°C 105
°C 125
°C Unit
2 V 79.0 125 175 275 110 350 610 1100
All clocks off 2.4 V 79.0 125 175 275 110 350 610 1100
All clocks off 3 V 80.0 125 180 275 110 350 610 1100
3.6 V 81.5 130 180 280 110 350 610 1100
2 V 70.5 120 170 270 97.0 340 600 1100
All clocks off Flash memory in power-down stop 2.4 V 72.0 120 170 270 98.0 340 600 1100
mode 3 V 73.5 120 170 270 100 340 600 1100
3.6 V 75.0 120 175 270 110 340 600 1100
2 V 78.0 125 175 275 110 350 610 1100
1 Supply current RTC enabled and supplied with 2.4 V 78.5 125 175 275 110 350 610 1100 μA
I _DD(Stop) in Stop mode LSE bypass (32.768 kHz) 3 V 80.0 125 180 275 110 350 610 1100 μΛ
3.6 V 82.0 130 180 280 110 350 610 1100
RTC enabled and supplied with 2 V 71.0 120 170 270 97.0 340 600 1100
LSE bypass (32.768 kHz) 2.4 V 72.5 120 170 270 98.0 340 600 1100
Flash memory in power-down stop 3 V 74.0 120 170 270 100 340 600 1100
mode 3.6 V 75.5 120 175 270 110 340 600 1100
2 V 605 630 675 765 640 850 1100 1600
HSI Kernel on 2.4 V 605 630 675 765 640 850 1100 1600
3 V 605 630 675 765 640 850 1200 1600
3.6 V 605 635 680 770 640 850 1200 1600

^1. Evaluated by characterization – Not tested in production.

Table 32. Current consumption in Standby mode

		Conditions			Ty	/p			Ma	x ⁽¹⁾
Symbol	Parameter		V_DD	25 °C	85 °C	105 °C	125 °C	25 °C	85 °C	105 °C
			2 V	6.75	7.70	8.55	10.5	7.50	8.90	11.0
	Supply current in		2.4 V	7.05	8.00	8.85	11.0	7.70	9.10	11.0
			3 V	7.45	8.45	9.45	12.0	8.20	9.70	12.0
1 .			3.6 V	7.90	8.95	10.0	12.5	8.70	11.0	13.0
DD(Standby)	Clariaby	IWDG	2 V	7.30	8.35	9.20	11.5	8.10	9.50	12.0
	mode	enabled and	2.4 V	7.65	8.65	9.60	11.5	8.30	9.80	12.0
		clocked by	3 V	8.10	9.20	10.0	12.5	8.90	11.0	13.0
		LSI	3.6 V	8.60	9.75	11.0	13.5	9.50	12.0	14.0

Table 33. Current consumption in Shutdown mode

Symbol	Parameter	Parameter Conditions		Typ			Max ⁽¹⁾				Unit
Cymbol	- aramotor	Conditions	V_DD	25 °C	85 °C	105 °C	125 °C	25 °C	85 °C	105 °C	125 °C
DD (0) ( )	Supply		2 V	9.00	290	835	2350	55	920	2700	7600
	current in		2.4 V	13.0	320	915	2550	62	970	2900	7900
			off	3.0 V	19.0	375	1050	2900	72	1200	3300
			mode		3.6 V	31.0	460	1250	3350	95	1400

^1. Evaluated by characterization – Not tested in production.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 49: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see Table 34: Current consumption of peripherals), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

$I_SW = V_DDIO1 × f_SW × Cwhere

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

VDDIO1 is the I/O supply voltage

fSW is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
- when the peripheral is clocked on
- when the peripheral is clocked off
Ambient operating temperature and supply voltage conditions summarized in Table 20: Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Table 34. Current consumption of peripherals

Peripheral	Bus	Consumption in μA/MHz
IOPORT bus		0.72
GPIOA		1.64
GPIOB	IOPORT	1.64
GPIOC		0.82
GPIOF		0.74
Bus matrix	AHB	0.31
All AHB peripherals		8
DMA1	ALID	2.64
FLASH	AHB	4.56
SRAM1		0.01
CRC1		0.48
All APB peripherals		30.76
AHB to APB bridge (2)		0.32
TIM3		3.66
RTCAPB		1.13
WWDG1		0.48
USART2	ADD	2.01
I2C1	APB	3.44
I2C1 independent clock domain		2.59
DBGMCU1		0.09
PWR		0.3
SYSCFG		0.4
TIM1		5.84

SPI1 APB 3.18 SPI1 independent clock domain 1.44 USART1 2.22 USART1 independent clock domain 5.77 TIM14 1.42 TIM16 2.54 TIM17 2.45 ADC1 1.92 ADC1 independent clock domain 0.12 All peripherals 43.56 Peripheral Bus Consumption in μA/MHz

Table 34. Current consumption of peripherals (continued)

5.3.6 Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in Table 35 are the latency between the event and the execution of the first user instruction.

Table 35. Low-power mode wakeup times(1)

Symbol	Parameter		Conditions	Typ	Max	Unit
	Wakeup time from Sleep to Run	HCLK = HSI48/4 =	Transiting to Run-mode execution in flash memory powered during Sleep mode	10	12	CPU clock cycles
tWUSLEEP	mode	12 MHz	Transiting to Run-mode execution in flash memory not powered during Sleep mode	4.75	5.02	μs
		Clock after	Transiting to Run-mode execution in flash memory powered during Stop mode	2.7	3.1
tWULPSTOP	Wakeup time from Stop mode	wakeup is HCLK = HSI48/4 = 12 MHz	Transiting to Run-mode execution in flash memory not powered during Stop mode	5.9	6.4
			Transiting to Run-mode execution in SRAM	2.5	2.9	μs
tWUSTBY	Wakeup time from Standby mode	Clock after wakeup is HCLK = HSI48/4 = 12 MHz	Transiting to Run mode	23	35
tWUSHDN	Wakeup time from Shutdown mode	Clock after wakeup is HCLK = HSI48/4 = 12 MHz	Transiting to Run mode	385	466

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.13. See Figure 12 for recommended clock input waveform.

Table 36. High-speed external user clock characteristics⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
f _{HSE_ext}	User external clock source frequency	-	-	8	48	MHz
V _HSEH	Digital OSC_IN input pin high level voltage	-	0.7 V _DD	-	V _DD	V
V _HSEL	Digital OSC_IN input pin low level voltage	-	V _SS	-	0.3 V _DD	V
t _w(HSEH) / t _w(HSEL)	Digital OSC_IN high or low time	-	7	-	-	ns

^1. Specified by design – Not tested in production.

Figure 12. High-speed external clock source AC timing diagram

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.13. See Figure 13 for recommended clock input waveform.

Table 37. Low-speed external user clock characteristics⁽¹⁾

	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Ī	f _{LSE_ext}	User external clock source frequency	-	-	32.768	1000	kHz

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V _LSEH	OSC32_IN input pin high level voltage	-	0.7 V _DDIO1	-	V _DDIO1	V
V_{LSEL}	OSC32_IN input pin low level voltage	-	V _SS	-	0.3 V _DDIO1
t _w(LSEH) / t _w(LSEL)	OSC32_IN high or low time	-	250	-	-	ns

Table 37. Low-speed external user clock characteristics⁽¹⁾ (continued)

Figure 13. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 38. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Conditions⁽²⁾ Min Symbol Parameter αvΤ Max Unit Oscillator frequency 4 48 MHz fosc inR_{F}Feedback resistor 200 kΩ

Table 38. HSE oscillator characteristics⁽¹⁾

^1. Specified by design – Not tested in production.

Table 38. HSE oscillator characteristics(1) (continued)

Symbol	Parameter	Conditions(2)	Min	Typ	Max	Unit
		During startup(3)	-	-	5.5
		VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz	-	0.58	-
		VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz	-	0.59	-
IDD(HSE)	HSE current consumption	VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz	-	0.89	-	mA
		VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz	-	1.14	-
		VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz	-	1.94	-
Gm	Maximum critical crystal transconductance	Startup	-	-	1.5	mA/V
tSU(HSE)(4)	Startup time	VDD is stabilized	-	2	-	ms

1. Specified by design Not tested in production.
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
1. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
1. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

Figure 14. Typical application with an 8 MHz crystal

REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Conditions(2)	Min	Typ	Max	Unit
IDD(LSE)	LSE current consumption	LSEDRV = 0 Medium high drive capability	-	500	-	nA
		LSEDRV = 1 High drive capability	-	630	-
Gmcritmax	Maximum critical crystal	LSEDRV = 0 Medium high drive capability	-	-	1.7
	gm	LSEDRV = 1 High drive capability	-	-	2.7	μA/V

Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

tSU(LSE)(3) Startup time VDD is stabilized - 2 - s

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

^1. Specified by design – Not tested in production.

^2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers".

^3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Figure 15. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

5.3.8 Internal clock source characteristics

The parameters given in Table 40 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI48) RC oscillator

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI48	HSI48 Frequency	VDD=3.0 V, TA=30 °C	47.92	-	48.40	MHz
	HSI48 oscillator frequency	TA= 0 to 85 °C	-1	-	1	%
∆Temp(HSI)(1)	drift over temperature and VDD full voltage range	TA= -40 to 125 °C	-2.5	-	2	%
		From code 127 to 128	-8	-6	-4
TRIM(1)	HSI48 oscillator frequency user trimming step	From code 63 to 64 From code 191 to 192	-5.8	-3.8	-1.8	%
		For all other code increments	0.2	0.3	0.4 55
DHSI48(2)	Duty cycle	-	45	-		%
tsu(HSI48)(2)	HSI48 oscillator start-up time	-	-	1.4	1.8	μs
tstab(HSI48)(2)	HSI48 oscillator stabilization time	at 1% of target frequency	-	1.5	3.6	μs
IDD(HSI48)(1)	HSI48 oscillator power consumption	-	-	525	570	μA

Table 40. HSI48 oscillator characteristics

^1. Based on characterization results, not tested in production

^2. Specified by design – Not tested in production.

Figure 16. HSI48 frequency versus temperature

Low-speed internal (LSI) RC oscillator

Table 41. LSI oscillator characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
		VDD = 3.3 V, TA = 25 °C	31.04	32	32.96
fLSI	LSI frequency	VDD = 2 V to 3.6 V, TA = -40 to 125 °C	29.5 (1)	-	34(1)	kHz
tSU(LSI)(2)	LSI oscillator start-up time	-	-	80	130	μs
tSTAB(LSI)(2)	LSI oscillator stabilization time	5% of final frequency	-	125	180	μs
IDD(LSI)(2)	LSI oscillator power consumption	-	-	110	180	nA

^1. Evaluated by characterization – Not tested in production.

5.3.9 flash memory characteristics

Table 42. Flash memory characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tprog	Word programming time	64 bits	-	85.0	125.0	μs
	Row (32 double word) programming time	Normal programming	-	2.7	4.6
tprog_row		Fast programming	-	1.7	2.8
	Page (2 Kbyte) programming	Normal programming	-	21.8	36.6	ms
tprog_page	time	Fast programming	-	13.7	22.4
tERASE	Page (2 Kbyte) erase time	-	-	22.0	40.0

^2. Specified by design – Not tested in production.

Table 42. Flash memory characteristics(1) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	Bank (32 Kbyte(2))	Normal programming	-	0.4	0.6
tprog_bank	programming time	Fast programming	-	0.2	0.4	s
tME	Mass erase time	-	-	22.1	40.1	ms
	Average consumption from VDD	Programming	-	3.0	-
IDD(FlashA)		Page erase	-	3.0	-	mA
		Mass erase	-	5.0	-
IDD(FlashP)	Maximum current (peak)	Programming, 2 μs peak duration	-	7.0	-	mA
		Erase, 41 μs peak duration	-	7.0	-

Table 43. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TJ = -40 to +130 °C 10 kcycles
1 kcycle(2) at TA = 85 °C 30
1 kcycle(2) at TA = 105 °C 15
1 kcycle(2) at TA = 125 °C 7 Years
tRET Data retention 10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10

^1. Evaluated by characterization – Not tested in production..

^2. Values provided also apply to devices with less flash memory than one 32 Kbyte bank

^2. Cycling performed over the whole temperature range.

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V_DD and V_SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 44. They are based on the EMS levels and classes defined in application note AN1709.

Symbol	Parameter	Conditions	Level/ Class
V _FESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	V_{DD}$ = 3.3 V, $T_{A}$ = +25 °C, $f_{HCLK}$ = 48 MHz, LQFP48, conforming to IEC 61000-4-2	2B
V _EFTB	Fast transient voltage burst limits to be applied through 100 pF on $V_{DD}$ and $V_{SS}pins to induce a functional disturbance	V _DD = 3.3 V, T _A = +25 °C, f _HCLK = 48 MHz, LQFP48, conforming to IEC 61000-4-2	4B

Table 44. EMS characteristics

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pregualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

corrupted program counter
unexpected reset
critical data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol	Parameter	Conditions	Monitored	Max vs. [fHSE/fCPU]	Max vs. [fHSI/fCPU]	Unit
			frequency band	48 MHz / 48 MHz	48 MHz / 48 MHz
		VDD = 3.6 V, TA = 25 °C, LQFP48 package compliant with IEC 61967-2	0.1 MHz to 30 MHz 30 MHz to 130 MHz	3 5	3 -2
SEMI	Peak level		130 MHz to 1 GHz 1 GHz to 2 GHz	1 7	-1 8	dBμV
		EMI level	2	2	-

5.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol	Ratings	Conditions	Package	Class	Maximum value(1)	Unit
VESD(HBM)	Electrostatic discharge voltage (human body model)	TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001	All	1C	-2000/+1500
VESD(CDM)	Electrostatic discharge voltage (charge device model)	TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002	All	C2a	500	V

Table 46. ESD absolute maximum ratings

^1. Evaluated by characterization – Not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin.
A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 47. Electrical sensitivity

Symbol	Parameter	Conditions	Class
LU	Static latch-up class	T _A = +125 °C conforming to JESD78	II Level A

5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage belowV_{\rm SS}$ or above $V_{\rm DDIO1}$ (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 $\mu$ A/+0 $\mu$ A range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Table 48. I/O current injection susceptibility⁽¹⁾

	Symbol Description		Functional s
Symbol			Negative injection
I _INJ ⁽²⁾	Injected current on pin	Any IO	5

1. Evaluated by characterization Not tested in production.
1. The injection current value is applicable when the switchable diode is activated, NA when not activated.

5.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.

Table 49. I/O static characteristics

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
V _IL ⁽¹⁾	I/O input low level voltage	All	2 V < V _DDIO1 < 3.6 V	-	-	0.3 x V _DDIO1	V
V _IH ⁽¹⁾	I/O input high level voltage	All	2 V < V _DDIO1 < 3.6 V	0.7 x V _DDIO1	-	-	V
V _hys ⁽²⁾	I/O input hysteresis	-		-	200	-	mV
	(3) Input leakage current ⁽³⁾		N ≤ V _DDIO1	-	-70	-
I _lkg ⁽³⁾			$1 \le V{IN} \le V_{DDIO1} + 1 V$	-	600	-	nA
		$V_{DDIO}	₁ +1 V ≤ V _IN	-	150	-
R _PU	Weak pull-up equivalent resistor	V _IN = V _SS		25	40	55	kΩ
R _PD	Weak pull-down equivalent resistor ⁽⁴⁾	V _IN = V _DDIO1		25	40	55	kΩ
C _IO	I/O pin capacitance		-	-	5	-	pF

^1. Refer to Figure 17: I/O input characteristics.

^2. Specified by design – Not tested in production.

^3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_lleak_max = 10 μA + [number of I/Os where VIN is applied on the pad] x Ilkg(Max).

^4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 17.

Figure 17. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to\pm 6$ mA, and up to $\pm 15$ mA with relaxed $V_{OL}/V_{OH}$ .

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

The sum of the currents sourced by all the I/Os on V_DDIO1, plus the maximum consumption of the MCU sourced on V_DD, cannot exceed the absolute maximum rating I_VDD (see Table 20: Voltage characteristics).
The sum of the currents sunk by all the I/Os on V_SS, plus the maximum consumption of the MCU sunk on V_SS, cannot exceed the absolute maximum rating I_VSS (see Table 20: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).

	Table 30. Outpo	ut voltage characteristics	3
Symbol	Parameter	Conditions	Min
$V_{OL}$	Output low level voltage	CMOS port ⁽²⁾	-
V _OH	Output high level voltage	$ I_{IO} = 8 \text{ mA}$ 2.7 V $\leq$ V _DD $\leq$ 3.6 V	V _DD - 0.4
V _OL ⁽³⁾	Output low level voltage	TTL port ⁽²⁾	-
V _OH ⁽³⁾	Output high level voltage	$ I_{IO} = 8 \text{ mA}$ 2.7 V $\leq$ V _DD $\leq$ 3.6 V	2.4
V _OL ⁽³⁾	Output low level voltage	All I/Os	-
V _OH ⁽³⁾	Output high level voltage	$ I_{IO} = 20 \text{ mA} 2.7 V ≤ V _DD ≤ 3.6 V	V _DD - 1.3
V _OL ⁽³⁾	Output low level voltage	I _IO = 4 mA	-
V _OH ⁽³⁾	Output high level voltage	2.7 \text{ V} \le \text{V}_{DD} \le 3.6 \text{ V}$	V _DD - 0.45
V _OLEM+ Ou	Output low level voltage for an FT I/O	$ I_{IO} = 20 \text{ mA} 2.7 V ≤ V_DD ≤ 3.6 V	-
	pin in FM+ mode	I _IO = 10 mA 2.7 V ≤ V _DD ≤ 3.6 V	-

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 18 and Table 51, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
•			C=50 pF, 2.7 V ≤ V _DD ≤ 3.6 V	-	2
Fmax	Fmov	Maximum frequency	C=50 pF, 2 V ≤ V _DD ≤ 2.7 V	-	0.35	NALI-
	Fillax		C=10 pF, 2.7 V ≤ V _DD ≤ 3.6 V	-	3.00	MHz
00			C=10 pF, 2 V ≤ V _DD ≤ 2.7 V	-	0.45
00		Output rise and fall time ⁽³⁾	C=50 pF,2.7 V ≤ V _DD ≤ 3.6 V	-	100.00
Tr/Tf	Tr/Tf		C=50 pF, 2 V ≤ V _DD ≤ 2.7 V	-	225.00
	Output rise and fail time.	C=10 pF, 2.7 V ≤ V _DD ≤ 3.6 V C=10 pF, 2 V\leq$ V _DD $\leq2.7 V	- -	75.00 150.00	ns

The I_IO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20: Voltage characteristics , and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ∑I_IO.

^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^3. Specified by design – Not tested in production.

Table 51. I/O AC characteristics(1)(2) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	10.00
	Fmax	Maximum frequency	C=50 pF, 2 V ≤ VDD ≤ 2.7 V C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V	- -	2.00 15.00	MHz
01			C=10 pF, 2 V ≤ VDD ≤ 2.7 V C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V	- -	2.50 30.00
		Output rise and fall time(3)	C=50 pF, 2 V ≤ VDD ≤ 2.7 V	-	60.00
	Tr/Tf		C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V C=10 pF, 2 V ≤ VDD ≤ 2.7 V C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V	- - -	15.00 30.00 30.00	ns
		Maximum frequency	C=50 pF, 2 V ≤ VDD ≤ 2.7 V	-	15.00
	Fmax		C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V C=10 pF, 2 V ≤ VDD ≤ 2.7 V	- -	60.00(4) 30.00	MHz
10			C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	11.00	ns
		Output rise and fall time(3)	C=50 pF, 2 V ≤ VDD ≤ 2.7 V	-	22.00
	Tr/Tf		C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V C=10 pF, 2 V ≤ VDD ≤ 2.7 V C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V C=30 pF, 2 V ≤ VDD ≤ 2.7 V	- - - -	4.00 8.00 60.00(4) 30.00
	Fmax	Maximum frequency	C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V C=10 pF, 2 V ≤ VDD ≤ 2.7 V	- -	80.00(4) 40.00	MHz
11			C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	5.50
		Output rise and fall time(3)	C=30 pF, 2 V ≤ VDD ≤ 2.7 V	-	11.00	ns
	Tr/Tf		C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V C=10 pF, 2 V ≤ VDD ≤ 2.7 V	- -	2.50 5.00

^2. Specified by design – Not tested in production.

^3. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.

^4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.

Figure 18. I/O AC characteristics definition⁽¹⁾

Refer to Table 51: I/O AC characteristics.

5.3.14 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor,R_{\mbox{\scriptsize PU}}.Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V _IL(NRST)	NRST input low level voltage	-	-	-	0.3 x V _DD	V
V _IH(NRST)	NRST input high level voltage	-	0.7 x V _DD	-	-	V
V _hys(NRST)	NRST Schmitt trigger voltage hysteresis	-	-	200	-	mV
R _PU ⁽¹⁾	Weak pull-up equivalent resistor ⁽²⁾	V _IN = V _SS	25	40	55	kΩ
V _F(NRST) (1)	NRST input filtered pulse	2.0 V < V _DD < 3.6 V	-	-	70	ns
V _NF(NRST) ⁽¹⁾	NRST input not filtered pulse	2.0 V < V _DD < 3.6 V	350	-	-	ns

Table 52. NRST pin characteristics

^1. Specified by design – Not tested in production..

^2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

Figure 19. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.
1. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 52: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
1. The external capacitor on NRST must be placed as close as possible to the device.

5.3.15 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 53 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Table 53. ADC characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VDDA	Analog supply voltage	-	2.0	-	3.6	V
VREF+	Positive reference voltage	-	2	-	VDD	V
fADC	ADC clock frequency	-	0.14	-	35	MHz
	Sampling rate	12 bits	-	-	2.50
		10 bits	-	-	2.92	MSps
fs		8 bits	-	-	3.50
		6 bits	-	-	4.38
	External trigger	fADC = 35 MHz; 12 bits	-	-	2.33
fTRIG	frequency	12 bits	-	-	fADC/15	MHz
VAIN	Conversion voltage range	-	0	-	VREF+(2)	V
RAIN	External input impedance	-	-	-	50	kΩ
CADC	Internal sample and hold capacitor	-	-	5	-	pF

Table 53. ADC characteristics(1) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tSTAB	ADC power-up time	LDO already started fADC = 35 MHz		2 2.35		Conversion cycle μs
tCAL	Calibration time	-		82		1/fADC
	Trigger conversion latency for regular and injected	CKMODE = 00 CKMODE = 01	2	- 6.5	3	1/fADC
tLATR	channels without aborting the conversion	CKMODE = 10 CKMODE = 11		12.5 3.5		1/fPCLK
			0.043	-	4.59	μs
ts	Sampling time	fADC = 35 MHz	1.5	-	160.5	1/fADC
tADCVREG_S TUP	ADC voltage regulator start-up time	-	-	-	20	μs
	Total conversion	fADC = 35 MHz Resolution = 12 bits	0.40	-	4.95	μs
tCONV	time (including sampling time)	Resolution = 12 bits		ts + 12.5 cycles for successive approximation = 14 to 173		1/fADC
tIDLE	Laps of time allowed between two conversions without rearm	-	-	-	100	μs
		fs = 2.5 MSps	-	410	-
IDDA(ADC)	ADC consumption from VDDA	fs = 1 MSps	-	164	-	μA
		fs = 10 kSps	-	17	-
		fs = 2.5 MSps	-	65	-
IDDV(ADC)	ADC consumption from VREF+	fs = 1 MSps	-	26	-	μA
		fs = 10 kSps	-	0.26	-

^2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate functions for further details.

Table 54. Maximum ADC RAIN .

Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz Max. RAIN(1)
[ns] (Ω)
1.5 43 50
3.5 100 680
7.5 214 2200
12 bits 12.5 357 4700
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000
1.5 43 68
3.5 100 820
7.5 214 3300
12.5 357 5600
10 bits 19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000
1.5 43 82
3.5 100 1500
7.5 214 3900
12.5 357 6800
8 bits 19.5 557 12000
39.5 1129 27000
79.5 2271 50000
160.5 4586 50000
1.5 43 390
3.5 100 2200
7.5 214 5600
12.5 357 10000
6 bits 19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000

^1. Specified by design – Not tested in production.

Table 55. ADC accuracy(1)(2)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
ET	Total unadjusted	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C	-	±3	±4
	error	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±3	±6.5
EO	Offset error	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C	-	±1.5	±2
		2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±1.5	±4.5
EG	Gain error	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	-	±3	±3.5	LSB
		2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±3	±5
ED	Differential	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	-	±1.2	±1.5
	linearity error	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±1.2	±1.5
EL	Integral linearity error	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	-	±2.5	±3
		2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	±2.5	±3
ENOB	Effective	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	10.1	10.2	-	bit
	number of bits	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	9.6	10.2	-
	Signal-to-noise and distortion	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	62.5	63	-	dB
SINAD	ratio	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	59.5	63	-
	Signal-to-noise	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C	63	64	-	dB
SNR	ratio	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	60	64	-
	VDDA = VREF+ = 3 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C Total harmonic		-	-74	-73
THD	distortion	2 V < VDDA = VREF+ < 3.6 V fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range	-	-74	-70	dB

^1. Evaluated by characterization – Not tested in production.

^2. ADC DC accuracy values are measured after internal calibration.

Figure 20. ADC accuracy characteristics

1. Refer to Table 53: ADC characteristics for the values of RAIN and CADC.
C_parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 49: I/O static characteristics for the value of the pad capacitance). A high C_parasitic value will downgrade conversion accuracy. To remedy this, f_ADC should be reduced.
1. Refer to Table 49: I/O static characteristics for the values of I_Ika.
1. Refer to Figure 2: Power supply overview.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

5.3.16 Temperature sensor characteristics

Table 56. TS characteristics

Symbol	Parameter	Min	Typ	Max	Unit
T _L ⁽¹⁾	V _SENSE linearity with temperature	-	±1	±5	°C
Avg_Slope ⁽²⁾	Average slope from V _SENSE voltage	2.4	2.53	2.65	mV/°C
V ₃₀ ⁽³⁾	Voltage at 30°C (±5 °C)	0.742	0.76	0.786	V
t _{START(TS_BUF)} (1)	Sensor Buffer Start-up time in continuous mode	-	8	15
t _START (1)	Start-up time when entering in continuous mode	-	8	120	μs
t _{S_temp} ⁽¹⁾ ADC sampling time when reading the temperature		5	-	-
i _sens (1)	Temperature sensor consumption from VDD, when selected by ADC	-	4.7	7.0	μΑ

^1. Specified by design – Not tested in production.

5.3.17 Timer characteristics

The parameters given in the following tables are guaranteed by design. Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 57. TIMx⁽¹⁾ (2)characteristics

Symbol	Parameter	Conditions	Min	Max	Unit
t	Timer resolution time	-	1	-	t _TIMxCLK
^t res(TIM)	Timer resolution time	f _TIMxCLK = 48 MHz	20.833	-	ns
f _EXT	Timer external clock frequency on CH1 to CH4	-	0	f _TIMxCLK /4	MHz
Res _TIM	Timer resolution	TIMx	-	16	bit
t _COUNTER	16-bit counter clock period	-	1	65536	t _TIMxCLK
t _{MAX_COUNT}	Maximum possible count with 16-bit counter	-	-	65536	t _TIMxCLK

^1. TIMx is used as a general term to refer to the TIM1 and TIM17 timers.

^2. Evaluated by characterization – Not tested in production.

^3. Measured atV_{DDA}$ = 3.3 V ±10 mV. The $V_{30}ADC conversion result is stored in the TS_CAL1 byte.

^2. Specified by design – Not tested in production.

Prescaler divider	PR[2:0] bits	Min timeout RL[11:0]= 0x000	Max timeout RL[11:0]= 0xFFF	Unit
/4	0	0.125	512
/8	1	0.250	1024
/16	2	0.500	2048
/32	3	1.0	4096	ms
/64	4	2.0	8192
/128	5	4.0	16384
/256	6 or 7	8.0	32768

5.3.18 Characteristics of communication interfaces

I 2 C-bus interface characteristics

The I2C-bus interface meets timing requirements of the I2C-bus specification and user manual rev. 03 for:

Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are guaranteed by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0490) and when the I2CCLK frequency is greater than the minimum shown in the following table.

Symbol Parameter Condition Typ Unit fI2CCLK(min) Minimum I2CCLK frequency for correct operation of I2C peripheral Standard-mode 2 MHz Fast-mode Analog filter enabled 9 DNF = 0 Analog filter disabled 9 DNF = 1 Fast-mode Plus Analog filter enabled 19 DNF = 0 Analog filter disabled 16 DNF = 1

Table 59. Minimum I2CCLK frequency

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins

^1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period.

support Fm+ low-level output current maximum requirement. Refer to Section 5.3.13: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics:

Table 60. I2C analog filter characteristics(1)

Symbol	Parameter	Min	Max	Unit
tAF	Limiting duration of spikes suppressed by the filter(2)	50	260	ns

1. Specified by design Not tested in production.
1. Spikes shorter than the limiting duration are suppressed.

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 61 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. The additional general conditions are:

OSPEEDRy[1:0] set to 11 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x VDD

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 61. SPI characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
		Master mode 2. V < VDD < 3.6 V Master transmitter mode 2. V < VDD < 3.6 V		-	24 24
fSCK 1/tc(SCK)	SPI clock frequency	Slave receiver mode Slave transmitter mode/full duplex(2) 2.7 V < VDD < 3.6 V Slave transmitter mode/full duplex(2) 2 V < VDD < 3.6 V	-		24 24 22	MHz
tsu(NSS)	NSS setup time		4 * TPCLK	-	-	ns
th(NSS)	NSS hold time	Slave mode	2 * TPCLK	-	-	ns
tw(SCKH) tw(SCKL)	SCK high and low time	Master mode	TPCLK - 1	TPCLK	TPCLK + 1	ns
-	SCK low time	Master mode	TPCLK - 2	TPCLK	TPCLK + 2	ns
tsu(MI)		Master mode	4.5	-	-	ns
tsu(SI)	Data input setup time	Slave mode	2	-	-	ns

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
th(MI)		Master mode	2	-	-	ns
th(SI)	Data input hold time	Slave mode	3	-	-	ns
ta(SO)	Data output access time	Slave mode	9	-	34	ns
tdis(SO)	Data output disable time	Slave mode	9	-	16	ns
	Data output valid time	Slave mode 2.7 V < VDD < 3.6 V	-	10	16	ns
tv(SO)		Slave mode 2 V < VDD < 3.6 V	-	10	22
tv(MO)		Master mode	-	3	5.5	ns
th(SO)	Data output hold time	Slave mode 2 V < VDD < 3.6 V	8	-	-	ns
th(MO)		Master mode	1.5	-	-	ns

Table 61. SPI characteristics(1) (continued)

^2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%

Figure 22. SPI timing diagram - slave mode and CPHA = 0

^1. Evaluated by characterization – Not tested in production.

Figure 23. SPI timing diagram - slave mode and CPHA = 1

Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

Figure 24. SPI timing diagram - master mode

Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

Table 62. I2S characteristics(1)

Symbol	Parameter	Conditions	Min	Max	Unit
fMCK	I2S main clock output	-	-	48	MHz
		Master TX	-	12
		Master RX	-	12
fCK	I2S clock frequency	Slave TX	-	15	MHz
		Slave RX	-	48
tv(WS)	WS valid time	Master mode	-	5
th(WS)	WS hold time	Master mode	2	-
tsu(WS)	WS setup time	Slave mode	3.5	-	ns
th(WS)	WS hold time Slave mode		1	-
tsu(SD_MR)		Master receiver	5	-
tsu(SD_SR)	Data input setup time	Slave receiver	2.5 -
th(SD_MR)	Data input hold time	Master receiver	1.5	-
th(SD_SR)		Slave receiver	1	-
tv(SD_ST)		Slave transmitter (after enable edge)	-	19,5
tv(SD_MT)	Data output valid time	Master transmitter (after enable edge)	-	5	ns
th(SD_ST)		Slave transmitter (after enable edge)	8	-
th(SD_MT)	Data output hold time	Master transmitter (after enable edge)	2.5	-

Figure 25. I2S slave timing diagram (Philips protocol)

1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 26. I2S master timing diagram (Philips protocol)

1. Evaluated by characterization Not tested in production.
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

USART characteristics

Unless otherwise specified, the parameters given in Table 63 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. The additional general conditions are:

OSPEEDRy[1:0] set to 10 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x VDD

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART).

Table 63. USART characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
		Master mode	-	-	6.0
f_{CK}$	USART clock frequency	Slave receiver mode	-	-	16.0	MHz
		Slave transmitter	-	-	16.0
t _su(NSS)	NSS setup time	Slave mode	t _ker + 1	-	-
t _h(NSS)	NSS hold time	Slave mode	2	-	-
t _w(CKH)	CK high time	- Master mode	1 / f _CK / 2	1 / f _CK / 2	1 / f _CK / 2
t _w(CKL)	CK low time	- Iviastei mode	- 1	1 / 1 CK / 2	+ 1
t _su(MI)	$t_{su(MI)}$ $t_{su(SI)}$ Data input setup time	Master mode	16	-	-
t _su(SI)		Slave mode	1.5	-	-
t _h(MI)	Data input hold time	Master mode	0	-	-
t _h(SI)	Data input noid time	Slave mode	0	-	-	ns
4		Slave mode 2.7 V < VDD < 3.6 V	-	12.0	19
t _v(SO)	Data output valid time	Slave mode 1.6 V < VDD < 3.6 V	-	12.0	13
t _v(MO)		Master mode	-	2.0	4
t _h(SO)	Data output hold time	Slave mode	9.5	-	-
t _h(SO)	Data output hold time	Master mode	0.5	-	-

Absolute Maximum Ratings

All voltages are defined with respect to VSS.

Table 20. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD - VSS	External supply voltage	-0.3	4.0
(1) VIN	Input voltage on pin	-0.3	VDD + 4.0(2)	V

^1. VIN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values.

Table 21. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)	100
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)	100
	Output current sunk by any I/O and control pin	20
IIO(PIN)	Output current sourced by any I/O and control pin	20
	Total output current sunk by sum of all I/Os and control pins(1)	80	mA
∑I(PIN)	Total output current sourced by sum of all I/Os and control pins(1)	80
IINJ(PIN)(1)(2)	Injected current on a FT_xx pin	-5 / 0
∑IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(3)	-25

^2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.
When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 22. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	130	°C

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

6.1 SO8N package information

SO8N is an 8-lead 4.9 x 6 mm plastic small-outline package with 150 mils body width.

Figure 27. SO8N – Outline

Drawing is not to scale.

Table 64. SO8N – Mechanical data

		millimeters		inches(1)
Symbol	Min.	Typ.	Max.	Min.
A	-	-	1.750	-
A1	0.100	-	0.250	0.0039
A2	1.250	-	-	0.0492
b	0.280	-	0.480	0.0110
c	0.170	-	0.230	0.0067
D(2)	4.800	4.900	5.000	0.1890
E	5.800	6.000	6.200	0.2283
E1(3)	3.800	3.900	4.000	0.1496
e	-	1.270	-	-
h	0.250	-	0.500	0.0098
k	0°	-	8°	0°
L	0.400	-	1.270	0.0157

Symbol					inches(1)
	Min.	Typ.	Max.	Min.	Typ.
L1	-	1.040	-	-	0.0409
ccc	-	-	0.100	-	-

Table 64. SO8N – Mechanical data (continued)

1. Values in inches are converted from mm and rounded to four decimal digits.
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side
1. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Figure 28. SO8N – Footprint example

Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Package information STM32C011x4/x6

Figure 29. SO8N package marking example

Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

6.2 WLCSP12 package information

This WLCSP is a 12-ball, 1.70 x 1.42 mm, 0.35 mm pitch, wafer level chip scale package

e2 G F e1 A4 B0EK_WLCSP12_ME_V1 A2 B3 B1 C4 C2 D3 D1 E4 E2 F3 F1 (DETAIL B) DETAIL B e e (DETAIL A) bbb Z A BACKSIDE COATING SIDE VIEW BOTTOM VIEW SIDE VIEW A3 A2 D E A eee aaa TOP VIEW B1 Orientation ref Z 4x BUMP b (Nx) ddd Z X Y ccc A1 Z SEATING PLANE DETAIL A ROATATED 90

Figure 30. WLCSP12 – Outline

1. Drawing is not to scale.
1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
1. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
1. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.

Package information STM32C011x4/x6

Table 65. WLCSP12 – Mechanical data

		millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ
A(2)	-	-	0.49	-	-
A1	-	0.17	-	-	0.0067
A2	-	0.29	-	-	0.0114
A3(3)	-	0.025	-	-	0.0098
Ø b(4)	0.21	0.24	0.27	0.0083	0.0094
D	1.68	1.70	1.72	0.0661	0.0669
E	1.41	1.42	1.43	0.0555	0.0559
e	-	0.35	-	-	0.0138
e1	-	0.909	-	-	0.0358
e2	-	0.875	-	-	0.0344
F(5)	-	0.409	-	-	0.0161
G(5)	-	0.282	-	-	0.0111
N				12
aaa	-	-	0.10	-	-
bbb	-	-	0.10	-	-
ccc(6)	-	-	0.10	-	-
ddd(7)	-	-	0.05	-	-
eee	-	-	0.05	-	-

1. Values in inches are converted from mm and rounded to 4 decimal digits.
1. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2.
1. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
1. Calculated dimensions are rounded to the 3rd decimal place
1. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
1. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone. Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of each ball must lie simultaneously in both tolerance zones

BGA_WLCSP_FT_V1 Dsm Dpad

Figure 31. WLCSP12 – Footprint example

Table 66. WLCSP12 – Example of PCB design rules

Dimension	Recommended values
Pitch	0.35 mm
Dpad	0.200 mm
Dsm	0.275 mm
Stencil thickness	0.08 mm

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Date code Pin 1 identifier 3C0 Product identification(1) Y WW

Figure 32. WLCSP12 package marking example

MS55865V1

Package information STM32C011x4/x6

Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

6.3 TSSOP20 package information

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch.

Figure 33. TSSOP20 - Outline

Drawing is not to scale.

Table 67. TSSOP20 - Mechanical data

Cumbal		millimeters		inches ⁽¹⁾
Symbol	Min.	Typ.	Max.	Min.
Α	-	-	1.200	-
A1	0.050	-	0.150	0.0020
A2	0.800	1.000	1.050	0.0315
b	0.190	-	0.300	0.0075
C	0.090	-	0.200	0.0035
D ⁽²⁾	6.400	6.500	6.600	0.2520
E	6.200	6.400	6.600	0.2441
E1 ⁽³⁾	4.300	4.400	4.500	0.1693
e	-	0.650	-	-
L	0.450	0.600	0.750	0.0177
L1	-	1.000	-	-

Symbol	millimeters			inches(1)
	Min.	Typ.	Max.	Min.
k	0°	-	8°	0°
aaa	-	-	0.100	-

Table 67. TSSOP20 – Mechanical data (continued)

1. Values in inches are converted from mm and rounded to four decimal digits.
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
1. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Figure 34. TSSOP20 – Footprint example

Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

Package information STM32C011x4/x6

Figure 35. TSSOP20 package marking example

Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

6.4 UFQFPN20 package information

UFQFPN20 is a 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Figure 36. UFQFPN20 – Outline

Drawing is not to scale.

Table 68. UFQFPN20 – Mechanical data

Symbol	millimeters			inches(1)
	Min	Typ	Max	Min
A	0.500	0.550	0.600	0.0197
A1	0.000	0.020	0.050	0.0000
A3	-	0.152	-	-
D	2.900	3.000	3.100	0.1142
D1	-	2.000	-	-
E	2.900	3.000	3.100	0.1142
E1	-	2.000	-	-
L1	0.500	0.550	0.600	0.0197
L2	0.300	0.350	0.400	0.0118
L3	-	0.200	-	-
L5	-	0.150	-	-
b	0.180	0.250	0.300	0.0071
e	-	0.500	-	-
ddd	-	-	0.050	-

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

A0A5_FP_V2

Figure 37. UFQFPN20 – Footprint example

Dimensions are expressed in millimeters.

Package information STM32C011x4/x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below.

MS55849V1 Date code Pin 1 identifier C166 Product identification(1) Y WW A

Figure 38. UFQFPN20 package marking example

Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
STM32C011D6	STMicroelectronics	—
STM32C011F4	STMicroelectronics	—
STM32C011F4P6	STMicroelectronics	—
STM32C011F6	STMicroelectronics	—
STM32C011J4	STMicroelectronics	—
STM32C011J6	STMicroelectronics	—

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