RP2350A
The RP2350A is an electronic component from Raspberry Pi. View the full RP2350A datasheet below including pinout.
Manufacturer
Raspberry Pi
Overview
Part: RP2350 — Raspberry Pi
Type: Microcontroller
Description: High-performance, secure microcontroller featuring dual Arm Cortex-M33 or dual Hazard3 RISC-V processors at 150MHz, 520 KB on-chip SRAM, and comprehensive security architecture built around Arm TrustZone for Cortex-M.
Operating Conditions:
- Supply voltage (VREG_VIN): 2.7 V to 5.5 V
- GPIO supply voltage (IOVDD): 1.8 V to 3.3 V
- Max CPU clock: 150 MHz
Key Specs:
- CPU Cores: Dual Arm Cortex-M33 or dual Hazard3 RISC-V
- On-chip SRAM: 520 KB
- External Flash/PSRAM Support: Up to 16 MB via QSPI bus (additional 16 MB via optional second chip-select)
- Programmable I/O (PIO) State Machines: 12 (across 3 co-processors)
- USB: 1.1 controller and PHY, with host and device support
- GPIO Pins: 30 or 48
- ADC Channels: 4 or 8
Features:
- Arm TrustZone for Cortex-M
- Signed boot, enforced by on-chip mask ROM
- 8KB antifuse OTP for key storage
- SHA-256 acceleration
- Hardware TRNG
- Fast glitch detectors
- Global bus filtering based on security/privilege levels
- Peripherals, GPIOs, and DMA channels individually assignable to security domains
- Hardware mitigations for fault injection attacks
Applications:
- Cost-optimised embedded computing
- Secure applications requiring trusted firmware
- Industrial IoT deployments with demanding I/O requirements
Package:
- QFN-60 (30 GPIO, 4 ADC)
- QFN-80 (48 GPIO, 8 ADC)
Features
CPU:
Dual Arm Cortex-M33 or dual Hazard3 RISC-V processors @ 150MHz
Memory:
-
520 KB on-chip SRAM, in ten independent banks
-
Support for up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus; additional 16 MB flash/PSRAM accessible via optional second chip-select
Peripherals:
-
2 × UART
-
2 × SPI controllers
-
2 × I2C controllers
-
24 × PWM channels
-
4/8 × ADC channels
-
1 × USB 1.1 controller and PHY, with host and device support
-
12 × PIO state machines
Security features:
-
Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP
-
Protected OTP storage for optional boot decryption key
-
Global bus filtering based on Arm or RISC-V security/privilege levels
-
Peripherals, GPIOs, and DMA channels individually assignable to security domains
-
Hardware mitigations for fault injection attacks
-
Hardware SHA-256 accelerator
| Product | Package | Internal flash | GPIO | Analogue inputs |
|---|---|---|---|---|
| RP 2350A | QFN-60 | None | 30 | 4 |
| RP 2350B | QFN-80 | None | 48 | 8 |
| RP 2354A | QFN-60 | 2 MB | 30 | 4 |
| RP 2354B | QFN-80 | 2 MB | 48 | 8 |
Production lifetime:
Raspberry Pi understands the value to customers of long-term product availability and therefore aims to continue supply for as long as practically possible. We expect RP2350 to remain in production until at least January 2045.
Compliance:
For a full list of local and regional product approvals, please visit pip.raspberrypi.com
Pin Configuration
RP2350A – 60QFN Pinout
| Pin Number | Pin Name | Type | Description |
|---|---|---|---|
| 1 | IOVDD | P | I/O Supply Voltage |
| 2 | GPIO0 | I/O | General Purpose I/O 0 |
| 3 | GPIO1 | I/O | General Purpose I/O 1 |
| 4 | GPIO2 | I/O | General Purpose I/O 2 |
| 5 | GPIO3 | I/O | General Purpose I/O 3 |
| 6 | DVDD | P | Digital Core Supply Voltage |
| 7 | GPIO4 | I/O | General Purpose I/O 4 |
| 8 | GPIO5 | I/O | General Purpose I/O 5 |
| 9 | GPIO6 | I/O | General Purpose I/O 6 |
| 10 | GPIO7 | I/O | General Purpose I/O 7 |
| 11 | IOVDD | P | I/O Supply Voltage |
| 12 | GPIO8 | I/O | General Purpose I/O 8 |
| 13 | GPIO9 | I/O | General Purpose I/O 9 |
| 14 | GPIO10 | I/O | General Purpose I/O 10 |
| 15 | GPIO11 | I/O | General Purpose I/O 11 |
| 16 | GPIO12 | I/O | General Purpose I/O 12 |
| 17 | GPIO13 | I/O | General Purpose I/O 13 |
| 18 | GPIO14 | I/O | General Purpose I/O 14 |
| 19 | GPIO15 | I/O | General Purpose I/O 15 |
| 20 | IOVDD | P | I/O Supply Voltage |
| 21 | GND | S | Ground |
| 22 | XOUT | O | Crystal Oscillator Output |
| 23 | SWDIO | I/O | Serial Wire Debug Data I/O |
| 24 | SWCLK | I/O | Serial Wire Debug Clock |
| 25 | GND | S | Ground |
| 26 | GPIO16 | I/O | General Purpose I/O 16 |
| 27 | GPIO17 | I/O | General Purpose I/O 17 |
| 28 | GPIO18 | I/O | General Purpose I/O 18 |
| 29 | GPIO19 | I/O | General Purpose I/O 19 |
| 30 | IOVDD | P | I/O Supply Voltage |
| 31 | GPIO20 | I/O | General Purpose I/O 20 |
| 32 | GPIO21 | I/O | General Purpose I/O 21 |
| 33 | GPIO22 | I/O | General Purpose I/O 22 |
| 34 | GPIO23 | I/O | General Purpose I/O 23 |
| 35 | GPIO24 | I/O | General Purpose I/O 24 |
| 36 | GPIO25 | I/O | General Purpose I/O 25 |
| 37 | IOVDD | P | I/O Supply Voltage |
| 38 | DVDD | P | Digital Core Supply Voltage |
| 39 | GPIO26 | I/O | General Purpose I/O 26 |
| 40 | GPIO27 | I/O | General Purpose I/O 27 |
| 41 | GPIO28 | I/O | General Purpose I/O 28 |
| 42 | GPIO29 | I/O | General Purpose I/O 29 |
| 43 | ADC_AVDD | P | ADC Analog Supply Voltage |
| 44 | GPIO29_ADC3 | I/O | General Purpose I/O 29 / ADC Channel 3 |
| 45 | IOVDD | P | I/O Supply Voltage |
| 46 | IOVDD | P | I/O Supply Voltage |
| 47 | GPIO28_ADC2 | I/O | General Purpose I/O 28 / ADC Channel 2 |
| 48 | GPIO27_ADC1 | I/O | General Purpose I/O 27 / ADC Channel 1 |
| 49 | GPIO26_ADC0 | I/O | General Purpose I/O 26 / ADC Channel 0 |
| 50 | IOVDD | P | I/O Supply Voltage |
| 51 | DVDD | P | Digital Core Supply Voltage |
| 52 | SWCLK | I/O | Serial Wire Debug Clock |
| 53 | SWDIO | I/O | Serial Wire Debug Data I/O |
| 54 | XOUT | O | Crystal Oscillator Output |
| 55 | IOVDD | P | I/O Supply Voltage |
| 56 | GND | S | Ground |
| 57 | GPIO15 | I/O | General Purpose I/O 15 |
| 58 | GPIO14 | I/O | General Purpose I/O 14 |
| 59 | GPIO13 | I/O | General Purpose I/O 13 |
| 60 | GPIO12 | I/O | General Purpose I/O 12 |
Notes
- Package: 60-pin QFN (Quad Flat No-Lead)
- Power pins: IOVDD (I/O supply), DVDD (digital core supply), ADC_AVDD (ADC analog supply), and GND (ground) are distributed around the package
- ADC pins: GPIO26–GPIO29 have dual function as ADC channels (ADC0–ADC3)
- Debug pins: SWDIO and SWCLK appear at multiple locations (pins 23–24 and 52–53) for routing flexibility
- Crystal pins: XOUT appears at pins 22 and 54 for oscillator connection
- Pin numbering follows standard QFN convention: starting at pin 1 (top-left), proceeding counterclockwise around the perimeter
Related Variants
The following components are covered by the same datasheet.
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