Part: Raspberry Pi RP2350

Type: High-performance, Secure Microcontroller

Key Specs:

• CPU Clock Speed: 150 MHz
• On-chip SRAM: 520 KB
• On-chip OTP: 8 KB
• External QSPI Flash/PSRAM Support: Up to 16 MB (additional 16 MB via second chip-select)
• GPIO Pins: 30 or 48

Features:

• Dual Arm Cortex-M33 or dual Hazard3 RISC-V processors
• Arm TrustZone for Cortex-M
• Signed boot
• SHA-256 acceleration
• Hardware TRNG
• Fast glitch detectors
• Three Programmable I/O (PIO) co-processors with 12 independent state machines
• 2x UART
• 2x SPI controllers
• 2x I2C controllers
• 24x PWM channels
• 4/8x ADC channels
• 1x USB 1.1 controller and PHY, with host and device support
• Optional boot signing, enforced by on-chip mask ROM
• Protected OTP storage for optional boot decryption key
• Global bus filtering based on Arm or RISC-V security/privilege levels
• Peripherals, GPIOs, and DMA channels individually assignable to security domains
• Hardware mitigations for fault injection attacks

Applications:

• Cost-optimised embedded computing
• Secure applications requiring trusted firmware
• Industrial IoT deployments with demanding I/O requirements

Package:

• QFN-60
• QFN-80

CPU:	Dual Arm Cortex-M33 or dual Hazard3 RISC-V processors @ 150MHz
Memory:	• 520 KB on-chip SRAM, in ten independent banks • Support for up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus; additional 16 MB flash/PSRAM accessible via optional second chip-select
Peripherals:	• 2 × UART • 2 × SPI controllers • 2 × I2C controllers • 24 × PWM channels • 4/8 × ADC channels • 1 × USB 1.1 controller and PHY, with host and device support • 12 × PIO state machines
Security features:	• Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP • Protected OTP storage for optional boot decryption key • Global bus filtering based on Arm or RISC-V security/privilege levels • Peripherals, GPIOs, and DMA channels individually assignable to security domains • Hardware mitigations for fault injection attacks • Hardware SHA-256 accelerator
Package:
Product	Package
---------	---------
RP2350A	QFN-60
RP2350B	QFN-80
RP2354A	QFN-60
RP2354B	QFN-80

• Production lifetime: Raspberry Pi understands the value to customers of long-term product availability and therefore aims to continue supply for as long as practically possible. We expect RP2350 to remain in production until at least January 2045.
• Compliance: For a full list of local and regional product approvals, please visit pip.raspberrypi.com

RP2350 QFN-60 Pinout

Pin	Name	Type	Description
1	IOVDD	P	Power supply for digital GPIOs (1.8V–3.3V)
2	GPIO0	I/O	General-purpose digital input/output
3	GPIO1	I/O	General-purpose digital input/output
4	GPIO2	I/O	General-purpose digital input/output
5	GPIO3	I/O	General-purpose digital input/output
6	DVDD	P	Digital core power supply (1.1V)
7	GPIO4	I/O	General-purpose digital input/output
8	GPIO5	I/O	General-purpose digital input/output
9	GPIO6	I/O	General-purpose digital input/output
10	GPIO7	I/O	General-purpose digital input/output
11	IOVDD	P	Power supply for digital GPIOs (1.8V–3.3V)
12	GPIO8	I/O	General-purpose digital input/output
13	GPIO9	I/O	General-purpose digital input/output
14	GPIO10	I/O	General-purpose digital input/output
15	GPIO11	I/O	General-purpose digital input/output
16	GPIO12	I/O	General-purpose digital input/output
17	GPIO13	I/O	General-purpose digital input/output
18	GPIO14	I/O	General-purpose digital input/output
19	GPIO15	I/O	General-purpose digital input/output
20	IOVDD	P	Power supply for digital GPIOs (1.8V–3.3V)
21	XIN	I	Crystal oscillator input
22	XOUT	O	Crystal oscillator output
23	SWCLK	I	Serial Wire Clock (debug interface)
24	DVDD	P	Digital core power supply (1.1V)
25	SWDIO	I/O	Serial Wire Data I/O (debug interface)
26	RUN	I	Global asynchronous reset (active low)
27	GPIO16	I/O	General-purpose digital input/output
28	GPIO17	I/O	General-purpose digital input/output
29	GPIO18	I/O	General-purpose digital input/output
30	IOVDD	P	Power supply for digital GPIOs (1.8V–3.3V)
37	GND	S	Ground
38	GND	S	Ground
39	DVDD	P	Digital core power supply (1.1V)
40	GPIO26_ADC0	I/O	General-purpose digital input/output with ADC channel 0
46	VREG_FB	S	Internal core voltage regulator feedback
47	VREG_LX	S	Internal core voltage regulator inductor connection
48	VREG_VIN	P	Core voltage regulator input (2.7V–5.5V)
49	QSPI_SD3	I/O	QSPI data line 3
50	QSPI_SCLK	I/O	QSPI serial clock
51	QSPI_SD0	I/O	QSPI data line 0
52	QSPI_SD2	I/O	QSPI data line 2
53	QSPI_SS	I/O	QSPI chip select
54	QSPI_SD1	I/O	QSPI data line 1
55	QSPI_IOVDD	P	QSPI interface IO supply
56	GND	S	Ground
57	USB_DM	I/O	USB data minus line
58	USB_DP	I/O	USB data plus line
59	VREG_FB	S	Internal core voltage regulator feedback
60	USB_OTP_VDD	P	USB PHY and OTP power supply (3.3V)

Notes:

• ADC_AVDD pin not explicitly listed in source pinout diagram; ADC functionality available on GPIO26_ADC0 (pin 40)
• VREG_PGND and VREG_AVDD referenced in header but specific pin assignments not provided in the pinout table
• Multiple IOVDD and DVDD pins distributed around the package for power distribution
• Multiple GND pins for ground distribution