PIC18F57Q43

Part: PIC18F47Q43 — Microchip Type: Low-Power, High-Performance Microcontroller with XLP Technology

Description: A 28/40/44/48-pin microcontroller family featuring a 12-bit ADCC with computation, 16-bit dual PWM, six DMA controllers, and operating at up to 64 MHz with 128 KB Flash, 8 KB SRAM, and 1024 Bytes EEPROM.

Operating Conditions:

• Supply voltage: 1.8V to 5.5V
• Operating temperature: -40°C to 85°C (Industrial)
• Max CPU frequency: 64 MHz

Key Specs:

• Program Flash Memory: Up to 128 KB
• Data SRAM Memory: Up to 8 KB
• Data EEPROM: 1024 Bytes
• Max CPU Frequency: 64 MHz
• ADCC Resolution: 12-bit
• ADCC Max Sample Rate: 140 KSPS
• Sleep Current: < 800 nA (typical @ 1.8V)
• Operating Current: 48 μA (typical @ 32 kHz, 3V)

Features:

• C Compiler Optimized RISC Architecture
• Six Direct Memory Access (DMA) Controllers
• Vectored Interrupt Capability with fixed latency
• Windowed Watchdog Timer (WWDT)
• Memory Access Partition (MAP) and Device Information Area (DIA)
• Three 16-Bit Pulse-Width Modulators (PWM) with dual outputs
• Eight Configurable Logic Cell (CLC)
• Three Complimentary Waveform Generators (CWG)
• Five UART modules (one with LIN, DMX, DALI protocol support)
• Two SPI modules
• One I2C module, SMBus, PMBus™ Compatible
• Analog-to-Digital Converter with Computation (ADCC) with hardware Capacitive Voltage Divider (CVD) support
• 8-Bit Digital-to-Analog Converter (DAC)
• Two Comparators (CMP)
• Zero-Cross Detect (ZCD)
• High-Precision Internal Oscillator Block (HFINTOSC) up to 64 MHz
• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD)

Package:

• 28-pin
• 40-pin
• 44-pin
• 48-pin

• C Compiler Optimized RISC Architecture
• Operating Speed:
• -DC - 64 MHz clock input
• -62.5 ns minimum instruction cycle
• Six Direct Memory Access (DMA) Controllers:
• -Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
• -User programmable source and destination sizes
• -Hardware and software triggered data transfers
• Vectored Interrupt Capability:
• -Selectable high/low priority
• -Fixed interrupt latency of three instruction cycles
• -Programmable vector table base address
• -Backwards compatible with previous interrupt capabilities
• 127-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
• -Watchdog Reset on too long or too short interval between watchdog clear events
• -Variable prescaler selection
• -Variable window size selection

In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a HighVoltage Detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin).

For general battery applications, the figure below shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an Interrupt Service Routine (ISR), which would allow the application to perform 'housekeeping tasks' and a controlled shutdown before the device voltage exits the valid operating range at TB. This would give the application a time window, represented by the difference between TA and TB, to safely exit.

Figure 37-4. Typical Low-Voltage Detect Application

Legend:

VA = HLVD trip point VB = Minimum valid device operating voltage

In order for each PORT pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register must be set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register must be set. A PORT pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively.

1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Thermal Characteristics section to calculate device specifications.
2. Power dissipation is calculated as follows:

† NOTICE: Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.

Microchip Technology Drawing C04-2073 Rev B

© 2017 Microchip Technology Inc.