PIC18(L)F26K83

Part: Microchip PIC18(L)FXXK83 Type: Low-Power, High-Performance Microcontroller with CAN Technology Description: A full-featured microcontroller family with operating speeds up to 64 MHz, up to 64 KB Flash, 4 KB SRAM, and 1 KB EEPROM, featuring extensive communication peripherals including CAN 2.0B, SPI, two I2Cs, two UARTs, and a 12-bit ADC with computation.

Operating Conditions:

• Supply voltage: 1.8V to 5.5V (1.8V to 3.6V for PIC18LF25/26K83; 2.3V to 5.5V for PIC18F25/26K83)
• Operating temperature: -40°C to 125°C (Industrial: -40°C to 85°C; Extended: -40°C to 125°C)
• Max clock operation: 64 MHz

Absolute Maximum Ratings:

Key Specs:

• Operating Speed: Up to 64 MHz clock operation
• Flash Program Memory: Up to 64 KB
• Data SRAM Memory: Up to 4 KB
• Data EEPROM: Up to 1 KB
• ADC: 12-bit with up to 24 external channels
• CAN Module: Conforms to CAN 2.0B Active Specification, up to 1 Mbps
• Sleep Mode Current: 60 nA @ 1.8V, typical
• I/O Pins: 25 (for PIC18(L)F25/26K83)

Features:

• C Compiler Optimized RISC Architecture
• Two Direct Memory Access (DMA) Controllers
• Vectored Interrupt Capability
• Memory Access Partition (MAP) with configurable boot and app regions
• Peripheral Module Disable (PMD) for power saving
• Configurable Logic Cell (CLC)
• Hardware Capacitive Voltage Divider (CVD) for touch sensing
• Peripheral Pin Select (PPS) for flexible I/O mapping

Applications:

• Automotive
• Industrial applications
• Motor control
• Power supply
• Sensor, signal and user interface applications

Package:

• SPDIP
• SOIC
• SSOP
• UQFN (4x4x0.5mm, 28-pin)
• QFN (6x6x0.9mm, 28-pin)

• C Compiler Optimized RISC Architecture
• Operating Speed:
  • Up to 64 MHz clock operation
  • 62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
  • Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
  • User-programmable source and destination sizes
  • Hardware and software-triggered data transfers
• System Bus Arbiter with User-Configurable Priorities for Scanner and DMA1/DMA2 with respect to the main line and interrupt execution
• Vectored Interrupt Capability:
  • Selectable high/low priority
  • Fixed interrupt latency
  • Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
  • Variable prescaler selection
  • Variable window size selection
  • Configurable in hardware or software

For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively.