PIC18F26K83

Part: PIC18(L)FXXK83 — Microchip Type: Low-Power, High-Performance Microcontroller with CAN Technology Description: A full-featured 28-pin microcontroller family with up to 64 KB Flash, 4 KB SRAM, and 1 KB EEPROM, operating at up to 64 MHz, featuring extensive communication peripherals including CAN, SPI, two I2Cs, two UARTs, and a 12-bit ADC with computation.

Operating Conditions:

• Supply voltage: 1.8V to 3.6V (PIC18LF25/26K83), 2.3V to 5.5V (PIC18F25/26K83)
• Operating temperature: -40°C to 125°C
• Operating speed: Up to 64 MHz clock operation

Absolute Maximum Ratings:

Key Specs:

• Program Flash Memory: Up to 64 KB
• Data SRAM Memory: Up to 4 KB
• Data EEPROM: Up to 1 KB
• ADC: 12-bit with up to 24 external channels
• CPU Speed: 62.5 ns minimum instruction cycle
• Sleep mode current: 60 nA @ 1.8V, typical
• Operating Current: 4 μA @ 32 kHz, 1.8V, typical
• CAN: Conforms to CAN 2.0B Active Specification, up to 1 Mbps

Features:

• C Compiler Optimized RISC Architecture
• Two Direct Memory Access (DMA) Controllers
• Vectored Interrupt Capability
• Memory Access Partition (MAP) with configurable boot and app regions
• Peripheral Module Disable (PMD) for power saving
• Hardware Capacitive Voltage Divider (CVD) for touch sensing
• High-Precision Internal Oscillator: Selectable frequency range up to 64 MHz, ±1% at calibration
• Peripheral Pin Select (PPS) for flexible I/O mapping

Applications:

• Automotive
• Industrial
• Motor control
• Power supply
• Sensor, signal and user interface applications

Package:

• SPDIP (28-pin)
• SOIC (28-pin)
• SSOP (28-pin)
• UQFN (28-pin)
• QFN (28-pin)

• C Compiler Optimized RISC Architecture
• Operating Speed:
• -Up to 64 MHz clock operation
• -62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
• -Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
• -User-programmable source and destination sizes
• -Hardware and software-triggered data transfers
• System Bus Arbiter with User-Configurable Priorities for Scanner and DMA1/DMA2 with respect to the main line and interrupt execution
• Vectored Interrupt Capability:
• -Selectable high/low priority
• -Fixed interrupt latency
• -Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
• -Variable prescaler selection
• -Variable window size selection
• -Configurable in hardware or software

For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively.