PIC18F26K83

Part: PIC18(L)F25/26K83

Type: Low-Power, High-Performance Microcontroller with CAN Technology

Key Specs:

• Operating Speed: Up to 64 MHz clock operation
• Minimum Instruction Cycle: 62.5 ns
• Flash Program Memory: Up to 64 KB
• Data SRAM Memory: Up to 4 KB
• Data EEPROM: Up to 1 KB
• Operating Voltage (PIC18LF25/26K83): 1.8V to 3.6V
• Operating Voltage (PIC18F25/26K83): 2.3V to 5.5V
• Industrial Temperature Range: -40°C to 85°C
• Extended Temperature Range: -40°C to 125°C
• Sleep Mode Current: 60 nA @ 1.8V, typical
• I/O Pins (PIC18(L)F25K83): 25
• ADC: 12-bit with up to 24 external channels
• DAC: 5-bit

Features:

• C Compiler Optimized RISC Architecture
• Two Direct Memory Access (DMA) Controllers
• Vectored Interrupt Capability
• Windowed Watchdog Timer (WWDT)
• Memory Access Partition (MAP)
• Programmable Code Protection
• DOZE, IDLE, SLEEP power modes
• Peripheral Module Disable (PMD)
• Three Complementary Waveform Generators (CWGs)
• CAN module (CAN 2.0B Active Specification)
• Two UART Modules (LIN, DMX, DALI support)
• One SPI module
• Two I2C modules (SMBus, PMBus™ compatible)
• Peripheral Pin Select (PPS)
• Hardware Capacitive Voltage Divider (CVD)
• Temperature Sensor
• Fixed Voltage Reference

Applications:

• Automotive
• Industrial
• Motor control
• Power supply
• Sensor
• Signal
• User interface

Package:

• 28-Pin: dimensions null

• C Compiler Optimized RISC Architecture
• Operating Speed:
• Up to 64 MHz clock operation
• 62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
  • Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
  • User-programmable source and destination sizes
• Hardware and software-triggered data transfers
• System Bus Arbiter with User-Configurable Priorities for Scanner and DMA1/DMA2 with respect to the main line and interrupt execution
• Vectored Interrupt Capability:
• Selectable high/low priority
• Fixed interrupt latency
• Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
  • Variable prescaler selection
  • Variable window size selection
  • Configurable in hardware or software

For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively.