PIC18F26K83

Part: PIC18F26K83 — Microchip Technology

Type: 8-Bit Flash Microcontroller with CAN Technology

Description: 64 MHz 8-bit RISC microcontroller with 64 KB Flash, 4 KB SRAM, CAN 2.0B, 12-bit ADC with Computation, and Core Independent Peripherals.

Operating Conditions:

• Supply voltage: 2.3V to 5.5V (PIC18F25/26K83), 1.8V to 3.6V (PIC18LF25/26K83)
• Operating temperature: -40°C to 85°C (Industrial)
• Maximum clock frequency: 64 MHz

Key Specs:

• Maximum CPU speed: 64 MHz (62.5 ns minimum instruction cycle)
• Flash program memory: 64 KB
• Data SRAM: 4096 bytes
• Data EEPROM: 1024 bytes
• 12-bit ADC with Computation (ADC²): 24 channels
• DAC: 5-bit rail-to-rail resolution (1 module)
• High-precision internal oscillator: up to 64 MHz (±1% at calibration nominal)
• Sleep mode current: 60 nA at 1.8V typical (XLP)

Features:

• CAN module conforming to CAN 2.0B Active Specification with up to 1 Mbps bit rates
• Two Direct Memory Access (DMA) controllers
• Vectored interrupt capability with selectable high/low priority
• Four Configurable Logic Cells (CLC)
• Three Complementary Waveform Generators (CWG)
• Two UART modules supporting LIN, DMX, and DALI protocols
• Two I²C modules (SMBus and PMBus compatible) and one SPI module
• 12-bit ADC with automated math, averaging, and threshold comparison
• Peripheral Pin Select (PPS) for dynamic I/O pin mapping

Applications:

• Automotive systems
• Industrial applications
• Motor control
• Sensor and user interface applications

Package:

• 28-pin SPDIP
• 28-pin SOIC
• 28-pin SSOP
• 28-pin UQFN
• 28-pin QFN

• C Compiler Optimized RISC Architecture
• Operating Speed:
• -Up to 64 MHz clock operation
• -62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
• -Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
• -User-programmable source and destination sizes
• -Hardware and software-triggered data transfers
• System Bus Arbiter with User-Configurable Priorities for Scanner and DMA1/DMA2 with respect to the main line and interrupt execution
• Vectored Interrupt Capability:
• -Selectable high/low priority
• -Fixed interrupt latency
• -Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
• -Variable prescaler selection
• -Variable window size selection
• -Configurable in hardware or software

For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively.