PIC16F1824

Part: PIC16F1827 — Microchip Technology

Type: Flash Microcontroller

Description: High-performance RISC CPU operating up to 32 MHz, with up to 16 KB Flash, 1024 bytes SRAM, 10-bit ADC, and multiple communication interfaces, featuring eXtreme Low-Power (XLP) technology.

Operating Conditions:

• Supply voltage: 1.8–5.5 V
• Max clock speed: 32 MHz

Key Specs:

• Program Memory: Up to 16 Kbytes Flash
• Data EEPROM: 256 bytes
• Data SRAM: Up to 1024 bytes
• ADC Resolution: 10-bit (up to 12 channels)
• I/O Pins: Up to 17 (1 input only)
• I/O Current Sink/Source: 25 mA/25 mA
• Sleep mode current (PIC16LF variants): 20 nA @ 1.8V, typical
• Operating Current (PIC16LF variants): 48 μA/MHz @ 1.8V, typical

Features:

• High-Performance RISC CPU with 49 instructions
• Flexible Oscillator Structure with 32 MHz internal oscillator and PLL
• Fail-Safe Clock Monitor
• Self-Programmable under Software Control
• Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST)
• Programmable Brown-out Reset (BOR)
• Extended Watchdog Timer (WDT)
• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD)
• Two Analog Comparators
• Fixed Voltage Reference (FVR) and 5-bit rail-to-rail resistive DAC
• Multiple Timers (Timer0, Enhanced Timer1, Timer2-types)
• Two Capture, Compare, PWM (CCP) Modules
• Two Enhanced CCP (ECCP) Modules
• Up to Two Master Synchronous Serial Port (MSSP) with SPI and I2C
• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
• mTouch™ Sensing Oscillator Module (up to 12 input channels)
• Data Signal Modulator Module
• SR Latch

Package:

• PDIP
• SOIC
• TSSOP
• QFN
• UQFN
• SSOP

• 1.8V-5.5V Operation - PIC16F1825/9
• 1.8V-3.6V Operation - PIC16LF1825/9
• Self-Programmable under Software Control
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Programmable Brown-out Reset (BOR)
• Extended Watchdog Timer (WDT)
• In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via Two Pins
• Enhanced Low-Voltage Programming (LVP)
• Programmable Code Protection
• Power-Saving Sleep mode

Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs.

The Alternate Pin Function Control 0 (APFCON0) and Alternate Pin Function Control 1 (APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are shown in Register 12-1 and Register 12-2. For this device family, the following functions can be moved between different pins.

• RX/DT/TX/CK
• SDO1
• SS (Slave Select)
• T1G
• P1B/P1C/P1D/P2B
• CCP1/P1A/CCP2

These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.

• Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
• 2: PLL required for 32 MHz operation.

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature, TJ = Junction Temperature.

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2257A