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PCA9548ADBR.A

8-Channel I2C Switch

The PCA9548ADBR.A is a 8-channel i2c switch from NXP Semiconductors. View the full PCA9548ADBR.A datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

Manufacturer

NXP Semiconductors

Category

8-Channel I2C Switch

Key Specifications

ParameterValue
PackagingMouseReel
Standard Pack Qty2500

Overview

Part: PCA9548A — Texas Instruments

Type: 8-Channel I2C Switch

Description: An 8-channel bidirectional translating I2C switch with an active-low reset input, supporting voltage-level translation between 1.8-V, 2.5-V, 3.3-V, and 5-V buses, and operating from a 2.3 V to 5.5 V supply.

Operating Conditions:

  • Supply voltage: 2.3 V to 5.5 V
  • Operating temperature: -40 to 85 °C
  • Clock frequency: 0 kHz to 400 kHz

Absolute Maximum Ratings:

  • Max supply voltage: 7 V
  • Max input voltage: 7 V
  • Max storage temperature: 150 °C

Key Specs:

  • Input voltage (SCL, SDA): 0.7 × VCC to 6 V (VIH), -0.5 to 0.3 × VCC (VIL)
  • Input voltage (A2-A0, RESET): 0.7 × VCC to VCC + 0.5 V (VIH), -0.5 to 0.3 × VCC (VIL)
  • ESD HBM: ±2000 V
  • ESD CDM: ±1000 V
  • Input current: -20 mA to 20 mA
  • Output current: -25 mA to 25 mA

Features:

  • 1-of-8 Bidirectional Translating Switches
  • I2C Bus and SMBus Compatible
  • Active-Low Reset Input
  • Three Hardware Address Pins for Use of up to Eight PCA9548A Devices on the I2C Bus
  • Channel Selection Via I2C Bus
  • Power-Up with All Switch Channels Deselected
  • Low RON Switches
  • Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses
  • No Glitch on Power Up
  • Supports Hot Insertion
  • Low Standby Current
  • 5-V Tolerant Inputs

Applications:

  • Servers
  • Routers (Telecom Switching Equipment)
  • Factory Automation
  • Products With I2C Slave Address Conflicts (For Example, Multiple, Identical Temp Sensors)

Package:

  • SSOP (24)
  • TVSOP (24)
  • SOIC (24)
  • TSSOP (24)
  • VQFN (24)

Features

  • 1-of-8 Bidirectional Translating Switches
  • I 2 C Bus and SMBus Compatible
  • Active-Low Reset Input
  • Three Hardware Address Pins for Use of up to Eight PCA9548A Devices on the I 2 C Bus
  • Channel Selection Via I 2 C Bus
  • Power-Up with All Switch Channels Deselected
  • Low RON Switches
  • Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses
  • No Glitch on Power Up
  • Supports Hot Insertion
  • Low Standby Current
  • Operating Power-Supply Voltage Range of 2.3 V to 5.5 V
  • 5-V Tolerant Inputs
  • 0-kHz to 400-kHz Clock Frequency
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • -2000-V Human-Body Model (A114-A)
  • -200-V Machine Model (A115-A)
  • -1000-V Charged-Device Model (C101)

Applications

Pin Configuration

Figure 5-1. DB, DGV, DW or PW Package, 24-Pin SSOP, TVSOP, SOIC or TSSOP , Top View

Table 5-1. Pin Functions

PINPIN
NO.
NAMEDB, DW, DGV , PW
A01
A12
RESET3
SD04
SC05
SD16
SC17
SD28
SC29
SD310
SC311
GND12
SD413
SC414
SD515
SC516
SD617
SC618
SD719
SC720
A221
SCL22
SDA23
V CC24

Table 5-1. Pin Functions

Figure 5-2. RGE Package, 24-Pin VQFN , Top View

Table 5-2. Pin Functions, RGE

PINPINI/ODESCRIPTION
NAMENO.I/ODESCRIPTION
SD01I/OSerial data 0. Connect to V CC through a pull-up resistor
SC02I/OSerial clock 0. Connect to V CC through a pull-up resistor
SD13I/OSerial data 1. Connect to V CC through a pull-up resistor
SC14I/OSerial clock 1. Connect to V CC through a pull-up resistor
SD25I/OSerial data 2. Connect to V CC through a pull-up resistor
SC26I/OSerial clock 2. Connect to V CC through a pull-up resistor
SD37I/OSerial data 3. Connect to V CC through a pull-up resistor
SC38I/OSerial clock 3. Connect to V CC through a pull-up resistor
GND9-Ground
SD410I/OSerial data 4. Connect to V CC through a pull-up resistor
SC411I/OSerial clock 4. Connect to V CC through a pull-up resistor
SD512I/OSerial data 5. Connect to V CC through a pull-up resistor
SC513I/OSerial clock 5. Connect to V CC through a pull-up resistor
SD614I/OSerial data 6. Connect to V CC through a pull-up resistor
SC615I/OSerial clock 6. Connect to V CC through a pull-up resistor
SD716I/OSerial data 7. Connect to V CC through a pull-up resistor
SC717I/OSerial clock 7. Connect to V CC through a pull-up resistor
A218IAddress input 2. Connect directly to V CC or ground
SCL19I/OSerial clock bus. Connect to V CC through a pull-up resistor
SDA20I/OSerial data bus. Connect to V CC through a pull-up resistor
V CC21-Supply voltage
A022IAddress input 0. Connect directly to V CC or ground
A123IAddress input 1. Connect directly to V CC or ground
RESET24IActive-low reset input. Connect to V CC through a pull-up resistor, if not used

Table 5-2. Pin Functions, RGE

Electrical Characteristics

VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)

  • PARAMETER PARAMETER PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT
  • V PORR Power-on reset voltage, V CC rising No load, V I = V CC or GND 1.2 1.5 V
  • V PORF Power-on reset voltage, V CC falling (2) No load, V I = V CC or GND 0.8 1 V
  • V 5 V 3.6
  • 4.5 V to 5.5 V 2.6 4.5
  • 3.3 V 1.9
  • o(sw) voltage V i(sw) = V CC , I SWout = -100 μA 3 V to 3.6 V 1.6 2.8 V
  • 2.5 V 1.5
  • 2.3 V to 2.7 V 1.1 2
  • I OL V OL = 0.4 V 2.3 V to 5.5 V 3 6 mA
  • SDA V OL = 0.6 V 6 9
  • SCL, SDA SCL, SDA -1 1
  • SC7-SC0, SD7-SD0 SC7-SC0, SD7-SD0 -1 1
  • I I A2-A0 A2-A0 V I = V CC or GND 2.3 V to 5.5 V -1 1 μA
  • RESET RESET -1 1
  • 5.5 V 50 80
  • f SCL = 400 kHz V I = V CC or GND, I O = 0 3.6 V 20 35
  • 2.7 V 11 20
  • 5.5 V 9 30
  • f SCL = 100 kHz V I = V CC or GND, I O = 0 3.6 V 6 15
  • 2.7 V 4 8
  • I CC 5.5 V 0.2 2 μA
  • Low inputs V I = GND, I O = 0 3.6 V 0.1 2
  • 2.7 V 0.1 1
  • 5.5 V 0.2 2
  • High inputs V I = V CC , I O = 0 3.6 V 0.1 2
  • 2.7 V 0.1 1
  • SCL or SDA input at 0.6 V, 3
  • ΔI CC SCL, SDA Other inputs at V CC or GND SCL or SDA input at V CC - 0.6 V, 2.3 V to 5.5 V 20 μA
  • Other inputs at V CC or GND 3 20
  • 4 5
  • C A2-A0 A2-A0 V I = V CC or GND 2.3 V to 5.5 V 4 5 pF
  • i 20 28
  • V = I V CC or GND, Switch OFF
  • C (3) SDA SDA V I = V CC or GND, Switch OFF 2.3 V to 5.5 V 20 28 pF
  • io(off) SD7-SD0 4.5 V to 5.5 V 5.5 7.5 20
  • R ON Switch-on resistance V O = 0.4 V, I O = 15 mA 4 10 Ω
  • V O = 0.4 V, I O = 10 mA 3 V to 3.6 V 2.3 V to 2.7 V 5 7 12 15 30 45

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MINMAXUNIT
V CCSupply voltage-0.57V
V IInput voltage (2)-0.57V
I IInput current-2020mA
I OOutput current-2525mA
I CCSupply current-100100mA
T stgStorage temperature-65150°C

Recommended Operating Conditions

See (1)

MINMAXUNIT
V CCSupply voltageSupply voltage2.35.5V
V IHSCL, SDA0.7 × V CC6V
A2-A0, RESET0.7 × V CCV CC + 0.5V
V ILSCL, SDA-0.50.3 × V CCV
V ILA2-A0, RESET-0.50.3 × V CCV
T AOperating free-air temperatureOperating free-air temperature-4085°C

Thermal Information

PCA9548APCA9548APCA9548APCA9548APCA9548A
THERMAL METRIC (1)THERMAL METRIC (1)DB (SSOP)DGV (TVSOP)DW (SOIC)PW (TSSOP)RGE (VQFN)
24 PINS24 PINS24 PINS24 PINS24 PINS
R θJAJunction-to-ambient thermal resistance89.199.673.2108.857.2
R θJC(top)Junction-to-case (top) thermal resistance51.131.141.354.162.5
R θJBJunction-to-board thermal resistance46.653.142.962.734.4
ψ JTJunction-to-top characterization parameter18.50.915.310.93.8
ψ JBJunction-to-board characterization parameter46.352.642.662.334.4
R θJC(bot)Junction-to-case (bottom) thermal resistanceN/AN/AN/AN/A15.5

Typical Application

Applications of the PCA9548A contain an I 2 C (or SMBus) master device and up to eight I 2 C slave devices. The downstream channels are ideally used to resolve I 2 C slave address conflicts. For example, if eight identical digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all other channels switched off, the data can be retrieved, and the I 2 C master can move on and read the next channel.

In an application where the I 2 C bus contains many additional slave devices that do not result in I 2 C slave address conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance across multiple channels. If multiple switches are enabled simultaneously, additional design requirements must be considered (See the Design Requirements and Detailed Design Procedure sections).

Related Variants

The following components are covered by the same datasheet.

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