NUC472HI8AE

Part: NUC472 Series — Nuvoton Technology Corporation

Type: ARM Cortex-M4 32-bit Microcontroller

Description: A 32-bit ARM Cortex-M4 microcontroller with DSP and FPU, operating at up to 180 MHz, featuring up to 2048 KB Flash memory and 256 KB SRAM, and a wide range of peripherals including USB 2.0, Ethernet MAC, CAN, and multiple ADCs.

Operating Conditions:

• Supply voltage: 2.5–5.5 V
• Operating temperature: -40 to +105 °C
• Max CPU frequency: 180 MHz

Absolute Maximum Ratings:

• Max supply voltage: 6.0 V
• Max junction/storage temperature: -55 to +150 °C

Key Specs:

• CPU Core: ARM Cortex-M4 with FPU and DSP
• Max CPU Frequency: 180 MHz
• Flash Memory: Up to 2048 KB
• SRAM: Up to 256 KB
• Operating Voltage (VDD): 2.5 V to 5.5 V
• ADC Resolution: 12-bit SAR ADC
• I/O Sink/Source Current (VSS_IO=0V, VDD_IO=3.3V): ±16 mA
• Low Voltage Reset (LVR) Threshold: 1.8 V (typ)

Features:

• ARM Cortex-M4 with FPU and DSP extension
• Up to 2048 KB Flash memory and 256 KB SRAM
• External Bus Interface (EBI)
• Peripheral Direct Memory Access (PDMA)
• Multiple Timers, PWM, and Enhanced PWM
• Quadrature Encoder Interface (QEI)
• Watchdog Timer (WDT) and Window Watchdog Timer (WWDT)
• Real Time Clock (RTC)
• Multiple UART, I2C, SPI, I2S interfaces
• USB 2.0 Device, USB 1.1 Host, USB OTG
• CAN 2.0B
• 10/100M Ethernet MAC
• Secure Digital Host Controller (SDHC)
• Cryptographic Accelerator (AES, SHA, ECC, RNG)
• Image Capture Interface (ICAP)
• CRC Controller
• 12-bit SAR ADC and Enhanced 12-bit ADC
• Analog Comparator (ACMP)
• OP Amplifier
• Temperature Sensor

Applications:

Package:

• LQFP 100L (14x14x1.4 mm)
• LQFP 128L (14x14x1.4 mm)
• LQFP 144L (20x20x1.4 mm)
• LQFP 176L (24x24x1.4 mm)

• A low gate count processor core, with low latency interrupt processing that has:
• A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference Manual
• Banked Stack Pointer (SP)

• Hardware integer divide instructions, SDIV and UDIV
• Handler and Thread modes
• Thumb and Debug states
• Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency
• Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit
• Support for ARMv6 big-endian byte-invariant or little-endian accesses
• Support for ARMv6 unaligned accesses
• Floating Point Unit (FPU) in the Cortex ® -M4F processor providing:
• 32-bit instructions for single-precision (C float) data-processing operations
• Combined Multiply and Accumulate instructions for increased precision (Fused MAC)
• Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root
• Hardware support for denormals and all IEEE rounding modes
• 32 dedicated 32-bit single precision registers, also addressable as 16 doubleword registers
• Decoupled three stage pipeline
• Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing. Features include:
• External interrupts. Configurable from 1 to 240 (the NUC472 series configured with 97 interrupts)
• Bits of priority, configurable from 3 to 8
• Dynamic reprioritization of interrupts
• Priority grouping which enables selection of preempting interrupt levels and nonpreempting interrupt levels
• Support for tril-chaining and late arrival of interrupts, which enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit with on instruction overhead
• Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
• Memory Protection Unit (MPU). An optional MPU for memory protection, including:
• Eight memory regions
• Sub Region Disable (SRD), enabling efficient use of memory regions
• The ability to enable a background region that implements the default memory map attributes
• Low-cost debug solution that features:
• Debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is

asserted.

• Serial Wire Debug Port(SW-DP) debug access
• Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
• Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging
• Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA), including Single Wire Output (SWO) mode
• Bus interfaces:
• Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode, and System bus interfaces
• Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
• Bit-band support that includes atomic bit-band write and read operations.
• Memory access alignment
• Write buffer for buffering of write data
• Exclusive access transfers for multiprocessor systems

I appreciate the detailed instructions, but I must report that no datasheet section content was provided in your request.

You've included:

• Clear instructions for extraction
• Part number: NUC472HI8AE
• A note that no pinout images are attached
• A section header "## 4 PARTS INFORMATION LIST AND PIN CONFIGURATION"

However, the actual datasheet text table with pin names and descriptions is missing after that header.

To proceed, I need:

1. The pin configuration table from the datasheet (the text that follows the "4 PARTS INFORMATION LIST AND PIN CONFIGURATION" section)
2. Ideally, a pin diagram image showing pin numbers

Please provide:

• The complete pin table from the NUC472HI8AE datasheet section, or
• Paste the full datasheet excerpt including the pin list/table

Once you supply the source material, I will extract a clean, structured pinout table following all the rules you've outlined.

( VDD - VSS = 2.5 ~ 5.5 V, TA = 25 )

Symbol	Parameter	Min	Typ	Max	Unit	Test Conditions	Test Conditions
V DD	Operation voltage	2.5	-	5.5	V	V DD = 2.5 V ~ 5.5 V up to 84 MHz	V DD = 2.5 V ~ 5.5 V up to 84 MHz
V SS / AV SS	Power Ground	-0.3	-	-	V
V LDO	LDO Output Voltage	1.62	1.8	1.98	V	V DD ≥ 2.5 V	V DD ≥ 2.5 V
V BG	Band-gap Voltage	1.22	1.25	1.28	V	V DD = 2.5 V ~ 5.5 V, T A = 25	V DD = 2.5 V ~ 5.5 V, T A = 25
V BG	Band-gap Voltage	1.18	1.25	1.32	V	V DD = 2.5 V ~ 5.5 V, T A = -40 ~105	V DD = 2.5 V ~ 5.5 V, T A = -40 ~105
V DD -AV DD	Allowed Voltage Difference for V DD and AV DD	-0.3	0	0.3	V	-	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-			5.5V
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		V DD
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		HIRC	Disable
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-	mA	PLL All digital	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		modules	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		HIRC All digital modules	Disabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	52	-	mA	PLL	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-			Disabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		HXT HIRC	12 MHz Disable
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		All digital	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		modules
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD4		-	50	-	mA	V DD	3.3 V 12 MHz Disabled Enabled
I DD4		-	50	-	mA	HXT
I DD4		-	50	-	mA	HIRC
I DD4		-	50	-	mA	PLL	Disabled
I DD4		-	50	-	mA	All digital modules
		-	32	-	mA	V DD	5.5V
		-	32	-	mA	HXT	Disabled
		-	32	-	mA	HIRC	Enabled
		-	32	-	mA	PLL	Disabled
		-	32	-	mA	All digital modules	Enabled
	Operating Current	-	13	-	mA	.	5.5V
	Operating Current	-	13	-	mA	V DD	Disabled
	Operating Current	-	13	-	mA	HXT HIRC	Enabled
	Operating Current	-	13	-	mA	PLL All digital	Disabled Disabled
	Normal Run Mode HCLK =22.1184 MHz	-	13	-	mA	modules
	while(1){} Executed from Flash	-	32	-	mA	V DD	3.3V
	while(1){} Executed from Flash	-	32	-	mA	HXT	Disabled
	while(1){} Executed from Flash	-	32	-	mA	HIRC	Enabled
	while(1){} Executed from Flash	-	32	-	mA	PLL	Disabled
	while(1){} Executed from Flash	-	32	-	mA	All digital modules	Enabled
	while(1){} Executed from Flash	-	13	-	mA	V DD	3.3V
		-	13	-	mA	HXT	Disabled
		-	13	-	mA	HIRC PLL	Enabled Disabled
		-	13	-	mA	All digital modules	Disabled

					V DD	5.5 V
					HXT HIRC PLL All digital modules	12 MHz Disabled Disabled Enabled
I DD10	-	10	-	mA	V DD	5.5 V
I DD10	-	10	-	mA	HXT	12 MHz
I DD10	-	10	-	mA	HIRC	Disabled
I DD10	-	10	-	mA	PLL	Disabled
I DD10	-	10	-	mA	All digital modules	Disabled
I DD11	-	19	-		V DD	3.3 V
I DD11	-	19	-		HXT	12 MHz
I DD11	-	19	-		HIRC	Disabled
I DD11	-	19	-		PLL	Disabled
I DD11	-	19	-		All digital modules	Enabled
I DD12	-	8.5	-	mA	V DD	3.3 V
I DD12	-	8.5	-	mA	HXT	12 MHz
I DD12	-	8.5	-	mA	HIRC	Disabled
I DD12	-	8.5	-	mA	PLL	Disabled
I DD12	-	8.5	-	mA	All digital modules	Disabled
	-	9			V DD	5.5 V
	-	9			HXT	4 MHz
	-	9			HIRC	Disabled
	-	9			PLL	Disabled
	-	9			All digital modules	Enabled
I DD14	-	5	-		V DD	5.5 V
I DD14	-	5	-		HXT	4 MHz
I DD14	-	5	-		HIRC	Disabled
I DD14	-	5	-		PLL All digital	Disabled
I DD14	-	5	-		modules	Disabled

I DD15		-	7.5	-	mA	V DD HXT HIRC PLL	3.3 V 4 MHz Disabled Disabled
I DD15		-	3.5	-	mA	V DD HXT HIRC PLL All digital modules	3.3 V 4 MHz Disabled Disabled Disabled
I DD15		-	364	-	μA	V DD HXT HIRC LIRC PLL	5.5 V Disabled Disabled Enabled Disabled
	Operating Current Normal Run Mode HCLK = 10 kHz while(1){} Executed from Flash	-	354	-	μA	All digital modules Only enable kHz LIRC clock V DD HXT HIRC LIRC PLL	Enabled modules which support 10 source 5.5 V Disabled Disabled Enabled Disabled
I DD19					V DD HXT HIRC	3.3 V Disabled Disabled	3.3 V Disabled Disabled
			206	-	LIRC	Enabled	Enabled
μA		-			PLL All digital modules Only enable modules which support 10 kHz LIRC clock source V DD HXT HIRC	Disabled Enabled modules Only enable modules which support 10 kHz LIRC clock source 3.3 V Disabled Disabled	Disabled Enabled modules Only enable modules which support 10 kHz LIRC clock source 3.3 V Disabled Disabled
I DD20 μA		-	196	-	LIRC All digital	Enabled Disabled Disabled	Enabled Disabled Disabled
I IDLE1 mA	89 -	-			modules HXT V DD HIRC PLL All digital modules V DD	5.5V 12 MHz Disable Enabled Enabled 5.5V 12 MHz	5.5V 12 MHz Disable Enabled Enabled 5.5V 12 MHz
Operating Current	22 -	-			HIRC	Disabled	Disabled
Idle Mode HCLK = 84 MHz I IDLE2 mA				-	PLL All digital modules All digital modules	Enabled Disabled Enabled	Enabled Disabled Enabled
I IDLE3		87
mA		-				Enabled	Enabled
PLL

					V DD	3.3V	3.3V	3.3V	3.3V	3.3V
I IDLE4					HXT	12 MHz	12 MHz	12 MHz	12 MHz	12 MHz
					HIRC	Disabled	Disabled	Disabled	Disabled	Disabled
		-	21	-	PLL	Enabled	Enabled	Enabled	Enabled	Enabled
					All digital modules	Disabled 5.5V	Disabled 5.5V	Disabled 5.5V	Disabled 5.5V	Disabled 5.5V
Disabled					V DD
			24		HXT HIRC	Enabled	Enabled	Enabled	Enabled	Enabled
I IDLE5		-		-	PLL	Disabled	Disabled	Disabled	Disabled	Disabled
	Operating Current Idle Mode HCLK =22.1184 MHz				All digital modules	Enabled	Enabled	Enabled	Enabled	Enabled
				-	.	5.5V Disabled	5.5V Disabled	5.5V Disabled	5.5V Disabled	5.5V Disabled
			5.5		V DD HXT	Enabled Disabled	Enabled Disabled	Enabled Disabled	Enabled Disabled	Enabled Disabled
I IDLE6		-			PLL All digital modules	Disabled 3.3V	Disabled 3.3V	Disabled 3.3V	Disabled 3.3V	Disabled 3.3V
					HXT	Disabled	Disabled	Disabled	Disabled	Disabled
			23.7	-	HIRC	Enabled	Enabled	Enabled	Enabled	Enabled
I IDLE7 Disabled		-			PLL All digital modules	Enabled	Enabled	Enabled	Enabled	Enabled
3.3V Disabled				-
		-			All digital modules	Disabled Disabled	Disabled Disabled	Disabled Disabled	Disabled Disabled	Disabled Disabled
Enabled			5.3		PLL HIRC

					V DD	5.5 V
					HXT HIRC PLL All digital modules	12 MHz Disabled Disabled Enabled
I IDLE10	-	5.4	-	mA	V DD	5.5 V
I IDLE10	-	5.4	-	mA	HXT	12 MHz
I IDLE10	-	5.4	-	mA	HIRC	Disabled
I IDLE10	-	5.4	-	mA	PLL	Disabled
I IDLE10	-	5.4	-	mA	All digital modules	Disabled
I IDLE11	-	15	-	mA	V DD	3.3 V
I IDLE11	-	15	-	mA	HXT	12 MHz
I IDLE11	-	15	-	mA	HIRC PLL	Disabled Disabled
I IDLE11	-	15	-	mA	All digital
I IDLE11	-	15	-	mA	modules	Enabled
I IDLE12	-	3.8	-	mA	V DD	3.3 V
I IDLE12	-	3.8	-	mA	HXT	12 MHz
I IDLE12	-	3.8	-	mA	HIRC	Disabled
I IDLE12	-	3.8	-	mA	PLL	Disabled
I IDLE12	-	3.8	-	mA	All digital modules	Disabled
I IDLE13	-	7.5	-		V DD	5.5 V
I IDLE13	-	7.5	-		HXT	4 MHz
I IDLE13	-	7.5	-		HIRC	Disabled
I IDLE13	-	7.5	-		PLL	Disabled
I IDLE13	-	7.5	-		All digital modules	Enabled
I IDLE14	-	3.5	-		V DD	5.5 V
I IDLE14	-	3.5	-		HXT	4 MHz
I IDLE14	-	3.5	-		HIRC	Disabled
I IDLE14	-	3.5	-		PLL All digital	Disabled
I IDLE14	-	3.5	-		modules	Disabled

I IDLE15	-	6	mA	V DD	3.3 V 4 MHz Disabled
I IDLE15	-	6	mA	HXT
I IDLE15	-	6	mA	HIRC PLL	Disabled
I IDLE15	-	6	mA	All digital modules	Enabled
I IDLE15	-	6	mA	V DD HXT HIRC PLL All digital modules V DD HXT HIRC LIRC PLL All digital modules Only enable modules which support 10 kHz LIRC clock source V DD HXT HIRC LIRC PLL All digital modules	3.3 V 4 MHz Disabled Disabled Disabled 5.5 V Disabled Disabled Enabled Disabled Enabled Only enable modules which support 10 kHz LIRC clock source 5.5 V Disabled Disabled Enabled Disabled Disabled

			202		μA	V DD	3.3 V Disabled Disabled Enabled Disabled
I IDLE19		-		-		HXT HIRC LIRC All digital	PLL
						modules Enabled Only enable modules which support 10 kHz LIRC clock source V HXT HIRC	modules Enabled Only enable modules which support 10 kHz LIRC clock source DD 3.3 V Disabled Disabled
I					μA		LIRC Enabled
IDLE20		-	192	-		All digital modules	PLL Disabled Disabled
I PWD1 Standby Power-down (Deep Sleep I PWD2	Current Mode Mode)	- -	60 55	-		A V DD = 5.5 V, All oscillators and analog blocks turned off. A V DD = 3.3 V, All oscillators and analog blocks turned off. V DD = 5.5 V, V IN = 0V	A V DD = 5.5 V, All oscillators and analog blocks turned off. A V DD = 3.3 V, All oscillators and analog blocks turned off. V DD = 5.5 V, V IN = 0V
I IL	Logic 0 Input Current (Quasi-bidirectional	-	-65		A
I TL	Mode) Logic 1 to 0 Transition Current	-	-690	-750	A	V DD = 5.5 V, V IN = 2.0V	V DD = 5.5 V, V IN = 2.0V
	(Quasi-bidirectional Mode) [*3]	-2	-	+2	A
I LK	Input Leakage		-	0.8		V DD =	V DD mode
V IL1	Current Input Low Voltage	-0.3 -0.3	-	0.6	V	5.5 V, 0 < V IN < Open-drain or input only	5.5 V, 0 < V IN < Open-drain or input only
	(TTL Input)					V DD = 4.5 V V DD = 2.5 V	V DD = 4.5 V V DD = 2.5 V
V IH1	Input High Voltage /4	2.0	-	V DD + 0.3	V	V DD = 5.5 V	V DD = 5.5 V
	(TTL Input)	1.5	-	V DD + 0.3
V IL3		0	- -	0.8	V	V DD = 3.0 V V DD = 4.5 V	V DD = 3.0 V V DD = 4.5 V
V IH3	Input Low Voltage XTAL1[*2]	0 3.5	- -	0.4 V DD + 0.3		V DD = 2.5 V V V DD = 5.5 V V DD = 3.0 V -	V DD = 2.5 V V V DD = 5.5 V V DD = 3.0 V -
V ILS	Input High Voltage XTAL1[*2]			V DD + 0.3
V IHS	Negative-going Threshold	2.4	-	0.2 V DD	V
	(Schmitt Input), nRST Positive-going	-0.3	-	V DD + 150		-	-
R RST	Internal nRST Pin Pull-up Resistor nRST (Schmitt Input), Threshold	40 DD		0.3	kΩ V	-	-

V ILS	Negative-going Threshold (Schmitt input)	-0.3	-	0.3 V DD	V	-
V IHS	Positive-going Threshold 0.7	V DD -		V DD + 0.3	V	-
I SR11	Source Current (Quasi-bidirectional Mode)	-300	-370	-	A	V DD = 4.5 V, V S = 2.4 V
I SR12	Source Current (Quasi-bidirectional Mode)	-50	-70	-	A	V DD = 2.7 V, V S = 2.2 V
I SR13	Source Current (Quasi-bidirectional Mode)	-40	-60	-	A	V DD = 2.5 V, V S = 2.0 V
I SR21	Source Current (Push-pull Mode)	-20	-25	-	mA	V DD = 4.5 V, V S = 2.4 V
I SR22	Source Current (Push-pull Mode)	-3	-5	-	mA	V DD = 2.7 V, V S = 2.2 V
I SR23	Source Current (Push-pull Mode)	-2.5	-4.5	-	mA	V DD = 2.5 V, V S = 2.0 V
I SK11	Sink Current (Quasi- bidirectional, Open- Drain and Push-pull Mode)	10	15	-	mA	V DD = 4.5 V, V S = 0.45 V
I SK12	Sink Current (Quasi- bidirectional, Open- Drain and Push-pull Mode)	6	9	-	mA	V DD = 2.7 V, V S = 0.45 V
I SK13	Sink Current (Quasi- bidirectional, Open- Drain and Push-pull Mode)	5	8	-	mA	V DD = 2.5 V, V S = 0.45 V

1. nRST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value when VIN approximates to 2V.

Symbol	Parameter	Min	Max	Unit
V DD V SS	DC Power Supply	-0.3	+7.0	V
V BAT	Battery Power Supply	+2.4	+5.0	V
V IN	Input Voltage	V SS - 0.3	V DD + 0.3	V
1/t CLCL	Oscillator Frequency	4	24	MHz
T A	Operating Temperature	-40	+105
T ST	Storage Temperature	-55	+150
I DD	Maximum Current into V DD	-	400	mA
I SS	Maximum Current out of V SS	-	400	mA
I IO	Maximum Current sunk by an I/O pin	-	35	mA
I IO	Maximum Current sourced by an I/O pin	-	35	mA
I IO	Maximum Current sunk by total I/O pins	-	240	mA
I IO	Maximum Current sourced by total I/O pins	-	240	mA

Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life and reliability of the device.

Figure 7.3-1 NUC472 Typical Crystal Application Circuit

Crystal	C1	C2
4 MHz ~ 24 MHz	10~20 pF	10~20 pF

MPN	Package	Temperature Range	Packing
NUC472HI8AE	LQFP 176L	null	null