NUC472

Part: NUC472 Series — Nuvoton Technology Corporation

Type: ARM Cortex-M4 32-bit Microcontroller

Description: A 32-bit ARM Cortex-M4 microcontroller with DSP and FPU, operating at up to 180 MHz, featuring up to 2048 KB Flash memory and 256 KB SRAM, and a wide range of peripherals including USB 2.0, Ethernet MAC, CAN, and multiple ADCs.

Operating Conditions:

• Supply voltage: 2.5–5.5 V
• Operating temperature: -40 to +105 °C
• Max CPU frequency: 180 MHz

Absolute Maximum Ratings:

• Max supply voltage: 6.0 V
• Max junction/storage temperature: -55 to +150 °C

Key Specs:

• CPU Core: ARM Cortex-M4 with FPU and DSP
• Max CPU Frequency: 180 MHz
• Flash Memory: Up to 2048 KB
• SRAM: Up to 256 KB
• Operating Voltage (VDD): 2.5 V to 5.5 V
• ADC Resolution: 12-bit SAR ADC
• I/O Sink/Source Current (VSS_IO=0V, VDD_IO=3.3V): ±16 mA
• Low Voltage Reset (LVR) Threshold: 1.8 V (typ)

Features:

• ARM Cortex-M4 with FPU and DSP extension
• Up to 2048 KB Flash memory and 256 KB SRAM
• External Bus Interface (EBI)
• Peripheral Direct Memory Access (PDMA)
• Multiple Timers, PWM, and Enhanced PWM
• Quadrature Encoder Interface (QEI)
• Watchdog Timer (WDT) and Window Watchdog Timer (WWDT)
• Real Time Clock (RTC)
• Multiple UART, I2C, SPI, I2S interfaces
• USB 2.0 Device, USB 1.1 Host, USB OTG
• CAN 2.0B
• 10/100M Ethernet MAC
• Secure Digital Host Controller (SDHC)
• Cryptographic Accelerator (AES, SHA, ECC, RNG)
• Image Capture Interface (ICAP)
• CRC Controller
• 12-bit SAR ADC and Enhanced 12-bit ADC
• Analog Comparator (ACMP)
• OP Amplifier
• Temperature Sensor

Applications:

Package:

• LQFP 100L (14x14x1.4 mm)
• LQFP 128L (14x14x1.4 mm)
• LQFP 144L (20x20x1.4 mm)
• LQFP 176L (24x24x1.4 mm)

• A low gate count processor core, with low latency interrupt processing that has:
• A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference Manual
• Banked Stack Pointer (SP)

• Hardware integer divide instructions, SDIV and UDIV
• Handler and Thread modes
• Thumb and Debug states
• Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency
• Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit
• Support for ARMv6 big-endian byte-invariant or little-endian accesses
• Support for ARMv6 unaligned accesses
• Floating Point Unit (FPU) in the Cortex ® -M4F processor providing:
• 32-bit instructions for single-precision (C float) data-processing operations
• Combined Multiply and Accumulate instructions for increased precision (Fused MAC)
• Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root
• Hardware support for denormals and all IEEE rounding modes
• 32 dedicated 32-bit single precision registers, also addressable as 16 doubleword registers
• Decoupled three stage pipeline
• Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing. Features include:
• External interrupts. Configurable from 1 to 240 (the NUC472 series configured with 97 interrupts)
• Bits of priority, configurable from 3 to 8
• Dynamic reprioritization of interrupts
• Priority grouping which enables selection of preempting interrupt levels and nonpreempting interrupt levels
• Support for tril-chaining and late arrival of interrupts, which enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit with on instruction overhead
• Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
• Memory Protection Unit (MPU). An optional MPU for memory protection, including:
• Eight memory regions
• Sub Region Disable (SRD), enabling efficient use of memory regions
• The ability to enable a background region that implements the default memory map attributes
• Low-cost debug solution that features:
• Debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is

asserted.

• Serial Wire Debug Port(SW-DP) debug access
• Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
• Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging
• Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA), including Single Wire Output (SWO) mode
• Bus interfaces:
• Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode, and System bus interfaces
• Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
• Bit-band support that includes atomic bit-band write and read operations.
• Memory access alignment
• Write buffer for buffering of write data
• Exclusive access transfers for multiprocessor systems

MFP = Multi-function pin.

Pin No.	Pin Name	Type	MFP*	Description
1	PE.12	I/O	MFP0	General purpose digital I/O pin.
1	ADC1_4	A	MPF1	ADC1 analog input.
1	ACMP1_P3	A	MPF2	Analog comparator1 positive input pin.
1	ACMP2_P2	A	MPF3	Analog comparator2 positive input pin.
1	EBI_nCS1	O	MPF7	EBI chip select 1 enable output pin.
1	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
2	PE.13	I/O	MFP0	General purpose digital I/O pin.
2	ADC1_5	A	MPF1	ADC1 analog input.
2	ACMP2_P1	A	MPF3	Analog comparator2 positive input pin.
2	EBI_nCS2	O	MPF7	EBI chip select 2 enable output pin.
2	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
3	PE.14	I/O	MFP0	General purpose digital I/O pin.
3	ADC1_6	A	MPF1	ADC1 analog input.
3	ACMP2_P0	A	MPF3	Analog comparator2 positive input pin.
3	EBI_nCS3	O	MPF7	EBI chip select 3 enable output pin.
3	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
4	PE.15	I/O	MFP0	General purpose digital I/O pin.
4	ADC1_7	A	MPF1	ADC1 analog input.
4	ACMP2_N	A	MPF3	Analog comparator2 negative input pin.
5	V SS	P	MFP0	Ground pin for digital circuit.
6	V DD	P	MFP0	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
7	PC.12	I/O	MFP0	General purpose digital I/O pin.
	SPI1_SS0	I/O	MPF1	1st SPI1 slave select pin.
	SC4_CD	I	MPF2	SmartCard4 card detect pin.
	SD1_CDn	I	MPF4	SD mode #1 - card detect
	CAP_DATA7	I	MPF5	Image data input bus bit 7.
	EBI_A0	O	MPF7	EBI address bus bit0.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
8	PC.13	I/O	MFP0	General purpose digital I/O pin.
8	SPI1_MOSI1	I/O	MPF1	2nd SPI1 MOSI (Master Out, Slave In) pin.
8	SC4_RST	O	MPF2	SmartCard4 reset pin.
8	SD1_CMD	I/O	MPF4	SD mode #1 - command/response
8	CAP_DATA6	I	MPF5	Image data input bus bit 6.
8	EBI_A1	O	MPF7	EBI address bus bit1.
8	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
9	PC.14	I/O	MFP0	General purpose digital I/O pin.
9	SPI1_MISO1	I/O	MPF1	2nd SPI1 MISO (Master In, Slave Out) pin.
9	SC4_PWR	O	MPF2	SmartCard4 power pin.
9	TM3_EXT	I	MPF3	Timer3 external counter input
9	SD1_CLK	O	MPF4	SD mode #1 - clock.
9	CAP_DATA5	I	MPF5	Image data input bus bit 5.
9	EBI_A2	O	MPF7	EBI address bus bit2.
9	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
10	PC.15	I/O	MFP0	General purpose digital I/O pin.
10	SPI1_MOSI0	I/O	MPF1	1st SPI1 MOSI (Master Out, Slave In) pin.
10	SC4_DAT	I/O	MPF2	SmartCard4 data pin.
10	SD1_DAT3	I/O	MPF4	SD mode #1 data line bit 3.
10	CAP_DATA4	I	MPF5	Image data input bus bit 4.
10	EBI_A3	O	MPF7	EBI address bus bit3.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
11	PD.0	I/O	MFP0	General purpose digital I/O pin.
11	SPI1_MISO0	I/O	MPF1	1st SPI1 MISO (Master In, Slave Out) pin.
11	SC4_CLK	O	MPF2	SmartCard4 clock pin.
11	SD1_DAT2	I/O	MPF4	SD mode #1 data line bit 2.
11	CAP_DATA3	I	MPF5	Image data input bus bit 3.
11	EBI_A4	O	MPF7	EBI address bus bit4.
11	INT3	I	MPF8	External interrupt3 input pin.
11	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
12	PD.1	I/O	MFP0	General purpose digital I/O pin.
12	SPI1_CLK	O	MPF1	SPI1 serial clock pin.
12	TM0_CNT_OUT	I/O	MPF3	Timer0 event counter input/toggle output.
12	SD1_DAT1	I/O	MPF4	SD mode #1 data line bit 1;
12	CAP_DATA2	I	MPF5	Image data input bus bit 2.
12	EBI_A5	O	MPF7	EBI address bus bit5.
12	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
13	PD.3	I/O	MFP0	General purpose digital I/O pin.
13	SC5_CLK	O	MPF1	SmartCard5 clock pin.
13	I2C3_SDA	I/O	MPF2	I2C3 data input/output pin.
13	ACMP2_O	O	MPF3	Analog comparator2 output.
13	SD0_CDn	I	MPF4	SD mode #0 - card detect
13	CAP_DATA0	I	MPF5	Image data input bus bit 0.
13	EBI_A7	O	MPF7	EBI address bus bit7.
13	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
14	PD.4	I/O	MFP0	General purpose digital I/O pin.
14	SC5_CD	I	MPF1	SmartCard5 card detect pin.
	UART3_RXD	I	MPF2	Data receiver input pin for UART3.
	ACMP1_O	O	MPF3	Analog comparator1 output.
	CAP_SCLK	O	MPF5	Image capture interface sensor clock pin.
	EBI_A8	O	MPF7	EBI address bus bit8.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
15	PD.5	I/O	MFP0	General purpose digital I/O pin.
15	SC5_RST	O	MPF1	SmartCard5 reset pin.
15	UART3_TXD	O	MPF2	Data transmitter output pin for UART3.
15	CAP_VSYNC	I	MPF5	Image capture interface VSYNC input pin.
15	EBI_A9	O	MPF7	EBI address bus bit9.
15	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
16	PD.6	I/O	MFP0	General purpose digital I/O pin.
16	SC5_PWR	O	MPF1	SmartCard5 power pin.
16	UART3_RTS	O	MPF2	Request to Send output pin for UART3.
16	SD0_CMD	I/O	MPF4	SD mode #0 - command/response
16	CAP_HSYNC	I	MPF5	Image capture interface HSYNC input pin.
16	EBI_A10	O	MPF7	EBI address bus bit10.
16	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
17	PD.7	I/O	MFP0	General purpose digital I/O pin.
17	SC5_DAT	I/O	MPF1	SmartCard5 data pin.
17	UART3_CTS	I	MPF2	Clear to Send input pin for UART3.
17	SD0_CLK	O	MPF4	SD mode #0 - clock.
17	CAP_PIXCLK	I	MPF5	Image capture interface pix clock input pin.
17	EBI_A11	O	MPF7	EBI address bus bit11.
17	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
18	PG.13	I/O	MFP0	General purpose digital I/O pin.
	XT1_IN	I	MPF1	External 4~24 MHz (high-speed) crystal input pin.
19	PG.12	I/O	MFP0	General purpose digital I/O pin.
19	XT1_OUT	O	MPF1	External 4~24 MHz (high-speed) crystal output pin.
20	nRESET	I	MFP0	External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. Note: It is recommended to use 10 kΩ pull-up resistor and 10 μF capacitor on nRESET pin.
21	LDO_CAP	P	MFP0	LDO output pin. Note: This pin needs to be connected with an external capacitor.
22	V SS	P	MFP0	Ground pin for digital circuit.
23	V DD	P	MFP0	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
24	PG.10	I/O	MFP0	General purpose digital I/O pin.
24	ICE_CLK	I	MPF1	Serial wired debugger clock pin Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
25	PG.11	I/O	MFP0	General purpose digital I/O pin.
25	ICE_DAT	I/O	MPF1	Serial wired debugger data pin Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
26	PG.15	I/O	MFP0	General purpose digital I/O pin.
26	X32K_IN	I	MPF1	External 32.768 kHz (low-speed) crystal input pin.
26	I2C1_SCL	I/O	MPF3	I2C1 clock pin.
27	PG.14	I/O	MFP0	General purpose digital I/O pin.
27	X32K_OUT	O	MPF1	External 32.768 kHz (low-speed) crystal output pin.
27	I2C1_SDA	I/O	MPF3	I2C1 data input/output pin.
28	V BAT	P	MFP0	Battery power input pin.
29	PA.0	I/O	MFP0	General purpose digital I/O pin.
29	TAMPER0	I/O	MPF1	Tamper detect pin 0.
29	SC0_CD	I	MPF2	SmartCard0 card detect pin.
29	CAN1_RXD	I	MPF3	CAN bus receiver1 input.
	INT0	I	MPF8	External interrupt0 input pin.
30	PA.1	I/O	MFP0	General purpose digital I/O pin.
30	TAMPER1	I/O	MPF1	Tamper detect pin 1.
30	SC5_CD	I	MPF2	SmartCard5 card detect pin.
30	CAN1_TXD	I	MPF3	CAN bus transmitter1 input.
30	EBI_A22	O	MPF7	EBI address bus bit22.
31	PA.2	I/O	MFP0	General purpose digital I/O pin.
31	SC2_DAT	I/O	MPF1	SmartCard2 data pin.
31	SPI3_MISO0	I/O	MPF2	1st SPI3 MISO (Master In, Slave Out) pin.
31	I2S0_MCLK	O	MPF3	I2S0 master clock output pin.
31	BRAKE11	I	MPF4	Brake input pin 1 of EPWM0.
31	CAP_SFIELD	I	MPF5	Video input interface SFIELD input pin.
31	EBI_A12	O	MPF7	EBI address bus bit12.
31	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
32	PA.3	I/O	MFP0	General purpose digital I/O pin.
32	SC2_CLK	O	MPF1	SmartCard2 clock pin.
32	SPI3_MOSI0	I/O	MPF2	1st SPI3 MOSI (Master Out, Slave In) pin.
32	I2S0_DO	O	MPF3	I2S0 data output.
32	BRAKE10	I	MPF4	Brake input pin 0 of EPWM0.
32	EBI_A13	O	MPF7	EBI address bus bit13.
32	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
33	PA.4	I/O	MFP0	General purpose digital I/O pin.
33	SC2_PWR	O	MPF1	SmartCard2 power pin.
33	SPI3_CLK	O	MPF2	SPI3 serial clock pin.
33	I2S0_DI	I	MPF3	I2S0 data input.
33	QEI1_Z	I	MPF5	Quadrature encoder phase Z input of QEI Unit 1.
33	EBI_A14	O	MPF7	EBI address bus bit14.
	ECAP1_IC2	I	MPF8	Input 2 of enhanced capture unit 1.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
34	PA.5	I/O	MFP0	General purpose digital I/O pin.
34	SC2_RST	O	MPF1	SmartCard2 reset pin.
34	SPI3_SS0	I/O	MPF2	General purpose digital I/O pin.
34	I2S0_BCLK	O	MPF3	I2S0 bit clock pin.
34	PWM0_0	I/O	MPF4	PWM0_0 output/capture input.
34	QEI1_B	I	MPF5	Quadrature encoder phase B input of QEI Unit 1.
34	EBI_A15	O	MPF7	EBI address bus bit15.
34	ECAP1_IC1	I	MPF8	Input 1 of enhanced capture unit 1.
34	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
35	PA.6	I/O	MFP0	General purpose digital I/O pin.
35	SC2_CD	I	MPF1	SmartCard2 card detect pin.
35	I2S0_LRCK	O	MPF3	I2S0 left right channel clock.
35	PWM0_1	I/O	MPF4	PWM0_1 output/capture input.
35	QEI1_A	I	MPF5	Quadrature encoder phase Ainput of QEI Unit 1.
35	CAN1_TXD	I	MPF6	CAN bus transmitter1 input.
35	EBI_A16	O	MPF7	EBI address bus bit16.
35	ECAP1_IC0	I	MPF8	Input 0 of enhanced capture unit 1.
35	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
36	PA.7	I/O	MFP0	General purpose digital I/O pin.
36	SC0_CLK	O	MPF2	SmartCard0 clock pin.
36	SPI3_SS0	I/O	MPF3	General purpose digital I/O pin.
36	PWM1_3	I/O	MPF4	PWM1_3 output/capture input.
36	EPWM0_5	I/O	MPF5	PWM0_5 output/capture input.
36	EBI_A17	O	MPF7	EBI address bus bit17.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
37	PA.8	I/O	MFP0	General purpose digital I/O pin.
37	SC0_RST	O	MPF2	SmartCard0 reset pin.
37	SPI3_CLK	O	MPF3	SPI3 serial clock pin.
37	PWM1_2	I/O	MPF4	PWM1_2 output/capture input.
37	EPWM0_4	I/O	MPF5	PWM0_4 output/capture input.
37	EBI_A18	O	MPF7	EBI address bus bit18.
37	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
38	PA.9	I/O	MFP0	General purpose digital I/O pin.
38	SC0_PWR	O	MPF2	SmartCard0 power pin.
38	SPI3_MISO0	I/O	MPF3	1st SPI3 MISO (Master In, Slave Out) pin.
38	PWM1_1	I/O	MPF4	PWM1_1 output/capture input.
38	EPWM0_3	I/O	MPF5	PWM0_3 output/capture input.
38	EBI_A19	O	MPF7	EBI address bus bit19.
38	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
39	PA.10	I/O	MFP0	General purpose digital I/O pin.
39	SC0_DAT	I/O	MPF2	SmartCard0 data pin.
39	SPI3_MOSI0	I/O	MPF3	1st SPI3 MOSI (Master Out, Slave In) pin.
39	PWM1_0	I/O	MPF4	PWM1_0 output/capture input.
39	EPWM0_2	I/O	MPF5	PWM0_2 output/capture input.
39	EBI_A20	O	MPF7	EBI address bus bit20.
39	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
40	PA.11	I/O	MFP0	General purpose digital I/O pin.
40	UART0_RTS	O	MPF1	Request to Send output pin for UART0.
40	SPI3_MISO1	I/O	MPF3	2nd SPI3 MISO (Master In, Slave Out) pin.
40	PWM0_5	I/O	MPF4	PWM0_5 output/capture input.
	EPWM0_1	I/O	MPF5	PWM0_1 output/capture input.
	EBI_AD0	O	MPF7	EBI address/data bus bit 0.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
41	PA.12	I/O	MFP0	General purpose digital I/O pin.
	UART0_CTS	I	MPF1	Clear to Send input pin for UART0.
	SPI3_MOSI1	I/O	MPF3	2nd SPI3 MOSI (Master Out, Slave In) pin.
	PWM0_4	I/O	MPF4	PWM0_4 output/capture input.
	EPWM0_0	I/O	MPF5	PWM0_0 output/capture input.
	EBI_AD1	O	MPF7	EBI address/data bus bit 1.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
42	PA.13	I/O	MFP0	General purpose digital I/O pin.
	UART0_RXD	I	MPF1	Data receiver input pin for UART0.
	SC3_DAT	I/O	MPF3	SmartCard3 data pin.
	PWM1_4	I/O	MPF4	PWM1_4 output/capture input.
	EBI_AD2	O	MPF7	EBI address/data bus bit 2.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
43	PA.14	I/O	MFP0	General purpose digital I/O pin.
	UART0_TXD	O	MPF1	Data transmitter output pin for UART0.
	SC3_CLK	O	MPF3	SmartCard3 clock pin.
	PWM1_5	I/O	MPF4	PWM1_5 output/capture input.
	EBI_AD3	O	MPF7	EBI address/data bus bit 3.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
44	PA.15	I/O	MFP0	General purpose digital I/O pin.
	SC3_PWR	O	MPF1	SmartCard3 power pin.
	UART2_RTS	O	MPF2	Request to Send output pin for UART2.
	I2C0_SCL	I/O	MPF4	I2C0 clock pin.
	EBI_A21	O	MPF7	EBI address bus bit21.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
45	PC.9	I/O	MFP0	General purpose digital I/O pin.
45	STADC	A	MPF1	ADC analog input.
45	UART2_CTS	I	MPF2	Clear to Send input pin for UART2.
45	SC3_RST	O	MPF3	SmartCard3 reset pin.
45	I2C0_SDA	I/O	MPF4	I2C0 data input/output pin.
45	CAP_DATA1	I	MPF5	Image data input bus bit 1.
45	I2C3_SCL	I/O	MPF6	I2C3 clock pin.
45	EBI_A22	O	MPF7	EBI address bus bit22.
45	SD1_DAT0	I/O	MPF8	SD mode #1 data line bit 0.
45	EBI_A6	O	MPF9	EBI address bus bit6.
45	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
46	PC.10	I/O	MFP0	General purpose digital I/O pin.
46	SC3_CD	I	MPF1	SmartCard3 card detect pin.
46	UART2_RXD	I	MPF2	Data receiver input pin for UART2.
46	PWM0_2	I/O	MPF4	PWM0_2 output/capture input.
46	EBI_A23	O	MPF6	EBI address bus bit23.
46	EBI_AD2	O	MPF7	EBI address/data bus bit 2.
46	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
47	PC.11	I/O	MFP0	General purpose digital I/O pin.
47	UART2_TXD	O	MPF2	Data transmitter output pin for UART2.
47	PWM0_3	I/O	MPF4	PWM0_3 output/capture input.
47	EBI_A24	O	MPF6	EBI address bus bit24.
47	EBI_AD3	O	MPF7	EBI address/data bus bit 3.
47	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
48	LDO_CAP	P	MFP0	LDO output pin. Note: This pin needs to be connected with an external capacitor.
49	V SS	P	MFP0	Ground pin for digital circuit.
50	V DD	P	MFP0	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
51	VRES	A	MFP0	USB PHY VRES ground input pin. Add an 8.2K ohm resistor to VSSA.
52	VBUS	A	MFP0	USB PHY VBUS power input pin.
53	USB_VDD33_CAP	P	MFP0	Internal power regulator output 3.3V decoupling pin. Note: This pin needs to be connected with a 1μF capacitor.
54	VSSA	P	MFP0	Ground pin for digital circuit. Add a Feritte Bead to digital ground V SS .
55	USB0_D-	A	MFP0	USB0 differential signal D-.
56	USB0_D+	A	MFP0	USB0 differential signal D+.
57	USB0_OTG_ID	I	MFP0	USB0 OTG ID pin.
58	PB.0	I/O	MFP0	General purpose digital I/O pin.
58	USB0_OTG5V_ST	I	MPF1	USB0 external VBUS regulator status
58	I2C4_SCL	I/O	MPF2	I2C4 clock pin.
58	INT1	I	MPF8	External interrupt1 input pin.
59	PB.1	I/O	MFP0	General purpose digital I/O pin.
59	USB0_OTG5V_EN	O	MPF1	USB0 external VBUS regulator enable
59	I2C4_SDA	I/O	MPF2	I2C4 data input/output pin.
59	TM1_CNT_OUT	I/O	MPF3	Timer1 event counter input/toggle output.
60	PB.2	I/O	MFP0	General purpose digital I/O pin.
60	UART1_RXD	I	MPF1	Data receiver input pin for UART1.
60	SPI2_SS0	I/O	MPF2	General purpose digital I/O pin.
60	USB1_D-	A	MPF3	USB1 differential signal D-.
60	EBI_AD4	O	MPF7	EBI address/data bus bit 4.
60	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
61	PB.3	I/O	MFP0	General purpose digital I/O pin.
61	UART1_TXD	O	MPF1	Data transmitter output pin for UART1.
61	SPI2_CLK	O	MPF2	SPI2 serial clock pin.
61	USB1_D+	A	MPF3	USB1 differential signal D+.
61	EBI_AD5	O	MPF7	EBI address/data bus bit 5.
61	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
62	PB.4	I/O	MFP0	General purpose digital I/O pin.
62	UART1_RTS	O	MPF1	Request to Send output pin for UART1.
62	SPI2_MISO0	I/O	MPF2	1st SPI2 MISO (Master In, Slave Out) pin.
62	UART4_RXD	I	MPF3	Data receiver input pin for UART4.
62	TM0_CNT_OUT	I/O	MPF4	Timer0 event counter input/toggle output.
62	EBI_AD6	O	MPF7	EBI address/data bus bit 6.
62	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
63	PB.5	I/O	MFP0	General purpose digital I/O pin.
63	UART1_CTS	I	MPF1	Clear to Send input pin for UART1.
63	SPI2_MOSI0	I/O	MPF2	1st SPI2 MOSI (Master Out, Slave In) pin.
63	UART4_TXD	O	MPF3	Data transmitter output pin for UART4.
63	EBI_AD7	O	MPF7	EBI address/data bus bit 7.
63	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
64	PB.6	I/O	MFP0	General purpose digital I/O pin.
64	I2C2_SCL	I/O	MPF1	I2C2 clock pin.
64	BRAKE01	I	MPF2	Brake input pin 1 of EPWMB.
64	UART4_RTS	O	MPF3	Request to Send output pin for UART4.
64	PWM1_4	I/O	MPF4	PWM1_4 output/capture input.
64	EPWM1_0	I/O	MPF5	PWM1_0 output/capture input.
64	EBI_AD8	O	MPF7	EBI address/data bus bit 8.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
65	PB.7	I/O	MFP0	General purpose digital I/O pin.
65	I2C2_SDA	I/O	MPF1	I2C2 data input/output pin.
65	BRAKE00	I	MPF2	Brake input pin 0 of EPWMB.
65	UART4_CTS	I	MPF3	Clear to Send input pin for UART4.
65	PWM1_5	I/O	MPF4	PWM1_5 output/capture input.
65	EPWM1_1	I/O	MPF5	PWM1_1 output/capture input.
65	EBI_AD9	O	MPF7	EBI address/data bus bit 9.
65	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
66	PB.8	I/O	MFP0	General purpose digital I/O pin.
66	UART5_CTS	I	MPF1	Clear to Send input pin for UART5.
66	EPWM1_2	I/O	MPF5	PWM1_2 output/capture input.
66	EBI_AD10	O	MPF7	EBI address/data bus bit 10.
66	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
67	PB.9	I/O	MFP0	General purpose digital I/O pin.
67	UART5_RTS	O	MPF1	Request to Send output pin for UART5.
67	EPWM1_3	I/O	MPF5	PWM1_3 output/capture input.
67	EBI_AD11	O	MPF7	EBI address/data bus bit 11.
67	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
68	PB.10	I/O	MFP0	General purpose digital I/O pin.
68	UART5_TXD	O	MPF1	Data transmitter output pin for UART5.
68	EPWM1_4	I/O	MPF5	PWM1_4 output/capture input.
68	EBI_AD12	O	MPF7	EBI address/data bus bit 12.
68	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
69	PB.11	I/O	MFP0	General purpose digital I/O pin.
69	UART5_RXD	I	MPF1	Data receiver input pin for UART5.
	EPWM1_5	I/O	MPF5	PWM1_5 output/capture input.
	EBI_AD13	O	MPF7	EBI address/data bus bit 13.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
70	PB.12	I/O	MFP0	General purpose digital I/O pin.
70	UART4_RTS	O	MPF1	Request to Send output pin for UART4.
70	SPI2_MISO1	I/O	MPF2	2nd SPI2 MISO (Master In, Slave Out) pin.
70	CAN0_RXD	I	MPF3	CAN bus receiver0 input
70	EMAC_MII_MDC	O	MPF6	MII/RMII Management Data Clock.
70	EBI_AD14	O	MPF7	EBI address/data bus bit 14.
70	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
71	PB.13	I/O	MFP0	General purpose digital I/O pin.
71	UART4_CTS	I	MPF1	Clear to Send input pin for UART4.
71	SPI2_MOSI1	I/O	MPF2	2nd SPI2 MOSI (Master Out, Slave In) pin.
71	CAN0_TXD	I	MPF3	CAN bus transmitter0 input.
71	EMAC_MII_MDIO	I/O	MPF6	MII/RMII Management Data I/O.
71	EBI_AD15	O	MPF7	EBI address/data bus bit 15.
71	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
72	PB.14	I/O	MFP0	General purpose digital I/O pin.
72	I2S1_MCLK	O	MPF1	I2S1 master clock output pin.
72	SC1_RST	O	MPF2	SmartCard1 reset pin.
72	BRAKE01	I	MPF4	Brake input pin 1 of EPWMB.
72	EMAC_MII_MDC	O	MPF6	MII/RMII Management Data Clock.
72	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
73	PB.15	I/O	MFP0	General purpose digital I/O pin.
73	I2S1_DO	O	MPF1	I2S1 data output.
73	SC1_DAT	I/O	MPF2	SmartCard1 data pin.
	BRAKE00	I	MPF4	Brake input pin 0 of EPWMB.
	EMAC_MII_MDIO	I/O	MPF6	MII/RMII Management Data I/O.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
74	V DD	P	MFP0	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
75	PC.0	I/O	MFP0	General purpose digital I/O pin.
75	I2S1_DI	I	MPF1	I2S1 data input.
75	SC1_DAT	I/O	MPF2	SmartCard1 data pin.
75	UART4_RXD	I	MPF3	Data receiver input pin for UART4.
75	EMAC_REFCLK	I	MPF6	EMAC RMII mode clock input
75	EBI_MCLK	O	MPF7	EBI interface clock output pin.
75	INT2	I	MPF8	External interrupt2 input pin.
75	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
76	PC.1	I/O	MFP0	General purpose digital I/O pin.
76	I2S1_BCLK	O	MPF1	I2S1 bit clock pin.
76	SC1_CLK	O	MPF2	SmartCard1 clock pin.
76	UART4_TXD	O	MPF3	Data transmitter output pin for UART4.
76	TM3_CNT_OUT	I/O	MPF5	Timer3 event counter input/toggle output.
76	EMAC_MII_RXERR	I	MPF6	MII/RMII Receive Data error.
76	EBI_AD13	O	MPF7	EBI address/data bus bit 13.
76	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
77	PC.2	I/O	MFP0	General purpose digital I/O pin.
77	I2S1_LRCK	O	MPF1	I2S1 left right channel clock.
77	SC1_PWR	O	MPF2	SmartCard1 power pin.
77	UART4_RTS	O	MPF3	Request to Send output pin for UART4.
77	SPI0_SS0	I/O	MPF4	General purpose digital I/O pin.
77	EMAC_MII_RXDV	I	MPF6	MII Receive Data Valid / RMII CRS_DV Input.
	EBI_AD12	O	MPF7	EBI address/data bus bit 12.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
78	PC.3	I/O	MFP0	General purpose digital I/O pin.
78	I2S1_MCLK	O	MPF1	I2S1 master clock output pin.
78	SC1_CD	I	MPF2	SmartCard1 card detect pin.
78	UART4_CTS	I	MPF3	Clear to Send input pin for UART4.
78	SPI0_MISO1	I/O	MPF4	2nd SPI0 MISO (Master In, Slave Out) pin.
78	QEI0_Z	I	MPF5	Quadrature encoder phase Z input of QEI Unit 0.
78	EMAC_MII_RXD1	I	MPF6	MII/RMII Receive Data Bus Bit 1.
78	EBI_AD11	O	MPF7	EBI address/data bus bit 11.
78	ECAP0_IC2	O	MPF8	Input 2 of enhanced capture unit 0.
78	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
79	PC.4	I/O	MFP0	General purpose digital I/O pin.
79	I2S1_DO	O	MPF1	I2S1 data output.
79	SC1_RST	O	MPF2	SmartCard1 reset pin.
79	SPI0_MOSI1	I/O	MPF4	2nd SPI0 MOSI (Master Out, Slave In) pin.
79	QEI0_B	I	MPF5	Quadrature encoder phase B input of QEI Unit 0.
79	EMAC_MII_RXD0	I	MPF6	MII/RMII Receive Data Bus Bit 0.
79	EBI_AD10	O	MPF7	EBI address/data bus bit 10.
79	ECAP0_IC1	O	MPF8	Input 1 of enhanced capture unit 0.
79	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
80	PC.5	I/O	MFP0	General purpose digital I/O pin.
80	CLKO	O	MFP1	Clock Output Pin.
80	QEI0_A	I	MPF5	Quadrature encoder phase Ainput of QEI Unit 0.
80	EMAC_MII_RXCLK	I	MPF6	MII Receive Clock Input.
80	EBI_MCLK	O	MPF7	EBI interface clock output pin.
80	ECAP0_IC0	O	MPF8	Input 0 of enhanced capture unit 0.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
81	PC.6	I/O	MFP0	General purpose digital I/O pin.
81	TM2_EXT	I	MPF1	Timer2 external counter input
81	SPI0_MISO0	I/O	MPF4	1st SPI0 MISO (Master In, Slave Out) pin.
81	TM2_CNT_OUT	I/O	MPF5	Timer2 event counter input/toggle output.
81	EMAC_MII_TXD0	O	MPF6	MII/RMII Transmit Data Bus bit 0.
81	EBI_AD9	O	MPF7	EBI address/data bus bit 9.
81	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
82	PC.7	I/O	MFP0	General purpose digital I/O pin.
82	TM1_EXT	I	MPF1	Timer1 external counter input
82	SPI0_MOSI0	I/O	MPF4	1st SPI0 MOSI (Master Out, Slave In) pin.
82	EMAC_MII_TXD1	O	MPF6	MII/RMII Transmit Data Bus bit 1.
82	EBI_AD8	O	MPF7	EBI address/data bus bit 8.
82	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
83	PC.8	I/O	MFP0	General purpose digital I/O pin.
83	TM0_EXT	I	MPF1	Timer0 external counter input
83	SPI0_CLK	O	MPF4	SPI0 serial clock pin.
83	EMAC_MII_TXEN	O	MPF6	MII/RMII Transmit Enable.
83	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
84	LDO_CAP	P	MFP0	LDO output pin. Note: This pin needs to be connected with an external capacitor.
85	V SS	P	MFP0	Ground pin for digital circuit.
86	PE.0	I/O	MFP0	General purpose digital I/O pin.
86	ADC0_0	A	MPF1	ADC0 analog input.
86	INT4	I	MPF8	External interrupt4 input pin.
87	PE.1	I/O	MFP0	General purpose digital I/O pin.
	ADC0_1	A	MPF1	ADC0 analog input.
	TM2_CNT_OUT	I/O	MPF3	Timer2 event counter input/toggle output.
88	PE.2	I/O	MFP0	General purpose digital I/O pin.
88	ADC0_2	A	MPF1	ADC0 analog input.
88	ACMP0_O	O	MPF2	Analog comparator0 output .
88	SPI0_MISO0	I/O	MPF3	1st SPI0 MISO (Master In, Slave Out) pin.
88	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
89	PE.3	I/O	MFP0	General purpose digital I/O pin.
89	ADC0_3	A	MPF1	ADC0 analog input.
89	ACMP0_P3	A	MPF2	Analog comparator0 positive input pin.
89	SPI0_MOSI0	I/O	MPF3	1st SPI0 MOSI (Master Out, Slave In) pin.
89	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
90	PE.4	I/O	MFP0	General purpose digital I/O pin.
90	ADC0_4	A	MPF1	ADC0 analog input.
90	ACMP0_P2	A	MPF2	Analog comparator0 positive input pin.
90	SPI0_SS0	I/O	MPF3	General purpose digital I/O pin.
90	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
91	PE.5	I/O	MFP0	General purpose digital I/O pin.
91	ADC0_5	A	MPF1	ADC0 analog input.
91	ACMP0_P1	A	MPF2	Analog comparator0 positive input pin.
91	SPI0_CLK	O	MPF3	SPI0 serial clock pin.
91	SD0_CDn	I	MPF4	SD mode #0 - card detect
91	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
92	PE.6	I/O	MFP0	General purpose digital I/O pin.
92	ADC0_6	A	MPF1	ADC0 analog input.
92	ACMP0_P0	A	MPF2	Analog comparator0 positive input pin.
	SPI0_MISO0	I/O	MPF3	1st SPI0 MISO (Master In, Slave Out) pin.
	SD0_CMD	I/O	MPF4	SD mode #0 - command/response
	EBI_nWR	O	MPF7	EBI write enable output pin.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
93	PE.7	I/O	MFP0	General purpose digital I/O pin.
93	ADC0_7	A	MPF1	ADC0 analog input.
93	ACMP0_N	A	MPF2	Analog comparator0 negative input pin.
93	SPI0_MOSI0	I/O	MPF3	1st SPI0 MOSI (Master Out, Slave In) pin.
93	SD0_CLK	O	MPF4	SD mode #0 - clock.
93	EBI_nRD	O	MPF7	EBI read enable output pin.
93	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
94	AV SS	P	MFP0	Ground pin for digital circuit.
95	V REF	A	MFP0	Voltage reference input for ADC. Note: This pin needs to be connected with 0.1μF/10μF capacitors.
96	AV DD	P	MFP0	Power supply for internal analog circuit.
97	PE.8	I/O	MFP0	General purpose digital I/O pin.
	ADC1_0	A	MPF1	ADC1 analog input.
	ADC0_8	A	MPF1	ADC0 analog input.
	ACMP1_N	A	MPF2	Analog comparator1 negative input pin.
	TM1_CNT_OUT	I/O	MPF3	Timer1 event counter input/toggle output.
	SD0_DAT3	I/O	MPF4	SD mode #0 data line bit 3.
	EBI_ALE	O	MPF7	EBI address latch enable output pin.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
98	PE.9	I/O	MFP0	General purpose digital I/O pin.
98	ADC1_1	A	MPF1	ADC1 analog input.
98	ADC0_9	A	MPF1	ADC0 analog input.
98	ACMP1_P0	A	MPF2	Analog comparator1 positive input pin.
	SD0_DAT2	I/O	MPF4	SD mode #0 data line bit 2.
	EBI_nWRH	O	MPF7	EBI write enable output pin.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
99	PE.10	I/O	MFP0	General purpose digital I/O pin.
	ADC1_2	A	MPF1	ADC1 analog input.
	ADC0_10	A	MPF1	ADC0 analog input.
	ACMP1_P1	A	MPF2	Analog comparator1 positive input pin.
	SPI0_MISO1	I/O	MPF3	2nd SPI0 MISO (Master In, Slave Out) pin.
	SD0_DAT1	I/O	MPF4	SD mode #0 data line bit 1.
	EBI_nWRL	O	MPF7	EBI write enable output pin.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.
100	PE.11	I/O	MFP0	General purpose digital I/O pin.
	ADC1_3	A	MPF1	ADC1 analog input.
	ADC0_11	A	MPF1	ADC0 analog input.
	ACMP1_P2	A	MPF2	Analog comparator1 positive input pin.
	SPI0_MOSI1	I/O	MPF3	2nd SPI0 MOSI (Master Out, Slave In) pin.
	SD0_DAT0	I/O	MPF4	SD mode #0 data line bit 0.
	ACMP2_P3	A	MPF5	Analog comparator2 positive input pin.
	EBI_nCS0	O	MPF7	EBI chip select 0 enable output pin.
	HS		Slew	This pad is embedded with 'Slew Rate Control' capability.

Note:

Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin

( VDD - VSS = 2.5 ~ 5.5 V, TA = 25 )

Symbol	Parameter	Min	Typ	Max	Unit	Test Conditions	Test Conditions
V DD	Operation voltage	2.5	-	5.5	V	V DD = 2.5 V ~ 5.5 V up to 84 MHz	V DD = 2.5 V ~ 5.5 V up to 84 MHz
V SS / AV SS	Power Ground	-0.3	-	-	V
V LDO	LDO Output Voltage	1.62	1.8	1.98	V	V DD ≥ 2.5 V	V DD ≥ 2.5 V
V BG	Band-gap Voltage	1.22	1.25	1.28	V	V DD = 2.5 V ~ 5.5 V, T A = 25	V DD = 2.5 V ~ 5.5 V, T A = 25
V BG	Band-gap Voltage	1.18	1.25	1.32	V	V DD = 2.5 V ~ 5.5 V, T A = -40 ~105	V DD = 2.5 V ~ 5.5 V, T A = -40 ~105
V DD -AV DD	Allowed Voltage Difference for V DD and AV DD	-0.3	0	0.3	V	-	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-			5.5V
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		V DD
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		HIRC	Disable
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-	mA	PLL All digital	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		modules	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		HIRC All digital modules	Disabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	52	-	mA	PLL	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-			Disabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		HXT HIRC	12 MHz Disable
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		All digital	Enabled
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-		modules
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD2	Operating Current Normal Run Mode HCLK = 84 MHz while(1){} Executed from Flash	-	116	-
I DD4		-	50	-	mA	V DD	3.3 V 12 MHz Disabled Enabled
I DD4		-	50	-	mA	HXT
I DD4		-	50	-	mA	HIRC
I DD4		-	50	-	mA	PLL	Disabled
I DD4		-	50	-	mA	All digital modules
		-	32	-	mA	V DD	5.5V
		-	32	-	mA	HXT	Disabled
		-	32	-	mA	HIRC	Enabled
		-	32	-	mA	PLL	Disabled
		-	32	-	mA	All digital modules	Enabled
	Operating Current	-	13	-	mA	.	5.5V
	Operating Current	-	13	-	mA	V DD	Disabled
	Operating Current	-	13	-	mA	HXT HIRC	Enabled
	Operating Current	-	13	-	mA	PLL All digital	Disabled Disabled
	Normal Run Mode HCLK =22.1184 MHz	-	13	-	mA	modules
	while(1){} Executed from Flash	-	32	-	mA	V DD	3.3V
	while(1){} Executed from Flash	-	32	-	mA	HXT	Disabled
	while(1){} Executed from Flash	-	32	-	mA	HIRC	Enabled
	while(1){} Executed from Flash	-	32	-	mA	PLL	Disabled
	while(1){} Executed from Flash	-	32	-	mA	All digital modules	Enabled
	while(1){} Executed from Flash	-	13	-	mA	V DD	3.3V
		-	13	-	mA	HXT	Disabled
		-	13	-	mA	HIRC PLL	Enabled Disabled
		-	13	-	mA	All digital modules	Disabled

					V DD	5.5 V
					HXT HIRC PLL All digital modules	12 MHz Disabled Disabled Enabled
I DD10	-	10	-	mA	V DD	5.5 V
I DD10	-	10	-	mA	HXT	12 MHz
I DD10	-	10	-	mA	HIRC	Disabled
I DD10	-	10	-	mA	PLL	Disabled
I DD10	-	10	-	mA	All digital modules	Disabled
I DD11	-	19	-		V DD	3.3 V
I DD11	-	19	-		HXT	12 MHz
I DD11	-	19	-		HIRC	Disabled
I DD11	-	19	-		PLL	Disabled
I DD11	-	19	-		All digital modules	Enabled
I DD12	-	8.5	-	mA	V DD	3.3 V
I DD12	-	8.5	-	mA	HXT	12 MHz
I DD12	-	8.5	-	mA	HIRC	Disabled
I DD12	-	8.5	-	mA	PLL	Disabled
I DD12	-	8.5	-	mA	All digital modules	Disabled
	-	9			V DD	5.5 V
	-	9			HXT	4 MHz
	-	9			HIRC	Disabled
	-	9			PLL	Disabled
	-	9			All digital modules	Enabled
I DD14	-	5	-		V DD	5.5 V
I DD14	-	5	-		HXT	4 MHz
I DD14	-	5	-		HIRC	Disabled
I DD14	-	5	-		PLL All digital	Disabled
I DD14	-	5	-		modules	Disabled

I DD15		-	7.5	-	mA	V DD HXT HIRC PLL	3.3 V 4 MHz Disabled Disabled
I DD15		-	3.5	-	mA	V DD HXT HIRC PLL All digital modules	3.3 V 4 MHz Disabled Disabled Disabled
I DD15		-	364	-	μA	V DD HXT HIRC LIRC PLL	5.5 V Disabled Disabled Enabled Disabled
	Operating Current Normal Run Mode HCLK = 10 kHz while(1){} Executed from Flash	-	354	-	μA	All digital modules Only enable kHz LIRC clock V DD HXT HIRC LIRC PLL	Enabled modules which support 10 source 5.5 V Disabled Disabled Enabled Disabled
I DD19					V DD HXT HIRC	3.3 V Disabled Disabled	3.3 V Disabled Disabled
			206	-	LIRC	Enabled	Enabled
μA		-			PLL All digital modules Only enable modules which support 10 kHz LIRC clock source V DD HXT HIRC	Disabled Enabled modules Only enable modules which support 10 kHz LIRC clock source 3.3 V Disabled Disabled	Disabled Enabled modules Only enable modules which support 10 kHz LIRC clock source 3.3 V Disabled Disabled
I DD20 μA		-	196	-	LIRC All digital	Enabled Disabled Disabled	Enabled Disabled Disabled
I IDLE1 mA	89 -	-			modules HXT V DD HIRC PLL All digital modules V DD	5.5V 12 MHz Disable Enabled Enabled 5.5V 12 MHz	5.5V 12 MHz Disable Enabled Enabled 5.5V 12 MHz
Operating Current	22 -	-			HIRC	Disabled	Disabled
Idle Mode HCLK = 84 MHz I IDLE2 mA				-	PLL All digital modules All digital modules	Enabled Disabled Enabled	Enabled Disabled Enabled
I IDLE3		87
mA		-				Enabled	Enabled
PLL

					V DD	3.3V	3.3V	3.3V	3.3V	3.3V
I IDLE4					HXT	12 MHz	12 MHz	12 MHz	12 MHz	12 MHz
					HIRC	Disabled	Disabled	Disabled	Disabled	Disabled
		-	21	-	PLL	Enabled	Enabled	Enabled	Enabled	Enabled
					All digital modules	Disabled 5.5V	Disabled 5.5V	Disabled 5.5V	Disabled 5.5V	Disabled 5.5V
Disabled					V DD
			24		HXT HIRC	Enabled	Enabled	Enabled	Enabled	Enabled
I IDLE5		-		-	PLL	Disabled	Disabled	Disabled	Disabled	Disabled
	Operating Current Idle Mode HCLK =22.1184 MHz				All digital modules	Enabled	Enabled	Enabled	Enabled	Enabled
				-	.	5.5V Disabled	5.5V Disabled	5.5V Disabled	5.5V Disabled	5.5V Disabled
			5.5		V DD HXT	Enabled Disabled	Enabled Disabled	Enabled Disabled	Enabled Disabled	Enabled Disabled
I IDLE6		-			PLL All digital modules	Disabled 3.3V	Disabled 3.3V	Disabled 3.3V	Disabled 3.3V	Disabled 3.3V
					HXT	Disabled	Disabled	Disabled	Disabled	Disabled
			23.7	-	HIRC	Enabled	Enabled	Enabled	Enabled	Enabled
I IDLE7 Disabled		-			PLL All digital modules	Enabled	Enabled	Enabled	Enabled	Enabled
3.3V Disabled				-
		-			All digital modules	Disabled Disabled	Disabled Disabled	Disabled Disabled	Disabled Disabled	Disabled Disabled
Enabled			5.3		PLL HIRC

					V DD	5.5 V
					HXT HIRC PLL All digital modules	12 MHz Disabled Disabled Enabled
I IDLE10	-	5.4	-	mA	V DD	5.5 V
I IDLE10	-	5.4	-	mA	HXT	12 MHz
I IDLE10	-	5.4	-	mA	HIRC	Disabled
I IDLE10	-	5.4	-	mA	PLL	Disabled
I IDLE10	-	5.4	-	mA	All digital modules	Disabled
I IDLE11	-	15	-	mA	V DD	3.3 V
I IDLE11	-	15	-	mA	HXT	12 MHz
I IDLE11	-	15	-	mA	HIRC PLL	Disabled Disabled
I IDLE11	-	15	-	mA	All digital
I IDLE11	-	15	-	mA	modules	Enabled
I IDLE12	-	3.8	-	mA	V DD	3.3 V
I IDLE12	-	3.8	-	mA	HXT	12 MHz
I IDLE12	-	3.8	-	mA	HIRC	Disabled
I IDLE12	-	3.8	-	mA	PLL	Disabled
I IDLE12	-	3.8	-	mA	All digital modules	Disabled
I IDLE13	-	7.5	-		V DD	5.5 V
I IDLE13	-	7.5	-		HXT	4 MHz
I IDLE13	-	7.5	-		HIRC	Disabled
I IDLE13	-	7.5	-		PLL	Disabled
I IDLE13	-	7.5	-		All digital modules	Enabled
I IDLE14	-	3.5	-		V DD	5.5 V
I IDLE14	-	3.5	-		HXT	4 MHz
I IDLE14	-	3.5	-		HIRC	Disabled
I IDLE14	-	3.5	-		PLL All digital	Disabled
I IDLE14	-	3.5	-		modules	Disabled

I IDLE15	-	6	mA	V DD	3.3 V 4 MHz Disabled
I IDLE15	-	6	mA	HXT
I IDLE15	-	6	mA	HIRC PLL	Disabled
I IDLE15	-	6	mA	All digital modules	Enabled
I IDLE15	-	6	mA	V DD HXT HIRC PLL All digital modules V DD HXT HIRC LIRC PLL All digital modules Only enable modules which support 10 kHz LIRC clock source V DD HXT HIRC LIRC PLL All digital modules	3.3 V 4 MHz Disabled Disabled Disabled 5.5 V Disabled Disabled Enabled Disabled Enabled Only enable modules which support 10 kHz LIRC clock source 5.5 V Disabled Disabled Enabled Disabled Disabled

			202		μA	V DD	3.3 V Disabled Disabled Enabled Disabled
I IDLE19		-		-		HXT HIRC LIRC All digital	PLL
						modules Enabled Only enable modules which support 10 kHz LIRC clock source V HXT HIRC	modules Enabled Only enable modules which support 10 kHz LIRC clock source DD 3.3 V Disabled Disabled
I					μA		LIRC Enabled
IDLE20		-	192	-		All digital modules	PLL Disabled Disabled
I PWD1 Standby Power-down (Deep Sleep I PWD2	Current Mode Mode)	- -	60 55	-		A V DD = 5.5 V, All oscillators and analog blocks turned off. A V DD = 3.3 V, All oscillators and analog blocks turned off. V DD = 5.5 V, V IN = 0V	A V DD = 5.5 V, All oscillators and analog blocks turned off. A V DD = 3.3 V, All oscillators and analog blocks turned off. V DD = 5.5 V, V IN = 0V
I IL	Logic 0 Input Current (Quasi-bidirectional	-	-65		A
I TL	Mode) Logic 1 to 0 Transition Current	-	-690	-750	A	V DD = 5.5 V, V IN = 2.0V	V DD = 5.5 V, V IN = 2.0V
	(Quasi-bidirectional Mode) [*3]	-2	-	+2	A
I LK	Input Leakage		-	0.8		V DD =	V DD mode
V IL1	Current Input Low Voltage	-0.3 -0.3	-	0.6	V	5.5 V, 0 < V IN < Open-drain or input only	5.5 V, 0 < V IN < Open-drain or input only
	(TTL Input)					V DD = 4.5 V V DD = 2.5 V	V DD = 4.5 V V DD = 2.5 V
V IH1	Input High Voltage /4	2.0	-	V DD + 0.3	V	V DD = 5.5 V	V DD = 5.5 V
	(TTL Input)	1.5	-	V DD + 0.3
V IL3		0	- -	0.8	V	V DD = 3.0 V V DD = 4.5 V	V DD = 3.0 V V DD = 4.5 V
V IH3	Input Low Voltage XTAL1[*2]	0 3.5	- -	0.4 V DD + 0.3		V DD = 2.5 V V V DD = 5.5 V V DD = 3.0 V -	V DD = 2.5 V V V DD = 5.5 V V DD = 3.0 V -
V ILS	Input High Voltage XTAL1[*2]			V DD + 0.3
V IHS	Negative-going Threshold	2.4	-	0.2 V DD	V
	(Schmitt Input), nRST Positive-going	-0.3	-	V DD + 150		-	-
R RST	Internal nRST Pin Pull-up Resistor nRST (Schmitt Input), Threshold	40 DD		0.3	kΩ V	-	-

V ILS	Negative-going Threshold (Schmitt input)	-0.3	-	0.3 V DD	V	-
V IHS	Positive-going Threshold 0.7	V DD -		V DD + 0.3	V	-
I SR11	Source Current (Quasi-bidirectional Mode)	-300	-370	-	A	V DD = 4.5 V, V S = 2.4 V
I SR12	Source Current (Quasi-bidirectional Mode)	-50	-70	-	A	V DD = 2.7 V, V S = 2.2 V
I SR13	Source Current (Quasi-bidirectional Mode)	-40	-60	-	A	V DD = 2.5 V, V S = 2.0 V
I SR21	Source Current (Push-pull Mode)	-20	-25	-	mA	V DD = 4.5 V, V S = 2.4 V
I SR22	Source Current (Push-pull Mode)	-3	-5	-	mA	V DD = 2.7 V, V S = 2.2 V
I SR23	Source Current (Push-pull Mode)	-2.5	-4.5	-	mA	V DD = 2.5 V, V S = 2.0 V
I SK11	Sink Current (Quasi- bidirectional, Open- Drain and Push-pull Mode)	10	15	-	mA	V DD = 4.5 V, V S = 0.45 V
I SK12	Sink Current (Quasi- bidirectional, Open- Drain and Push-pull Mode)	6	9	-	mA	V DD = 2.7 V, V S = 0.45 V
I SK13	Sink Current (Quasi- bidirectional, Open- Drain and Push-pull Mode)	5	8	-	mA	V DD = 2.5 V, V S = 0.45 V

1. nRST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value when VIN approximates to 2V.

Symbol	Parameter	Min	Max	Unit
V DD V SS	DC Power Supply	-0.3	+7.0	V
V BAT	Battery Power Supply	+2.4	+5.0	V
V IN	Input Voltage	V SS - 0.3	V DD + 0.3	V
1/t CLCL	Oscillator Frequency	4	24	MHz
T A	Operating Temperature	-40	+105
T ST	Storage Temperature	-55	+150
I DD	Maximum Current into V DD	-	400	mA
I SS	Maximum Current out of V SS	-	400	mA
I IO	Maximum Current sunk by an I/O pin	-	35	mA
I IO	Maximum Current sourced by an I/O pin	-	35	mA
I IO	Maximum Current sunk by total I/O pins	-	240	mA
I IO	Maximum Current sourced by total I/O pins	-	240	mA

Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life and reliability of the device.

Figure 7.3-1 NUC472 Typical Crystal Application Circuit

Crystal	C1	C2
4 MHz ~ 24 MHz	10~20 pF	10~20 pF