NRF54L15-QFAA-R7
nRF54L15, nRF54L10, and nRF54L05 Wireless SoCs
Manufacturer
Nordic Semiconductor ASA
Overview
Part: nRF54L15, nRF54L10, nRF54L05 from Nordic Semiconductor
Type: Wireless System-on-Chip (SoC)
Key Specs:
- Processor: 128 MHz Arm® Cortex®-M33
- NVM: 500 KB to 1524 KB
- RAM: 96 KB to 256 KB
- Max TX power: 8 dBm (CSP), 7 dBm (QFN)
- RX sensitivity for 1 Mbps Bluetooth LE: -96 dBm
- RX sensitivity for IEEE 802.15.4: -102 dBm
- Supply and GPIO voltage: 1.7 V to 3.6 V
- Operating temperature: -40°C to +105°C
Features:
- Ultra-low power consumption
- Multiprotocol 2.4 GHz radio supporting Bluetooth® LE, 802.15.4-2020, and proprietary 2.4 GHz modes (up to 4 Mbps)
- Integrated 128 MHz Arm® Cortex®-M33 processor with FPU, DSP, MPU, TrustZone
- Integrated 128 MHz RISC-V coprocessor
- Scalable memory configurations
- Advanced security including TrustZone® isolation, tamper detection, and cryptographic engine
- Five serial interfaces (SPI/TWI/UART) including high-speed support
- Extended set of interfaces, peripherals, and timers (Global RTC, 14-bit ADC, I2S, PDM, NFC, PWM, QDEC)
- Single-inductor DC/DC converter
- Single 32 MHz crystal operation, optional 32.768 kHz crystal
Applications:
- Bluetooth® LE with optional Channel Sounding
- 802.15.4-2020 for Thread®, Matter, and Zigbee®
- Proprietary 2.4 GHz modes for higher throughput
Package:
- QFN40 (QDAA): 5.0x5.0 mm with 0.4 mm pitch, 24 GPIO pins
- QFN48 (QFAA): 31 GPIO pins
- QFN52 (QGAA): 6.0x6.0 mm with 0.4 mm pitch, 35 GPIO pins
- CSP47 (CAAA) (for nRF54L15): 2.4x2.2 mm with 0.3 mm pitch, 32 GPIO pins
Features
- 128 MHz Arm® Cortex®-M33 processor
- Scalable memory configurations from 500 KB up to 1524 KB NVM and 96 KB up to 256 KB RAM
- Multiprotocol 2.4 GHz radio supporting Bluetooth® LE, 802.15.4-2020, and 2.4 GHz proprietary modes (up to 4 Mbps)
- Five serial interfaces (SPI/TWI/UART) including high-speed support
- Extended set of interfaces, peripherals, and timers including Global RTC available in System OFF, 14-bit ADC, I 2S, PDM, NFC, PWM, and QDEC
- 128 MHz RISC-V coprocessor
- Advanced security including TrustZone® isolation, tamper detection, and cryptographic engine with side-channel leakage protection
- Ultra-compact CSP and QFN packages
Pin Configuration
The GPIO port peripheral implements up to 32 pins, PIN[n] (n = 0..31), that can be individually configured in the PIN_CNF[n] registers (n=0..31).
The following parameters can be enabled or configured in these registers:
- Direction
- Drive strength
- Pull-up and pull-down resistors
- Pin sensing
- Input buffer disconnect
- Analog input (for selected pins)
All write-capable registers are retained registers. See POWER — Power control on page 92 for more information.
When not used as an input, disconnect the input buffer of the GPIO pin to save power. An input must be connected to get a valid value in the IN register and for the sense mechanism to have access to the pin.
Other peripherals in the system can connect to GPIO pins to override their output value, override their configuration, or read their analog or digital input value.
Selected pins also support analog input signals (ANAIN). The assignment of the analog pins can be found in Pin assignments on page 859.
GPIO drive strength is configured using the DRIVE0 and DRIVE1 fields of register PIN\_CNF[n] (n=0..31) (Retained) on page 284. Some pins may not support every drive configuration, see Pin assignments on page 859 for more information.
When a pin is configured as digital input, it is important to minimize increased current consumption when the input voltage is between VIL and VIH. It is a good practice to ensure that the external circuitry does not drive the pin to levels between VIL and VIH for a long period of time.
For more information on pin assignment and the corresponding effect of read and write operations of GPIO registers, see Peripheral and subsystem assignment on page 277.
Note: NFCT uses two pins to connect to the antenna, which are shared with GPIOs. NFC pins are enabled from reset. To use them as GPIO pins, NFC use must be disabled using register PADCONFIG on page 398. For more details, see NFCT — Near field communication tag on page 359.
Electrical Characteristics
uint8_t sample_ed(void) { int val; NRF_RADIO->TASKS_EDSTART = 1; // Start while (NRF_RADIO->EVENTS_EDEND != 1) { // CPU can sleep here or do something else // Use of interrupts are encouraged } val = NRF_RADIO->EDSAMPLE * ED_RSSISCALE; // Read level return (uint8_t)(val>255 ? 255 : val); // Convert to IEEE 802.15.4 scale }
For scaling between hardware value and dBm, see [Clear channel assessment \(CCA\)](#page-478-0) on page 479.
The mlme-scan.reqprimitive of the MAC layer uses the ED measurement to detect channels where there might be wireless activity. To assist this primitive, a tailored mode of operation is available where the ED measurement runs for a defined number of iterations keeping track of the maximum ED level. This is engaged by writing the EDCNT field of the [EDCTRL](#page-529-0) register to a value different from 0, where it will run the specified number of iterations and report the maximum energy measurement in the [EDSAMPLE](#page-530-0) register. The scan is started with the [EDSTART](#page-491-0) task and the end indicated with the [EDEND](#page-502-0) event. This significantly reduces the interrupt frequency and therefore power consumption. The following figure shows how the ED measurement will operate depending on the EDCNT and EDPERIOD fields of the [EDCTRL](#page-529-0) register.
*Figure 125: Energy detection measurement for a single iteration (EDCNT = 0)*
*Figure 126: Energy detection measurement example with multiple iterations*
The scan is stopped by writing the [EDSTOP](#page-491-1) task. It is followed by the [EDSTOPPED](#page-502-1) event when the module has terminated.
#### <span id="page-478-0"></span>8.17.12.4 Clear channel assessment (CCA)
IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when transmitting. This is known as carrier sense multiple access with collision avoidance (CSMA-CA). The key part of this method is measuring if the wireless medium is busy or not.
The following clear channel assessment modes are supported:
• CCA Mode 1 (energy above threshold) – The medium is reported busy upon detecting any energy above the ED threshold.
- CCA Mode 2 (carrier sense only) The medium is reported busy upon detection of a signal compliant with IEEE 802.15.4 with the same modulation and spreading characteristics.
- CCA Mode 3 (carrier sense with energy above threshold) The medium is reported busy using a logical combination (AND/OR) between the results from CCA Mode 1 and CCA Mode 2.
The clear channel assessment should survey a period equal to 8 symbols or 128 μs.
RADIO must be in RX mode and be able to receive correct packets when performing the CCA. The shortcut between [READY](#page-498-0) and [START](#page-489-2) must be disabled if baseband processing is not to be performed while the measurement is running.
Register [EDSAMPLE](#page-530-0) on page 531 is updated at the end of the clear channel assessment and can be used to read the energy level measured during the procedure. For [CCACTRL.CCAMODE](#page-530-1) = EdModeEdModeTest1, [EDSAMPLE](#page-530-0) holds the first ED measurement. For the other CCA modes, [EDSAMPLE](#page-530-0) holds the average ED value.
#### CCA Mode 1
CCA Mode 1 is enabled by first configuring the field [CCACTRL.CCAMODE](#page-530-1) = EdMode and writing the [CCACTRL.CCAEDTHRES](#page-530-1) field to a chosen value. Once the [CCASTART](#page-491-2) task is written, RADIO will perform an ED measurement for 8 symbols and compare the measured level with that found in the [CCACTRL.CCAEDTHRES](#page-530-1) field. If the measured value is higher than or equal to this threshold, the [CCABUSY](#page-503-0) event is generated. If the measured level is less than the threshold, the [CCAIDLE](#page-502-2) event is generated.
#### CCA Mode 2
CCA Mode 2 is enabled by configuring the field [CCACTRL.CCAMODE](#page-530-1) = CarrierMode. RADIO will sample to see if a valid SFD is found during the 8 symbols. If a valid SFD is detected, the [CCABUSY](#page-503-0) event is generated and the device should not send any data. The [CCABUSY](#page-503-0) event is also generated if the scan was performed during an ongoing frame reception. If the measurement period completes with no SFD detection, the [CCAIDLE](#page-502-2) event is generated. When [CCACTRL.CCACORRCNT](#page-530-1) is not zero, the algorithm will look at the correlator output in addition to the SFD detection signal. If an SFD is reported during the scan period, it will terminate immediately indicating busy medium. Similarly, if the number of peaks above [CCACTRL.CCACORRTHRES](#page-530-1) crosses the [CCACTRL.CCACORRCNT](#page-530-1), the [CCACTRL.CCABUSY](#page-530-1) event is generated. If less than [CCACORRCOUNT](#page-530-1) crossings are found and no SFD is reported, the [CCAIDLE](#page-502-2) event will be generated and the device can send data.
#### CCA Mode 3
CCA Mode 3 is enabled by configuring [CCACTRL.CCAMODE](#page-530-1) = CarrierAndEdMode or [CCACTRL.CCAMODE](#page-530-1) = CarrierOrEdMode and performing the required logical combination of the result from CCA Mode 1 and CCA Mode 2. The [CCABUSY](#page-503-0) or [CCAIDLE](#page-502-2) events are generated by ANDing or ORing the energy above threshold and carrier detection scans.
#### Shortcuts
An ongoing CCA can be stopped by issuing the [CCASTOP](#page-491-3) task. This will trigger the associated [CCASTOPPED](#page-503-1) event.
For CCA mode automation, the following shortcuts are available:
- To automatically switch between RX mode (when performing the CCA) and to TX mode where the packet is sent, the shortcut between [CCAIDLE](#page-502-2) and [TXEN](#page-489-1), in conjunction with the short between [CCAIDLE](#page-502-2) and [STOP,](#page-489-3) must be used.
- To automatically disable RADIO whenever the CCA reports a busy medium, the shortcut between [CCABUSY](#page-503-0) and [DISABLE](#page-490-0) can be used.
• To immediately start a CCA after ramping up into RX mode, the shortcut between [RXREADY](#page-498-1) and [CCASTART](#page-491-2) can be used.
#### Conversion
The conversion from a CCAEDTHRES, LQI, or EDSAMPLE value to dBm can be done with the following equation, where VALHARDWARE is either CCAEDTHRES, LQI, or EDSAMPLE. LQI and EDSAMPLE are hardwarereported values, while CCAEDTHRES is set by software. Constants ED\_RSSISCALE and ED\_RSSIOFFS are from the electrical specifications.
PRF[dBm] = ED_RSSIOFFS + VALHARDWARE
The ED\_RSSISCALE constant is used to calculate power in 802.15.4 units (0-255), using the following formula:
PRF[802.15.4 units] = MIN( ED_RSSISCALE x VALHARDWARE, 255 )
#### 8.17.12.5 Cyclic redundancy check (CRC)
IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MAC header (MHR) and MAC service data unit (MSDU).
The standard defines the following generator polynomial:
$G(x) = x<sup>16</sup> + x<sup>12</sup> + x<sup>5</sup> + 1$
In RX mode, RADIO will trigger the CRC module when the first octet after the frame length (PHR) is received. The CRC will then update on each consecutive octet received. When a complete frame is received, the [CRCSTATUS](#page-540-2) register will be updated accordingly and the [CRCOK](#page-501-0) or [CRCERROR](#page-501-1) events will be generated. When the CRC module is enabled, it will not write the two last octets (CRC) to the frame RAM. When transmitting, the CRC will be computed on the fly, starting with the first octet after PHR, and inserted as the two last octets in the frame. The EasyDMA will fetch the frame length minus 2 octets from RAM and insert the CRC octets at their correct positions in the frame.
The following code shows how to configure the CRC module for correct operation when in IEEE 802.15.4 mode. The [CRCCNF](#page-544-1) is written to 16-bit CRC and the [CRCPOLY](#page-544-2) is written to 0x11021. The start value used by IEEE 802.15.4 is 0 and [CRCINIT](#page-545-0) is configured to reflect this.
/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/ NRF_RADIO->CRCCNF = ((RADIO_CRCCNF_SKIPADDR_Ieee802154 << RADIO_CRCCNF_SKIPADDR_Pos) | (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos)); NRF_RADIO->CRCPOLY = 0x11021; NRF_RADIO->CRCINIT = 0;
The ENDIANESS subregister must be set to little-endian since the FCS field is transmitted from the left bit to the right bit.
#### 8.17.12.6 Transmit sequence
The transmission is started by first putting RADIO in RX mode and triggering the [RXEN](#page-489-0) task .
An outline of the IEEE 802.15.4 transmission is illustrated in the following figure.
Figure 127: IEEE 802.15.4 transmit sequence
The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving the READY event, the CCA is started by triggering the CCASTART task. The chosen mode of assessment (register CCACTRL.CCAMODE) will be performed and signal the CCAIDLE event or CCABUSY event 128 μs later. If the event CCABUSY is received, RADIO will have to retry the CCA after a specific back-off period. This is outlined in the IEEE 802.15.4 standard, Figure 69 in section 7.5.1.4 The CSMA-CA algorithm.
If the event CCAIDLE is generated, a write to the task register TXEN enters RADIO in TXRU state. The READY event will be generated when RADIO is in the TXIDLE state and ready to transmit. With the PACKETPTR pointing to the length (PHR) field of the frame, the START task can be written. RADIO will send the four octet preamble sequence followed by the start of frame delimiter (register SFD). The first byte read from RAM is the length field (PHR) followed by the transmission of the number of bytes indicated as the frame length. If the CRC module is configured, it will run for PHR-2 octets. The last two octets will be substituted with the results from running the CRC. The necessary CRC parameters are sampled on the START task. The FCS field of the frame is little endian.
In addition to the available shortcuts, one is provided between the READY event and the CCASTART task so that a CCA can automatically start when the receiver is ready. A second shortcut has been added between the CCAIDLE event and the TXEN task, when a clear channel is detected, RADIO can immediately enter TX mode.
#### 8.17.12.7 Receive sequence
RADIO must be in RX mode before the receive sequence can begin. After writing to the RXEN task, RADIO will start ramping up and enter the RXRU state.
When the READY event is generated, RADIO enters the RXIDLE mode. For the baseband processing to be enabled, the START task must be written. An outline of the IEEE 802.15.4 receive sequence can be found in the following figure.
*Figure 128: IEEE 802.15.4 receive sequence*
When a valid SHR is received, RADIO will start storing future octets (starting with PHR) to the data memory pointed to by [PACKETPTR](#page-548-0). After the SFD octet is received, the [FRAMESTART](#page-499-3) event is generated. If the CRC module is enabled, it will start updating with the second byte received (first byte in payload) and run for the full frame length. The two last bytes in the frame are not written to RAM when CRC is configured. However, if the result of the CRC is zero after running the full frame, the [CRCOK](#page-501-0) event will be generated. The [END](#page-499-2) event is generated when the last octet has been received and is available in data memory.
When a packet is received, a link quality indicator (LQI) is generated and appended immediately after the last received octet. When using an IEEE 802.15.4 compliant frame, this will be just after the MSDU since the FCS is not reported. In the case of a non-compliant frame, it will be appended after the full frame. The LQI reported by the hardware must be converted to the IEEE 802.15.4 range by an 8-bit saturating multiplication of 4, as shown in [IEEE 802.15.4 ED measurement example](#page-478-1) on page 479. The LQI is only valid for frames equal to, or longer than, three octets. When receiving a frame, the RSSI (reported as negative dB) will be measured at three points during the reception. These three values will be sorted with the middle value selected (median 3) to be remapped within the LQI range. The following figure illustrates the LQI measurement and how the data is arranged in data memory.
#### PHY protocol data unit (PPDU) Preamble sequence SFD Length PHY payload 5 octets synchronization header (SHR) 1 octet (PHR) Maximum 127 octets (PSDU) MAC protocol data unit (MPDU) Length PHY payload 1 octet (PHR) Maximum 127 octets (PSDU) MAC protocol data unit (MPDU) On air frame In RAM frame LQI 1 octet Omitted if CRC enabled FCF 2 octets Median 3 160 μs 32 μs ≤4064 μs RSSI RSSI RSSI
*Figure 129: IEEE 802.15.4 frame in data memory*
A shortcut has been added between the [FRAMESTART](#page-499-3) event and the [BCSTART](#page-490-2) task. This can be used to trigger a [BCMATCH](#page-501-2) event after N bits, such as when inspecting the MAC addressing fields.
#### 8.17.12.8 Interframe spacing (IFS)
IEEE 802.15.4 defines a specific time that is allotted for the MAC sublayer to process received data. The interframe spacing (IFS) is used to prevent two frames from being transmitted too close together. If the transmission is requesting an acknowledgement, the space before the second frame must be at least one IFS period.
IFS is determined to be one of the following:
- IFS = macMinSIFSPeriod (12 symbols) if MPDU ≤ aMaxSIFSFrameSize (18 octets) octets
- IFS = macMinLIFSPeriod (40 symbols) if MPDU > aMaxSIFSFrameSize
Using the efficient assisted modes in RADIO, the [TIFS](#page-534-1) will be programmed with the correct value based on the frame being transmitted. If the assisted modes are not in use, the [TIFS](#page-534-1) register must be updated manually. The following figure shows what IFS period is valid in both acknowledged and unacknowledged transmissions.
#### Acknowledged transmission
#### Unacknowledged transmission
*Figure 130: Interframe spacing examples*
## <span id="page-484-0"></span>8.17.13 EasyDMA
RADIO uses EasyDMA to read and write packets to RAM without CPU involvement.
As illustrated in [RADIO block diagram](#page-464-1) on page 465, the RADIO peripheral's EasyDMA utilizes the same [PACKETPTR](#page-548-0) for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before RADIO is started by the [START](#page-489-2) task. The [PACKETPTR](#page-548-0) register is double-buffered, meaning that it can be updated and prepared for the next transmission.
The [END](#page-499-2) event indicates that the last bit has been processed by RADIO. The [DISABLED](#page-500-1) event is issued to acknowledge that the [DISABLE](#page-490-0) task is done.
The structure of a packet is described in detail in [Packet configuration](#page-464-2) on page 465. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:
- S0
- LENGTH
- S1
- PAYLOAD
In addition, a static add-on is sent immediately after the payload.
The size of each of the listed fields in the frame is configurable (see [Packet configuration](#page-464-2) on page 465), and the space occupied in RAM depends on these settings. The size of the field can be zero, as long as the resulting frame complies with the chosen RF protocol.
All fields are extended in size to align with a byte boundary in RAM. For instance, a 3-bit long field on-air will occupy 1 byte in RAM while a 9-bit long field will be extended to 2 bytes.
The packet's elements can be configured as follows:
- CI, TERM1, and TERM2 fields are only present in Bluetooth Low Energy Long Range mode
- S0 is configured through the field [PCNF0.S0LEN](#page-541-0)
- LENGTH is configured through the field [PCNF0.LFLEN](#page-541-0)
- S1 is configured through the field [PCNF0.S1LEN](#page-541-0)
- Payload size is configured through the value in RAM corresponding to the LENGTH field
- Static add-on size is configured through the field [PCNF1.STATLEN](#page-542-0)
The [PCNF1.MAXLEN](#page-542-0) field configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by RADIO. This feature can be used to ensure that RADIO does not overwrite or read beyond the RAM assigned to the packet payload. This means that if the LENGTH
field of the packet payload exceeds [PCNF1.STATLEN,](#page-542-0) and the LENGTH field in the packet specifies a packet larger than configured in [PCNF1.MAXLEN](#page-542-0), the payload will be truncated to the length specified in [PCNF1.MAXLEN](#page-542-0).
**Note:** The [PCNF1.MAXLEN](#page-542-0) field includes the payload and the add-on, but excludes the size occupied by the S0, LENGTH, and S1 fields. This has to be taken into account when allocating RAM.
If the payload and add-on length is specified larger than [PCNF1.MAXLEN,](#page-542-0) RADIO will transmit or receive in the same way as before, except the payload is now truncated to [PCNF1.MAXLEN](#page-542-0). The packet's LENGTH field will not be altered when the payload is truncated. RADIO will calculate CRC as if the packet length is equal to [PCNF1.MAXLEN.](#page-542-0)
**Note:** If [PACKETPTR](#page-548-0) is not pointing to the RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See [Memory](#page-12-1) on page 13 for more information about the different memory regions.
The [END](#page-499-2) event indicates that the last bit has been processed by RADIO. The [DISABLED](#page-500-1) event is issued to acknowledge that the [DISABLE](#page-490-0) task is done.
## <span id="page-485-0"></span>8.17.14 Registers
#### Instances
| Instance | Domain | Base address | TrustZone | | | Split | Description |
| ------------------------- | -------- | -------------------------- | ----------- | ----- | ----- | -------- | ------------------------------------- |
| | | | Map | Att | DMA | access | |
| | | | | | | | 2.4 GHz radio RADIO |
| RADIO : S<br>RADIO : NS | GLOBAL | 0x5008A000<br>0x4008A000 | US | S | SA | No | See pinout for GPIO options for DFE |
| | | | | | | | antenna switch control |
#### Configuration
| Instance | Domain | Configuration |
| ------------ | -------- | ------------------------------------------------------------ |
| RADIO : S | | For the PSEL registers, use only dedicated pins on port P1 |
| RADIO : NS | GLOBAL | No internal instantiation of DmaChannelPeripheral |
#### Register overview
| Register | Offset | TZ | Description |
| ----------------------- | -------- | ---- | -------------------------------------------------------------------------- |
| TASKS_TXEN | 0x000 | | Enable RADIO in TX mode |
| TASKS_RXEN | 0x004 | | Enable RADIO in RX mode |
| TASKS_START | 0x008 | | Start RADIO |
| TASKS_STOP | 0x00C | | Stop RADIO |
| TASKS_DISABLE | 0x010 | | Disable RADIO |
| TASKS_RSSISTART | 0x014 | | Start the RSSI and take one single sample of the receive signal strength |
| TASKS_BCSTART | 0x018 | | Start the bit counter |
| TASKS_BCSTOP | 0x01C | | Stop the bit counter |
| TASKS_EDSTART | 0x020 | | Start the energy detect measurement used in IEEE 802.15.4 mode |
| TASKS_EDSTOP | 0x024 | | Stop the energy detect measurement |
| TASKS_CCASTART | 0x028 | | Start the clear channel assessment used in IEEE 802.15.4 mode |
| TASKS_CCASTOP | 0x02C | | Stop the clear channel assessment |
| TASKS_AUXDATADMASTART | 0x038 | | Start DMA transaction of acquisition |
| Register | Offset | TZ | Description |
| --------------------------- | -------- | ---- | --------------------------------------------------------------------------------------- |
| TASKS_AUXDATADMASTOP | 0x03C | | Stop ongoing DMA transaction of acquisition |
| TASKS_PLLEN | 0x06C | | Enable RADIO in PLL mode (standby for either TX or RX) |
| TASKS_CSTONESSTART | 0x0A0 | | Start tone processing for channel sounding |
| TASKS_SOFTRESET | 0x0A4 | | Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/ |
| | | | SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. |
| SUBSCRIBE_TXEN | 0x100 | | Subscribe configuration for task TXEN |
| SUBSCRIBE_RXEN | 0x104 | | Subscribe configuration for task RXEN |
| SUBSCRIBE_START | 0x108 | | Subscribe configuration for task START |
| SUBSCRIBE_STOP | 0x10C | | Subscribe configuration for task STOP |
| SUBSCRIBE_DISABLE | 0x110 | | Subscribe configuration for task DISABLE |
| SUBSCRIBE_RSSISTART | 0x114 | | Subscribe configuration for task RSSISTART |
| SUBSCRIBE_BCSTART | 0x118 | | Subscribe configuration for task BCSTART |
| SUBSCRIBE_BCSTOP | 0x11C | | Subscribe configuration for task BCSTOP |
| SUBSCRIBE_EDSTART | 0x120 | | Subscribe configuration for task EDSTART |
| SUBSCRIBE_EDSTOP | 0x124 | | Subscribe configuration for task EDSTOP |
| SUBSCRIBE_CCASTART | 0x128 | | Subscribe configuration for task CCASTART |
| SUBSCRIBE_CCASTOP | 0x12C | | Subscribe configuration for task CCASTOP |
| SUBSCRIBE_AUXDATADMASTART | 0x138 | | Subscribe configuration for task AUXDATADMASTART |
| SUBSCRIBE_AUXDATADMASTOP | 0x13C | | Subscribe configuration for task AUXDATADMASTOP |
| SUBSCRIBE_PLLEN | 0x16C | | Subscribe configuration for task PLLEN |
| SUBSCRIBE_CSTONESSTART | 0x1A0 | | Subscribe configuration for task CSTONESSTART |
| SUBSCRIBE_SOFTRESET | 0x1A4 | | Subscribe configuration for task SOFTRESET |
| EVENTS_READY | 0x200 | | RADIO has ramped up and is ready to be started |
| EVENTS_TXREADY | 0x204 | | RADIO has ramped up and is ready to be started TX path |
| EVENTS_RXREADY | 0x208 | | RADIO has ramped up and is ready to be started RX path |
| EVENTS_ADDRESS | 0x20C | | Address sent or received |
| EVENTS_FRAMESTART | 0x210 | | IEEE 802.15.4 length field received |
| EVENTS_PAYLOAD | 0x214 | | Packet payload sent or received |
| EVENTS_END | 0x218 | | Memory access for packet data has been completed |
| EVENTS_PHYEND | 0x21C | | The last bit is sent on air or last bit is received |
| EVENTS_DISABLED | 0x220 | | RADIO has been disabled |
| EVENTS_DEVMATCH | 0x224 | | A device address match occurred on the last received packet |
| EVENTS_DEVMISS | 0x228 | | No device address match occurred on the last received packet |
| EVENTS_CRCOK | 0x22C | | Packet received with CRC ok |
| EVENTS_CRCERROR | 0x230 | | Packet received with CRC error |
| EVENTS_BCMATCH | 0x238 | | Bit counter reached bit count value |
| EVENTS_EDEND | 0x23C | | Sampling of energy detection complete (a new ED sample is ready for readout from the |
| | | | RADIO.EDSAMPLE register) |
| EVENTS_EDSTOPPED | 0x240 | | The sampling of energy detection has stopped |
| EVENTS_CCAIDLE | 0x244 | | Wireless medium in idle - clear to send |
| EVENTS_CCABUSY | 0x248 | | Wireless medium busy - do not send |
| EVENTS_CCASTOPPED | 0x24C | | The CCA has stopped |
| EVENTS_RATEBOOST | 0x250 | | Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit |
| EVENTS_MHRMATCH | 0x254 | | MAC header match found |
| EVENTS_SYNC | 0x258 | | Initial sync detected |
| EVENTS_CTEPRESENT | 0x25C | | CTEInfo byte is received |
| EVENTS_PLLREADY | 0x2B0 | | PLL has settled and RADIO is ready to be enabled in either TX or RX mode |
| EVENTS_RXADDRESS | 0x2BC | | Address received |
| EVENTS_AUXDATADMAEND | 0x2C0 | | AUXDATA DMA end |
| EVENTS_CSTONESEND | 0x2C8 | | The channel sounding tone processing is complete |
| PUBLISH_READY | 0x300 | | Publish configuration for event READY |
| PUBLISH_TXREADY | 0x304 | | Publish configuration for event TXREADY |
| PUBLISH_RXREADY | 0x308 | | Publish configuration for event RXREADY |
| PUBLISH_ADDRESS<br>0x30C<br>Publish configuration for event ADDRESS<br>PUBLISH_FRAMESTART<br>0x310<br>Publish configuration for event FRAMESTART<br>PUBLISH_PAYLOAD<br>0x314<br>Publish configuration for event PAYLOAD<br>PUBLISH_END<br>0x318<br>Publish configuration for event END<br>PUBLISH_PHYEND<br>0x31C<br>Publish configuration for event PHYEND<br>PUBLISH_DISABLED<br>0x320<br>Publish configuration for event DISABLED<br>PUBLISH_DEVMATCH<br>0x324<br>Publish configuration for event DEVMATCH<br>PUBLISH_DEVMISS<br>0x328<br>Publish configuration for event DEVMISS<br>PUBLISH_CRCOK<br>0x32C<br>Publish configuration for event CRCOK<br>PUBLISH_CRCERROR<br>0x330<br>Publish configuration for event CRCERROR<br>PUBLISH_BCMATCH<br>0x338<br>Publish configuration for event BCMATCH<br>PUBLISH_EDEND<br>0x33C<br>Publish configuration for event EDEND<br>PUBLISH_EDSTOPPED<br>0x340<br>Publish configuration for event EDSTOPPED<br>PUBLISH_CCAIDLE<br>0x344<br>Publish configuration for event CCAIDLE<br>PUBLISH_CCABUSY<br>0x348<br>Publish configuration for event CCABUSY<br>PUBLISH_CCASTOPPED<br>0x34C<br>Publish configuration for event CCASTOPPED<br>PUBLISH_RATEBOOST<br>0x350<br>Publish configuration for event RATEBOOST<br>PUBLISH_MHRMATCH<br>0x354<br>Publish configuration for event MHRMATCH<br>PUBLISH_SYNC<br>0x358<br>Publish configuration for event SYNC<br>PUBLISH_CTEPRESENT<br>0x35C<br>Publish configuration for event CTEPRESENT<br>PUBLISH_PLLREADY<br>0x3B0<br>Publish configuration for event PLLREADY<br>PUBLISH_RXADDRESS<br>0x3BC<br>Publish configuration for event RXADDRESS<br>PUBLISH_AUXDATADMAEND<br>0x3C0<br>Publish configuration for event AUXDATADMAEND<br>PUBLISH_CSTONESEND<br>0x3C8<br>Publish configuration for event CSTONESEND<br>SHORTS<br>0x400<br>Shortcuts between local events and tasks<br>INTENSET00<br>0x488<br>Enable interrupt<br>INTENSET01<br>0x48C<br>Enable interrupt<br>INTENCLR00<br>0x490<br>Disable interrupt<br>INTENCLR01<br>0x494<br>Disable interrupt<br>INTENSET10<br>0x4A8<br>Enable interrupt<br>INTENSET11<br>0x4AC<br>Enable interrupt<br>INTENCLR10<br>0x4B0<br>Disable interrupt<br>INTENCLR11<br>0x4B4<br>Disable interrupt<br>MODE<br>0x500<br>Data rate and modulation<br>PHYENDTXDELAY<br>0x518<br>Configurable delay of PHYEND event for TX<br>STATE<br>0x520<br>Current radio state<br>EDCTRL<br>0x530<br>IEEE 802.15.4 energy detect control<br>EDSAMPLE<br>0x534<br>IEEE 802.15.4 energy detect level<br>CCACTRL<br>0x538<br>IEEE 802.15.4 clear channel assessment control<br>DATAWHITE<br>0x540<br>Data whitening configuration<br>AUXDATA.CNF[n]<br>0x548<br>AUXDATA configuration<br>AUXDATADMA[n].ENABLE<br>0x550<br>Enable or disable data acquisition<br>AUXDATADMA[n].PTR<br>0x554<br>ACQ DMA pointer<br>AUXDATADMA[n].MAXCNT<br>0x558<br>Maximum number of 32-bit words to transfer<br>AUXDATADMA[n].AMOUNT<br>0x55C<br>Number of 32-bit words transferred in the last transaction<br>TIMING<br>0x704<br>Timing<br>FREQUENCY<br>0x708<br>Frequency<br>TXPOWER<br>0x710<br>Output power<br>TIFS<br>0x714<br>Interframe spacing in μs<br>RSSISAMPLE<br>0x718<br>RSSI sample<br>RXGAIN.CONFIG<br>0x7D4<br>Override configuration of receiver gain control loop<br>FREQFINETUNE<br>0x0804<br>Fine tuning of the RF frequency<br>FECONFIG<br>0x908<br>Config register | Register | Offset<br>TZ | Description |
| ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ---------- | -------------- | ------------- |
| Register | Offset | TZ | Description |
| ------------------------- | -------- | ---- | --------------------------------------------------------------------------------- |
| CFO_STAT | 0xB00 | | Carrier freq. offset estimate |
| DBCCORR | 0xB40 | | Correlator thresholds |
| DFEMODE | 0xD00 | | Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) |
| DFESTATUS | 0xD04 | | DFE status information |
| DFECTRL1 | 0xD10 | | Various configuration for Direction finding |
| DFECTRL2 | 0xD14 | | Start offset for Direction finding |
| SWITCHPATTERN | 0xD28 | | GPIO patterns to be used for each antenna |
| CLEARPATTERN | 0xD2C | | Clear the GPIO pattern array for antenna control |
| PSEL.DFEGPIO[n] | 0xD30 | | Pin select for DFE pin n |
| DFEPACKET.PTR | 0xD50 | | Data pointer |
| DFEPACKET.MAXCNT | 0xD54 | | Maximum number of bytes to transfer |
| DFEPACKET.AMOUNT | 0xD58 | | Number of bytes transferred in the last transaction |
| DFEPACKET.CURRENTAMOUNT | 0xD5C | | Number of bytes transferred in the current transaction |
| CRCSTATUS | 0xE0C | | CRC status |
| RXMATCH | 0xE10 | | Received address |
| RXCRC | 0xE14 | | CRC field of previously received packet |
| DAI | 0xE18 | | Device address match index |
| PDUSTAT | 0xE1C | | Payload status |
| PCNF0 | 0xE20 | | Packet configuration register 0 |
| PCNF1 | 0xE28 | | Packet configuration register 1 |
| BASE0 | 0xE2C | | Base address 0 |
| BASE1 | 0xE30 | | Base address 1 |
| PREFIX0 | 0xE34 | | Prefixes bytes for logical addresses 0-3 |
| PREFIX1 | 0xE38 | | Prefixes bytes for logical addresses 4-7 |
| TXADDRESS | 0xE3C | | Transmit address select |
| RXADDRESSES | 0xE40 | | Receive address select |
| CRCCNF | 0xE44 | | CRC configuration |
| CRCPOLY | 0xE48 | | CRC polynomial |
| CRCINIT | 0xE4C | | CRC initial value |
| DAB[n] | 0xE50 | | Device address base segment n |
| DAP[n] | 0xE70 | | Device address prefix n |
| DACNF | 0xE90 | | Device address match configuration |
| BCC | 0xE94 | | Bit counter compare |
| CTESTATUS | 0xEA4 | | CTEInfo parsed from received packet |
| MHRMATCHCONF | 0xEB4 | | Search pattern configuration |
| MHRMATCHMASK | 0xEB8 | | Pattern mask |
| SFD | 0xEBC | | IEEE 802.15.4 start of frame delimiter |
| CTEINLINECONF | 0xEC0 | | Configuration for CTE inline mode |
| PACKETPTR | 0xED0 | | Packet pointer |
| CSTONES.MODE | 0x1000 | | Selects the mode(s) that are activated on the start signal |
| CSTONES.NUMSAMPLES | 0x1004 | | Number of input samples at 2MHz sample rate |
| CSTONES.NEXTFREQUENCY | 0x1008 | | The value of FREQUENCY that will be used in the next step |
| CSTONES.FAEPEER | 0x1014 | | FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. |
| CSTONES.PHASESHIFT | 0x1018 | | Parameter used in TPM, provided by software |
| CSTONES.NUMSAMPLESCOEFF | 0x101C | | Parameter used in TPM, provided by software |
| CSTONES.PCT16 | 0x1020 | | Mean magnitude and mean phase converted to IQ |
| CSTONES.MAGPHASEMEAN | 0x1024 | | Mean magnitude and phase of the signal before it is converted to PCT16 |
| CSTONES.IQRAWMEAN | 0x1028 | | Mean of IQ values |
| CSTONES.MAGSTD | 0x102C | | Magnitude standard deviation approximation |
| CSTONES.FFOEST | 0x1034 | | FFO estimate |
| CSTONES.DOWNSAMPLE | 0x1038 | | Turn on/off down sample of input IQ-signals |
| CSTONES.FREQOFFSET | 0x1044 | | Frequency offset estimate |
| RTT.CONFIG | 0x1050 | | RTT Config. |
| Register | Offset<br>TZ | Description |
| --------------- | -------------- | ---------------------- |
| RTT.SEGMENT01 | 0x1054 | RTT segments 0 and 1 |
| RTT.SEGMENT23 | 0x1058 | RTT segments 2 and 3 |
| RTT.SEGMENT45 | 0x105C | RTT segments 4 and 5 |
| RTT.SEGMENT67 | 0x1060 | RTT segments 6 and 7 |
#### <span id="page-489-1"></span>8.17.14.1 TASKS\_TXEN
Address offset: 0x000 Enable RADIO in TX mode
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ------------ | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | W | TASKS_TXEN | | | Enable RADIO in TX mode |
| | | | Trigger | 1 | Trigger task |
#### <span id="page-489-0"></span>8.17.14.2 TASKS\_RXEN
Address offset: 0x004 Enable RADIO in RX mode
| A | W | TASKS_RXEN | | | Enable RADIO in RX mode |
| ---- | ------------------ | ------------ | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | R/W Field | Value ID | Value | Description |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | | | | |
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
#### <span id="page-489-2"></span>8.17.14.3 TASKS\_START
Address offset: 0x008
Start RADIO
#### <span id="page-489-3"></span>8.17.14.4 TASKS\_STOP
Address offset: 0x00C
Stop RADIO
#### <span id="page-490-0"></span>8.17.14.5 TASKS\_DISABLE
Address offset: 0x010
Disable RADIO
#### <span id="page-490-1"></span>8.17.14.6 TASKS\_RSSISTART
Address offset: 0x014
Start the RSSI and take one single sample of the receive signal strength
#### <span id="page-490-2"></span>8.17.14.7 TASKS\_BCSTART
Address offset: 0x018 Start the bit counter
#### <span id="page-490-3"></span>8.17.14.8 TASKS\_BCSTOP
Address offset: 0x01C Stop the bit counter
#### <span id="page-491-0"></span>8.17.14.9 TASKS\_EDSTART
Address offset: 0x020
Start the energy detect measurement used in IEEE 802.15.4 mode
#### <span id="page-491-1"></span>8.17.14.10 TASKS\_EDSTOP
Address offset: 0x024
Stop the energy detect measurement
#### <span id="page-491-2"></span>8.17.14.11 TASKS\_CCASTART
Address offset: 0x028
Start the clear channel assessment used in IEEE 802.15.4 mode
#### <span id="page-491-3"></span>8.17.14.12 TASKS\_CCASTOP
Address offset: 0x02C
Stop the clear channel assessment
| A<br>W | TASKS_CCASTOP | | | | | | | Stop the clear channel assessment |
| ------------------ | --------------- | ---------- | --------------------------------------------------------------------------------------- | --------------------------------------------------------------- | -- | -- | -- | ----------------------------------- |
| ID<br>R/W Field | | Value ID | Value | | | | | Description |
| Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | | | | |
| ID | | | | | | | | |
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | | | | |
#### <span id="page-492-0"></span>8.17.14.13 TASKS\_AUXDATADMASTART
Address offset: 0x038
Start DMA transaction of acquisition
#### <span id="page-492-1"></span>8.17.14.14 TASKS\_AUXDATADMASTOP
Address offset: 0x03C
Stop ongoing DMA transaction of acquisition
#### <span id="page-492-2"></span>8.17.14.15 TASKS\_PLLEN
Address offset: 0x06C
Enable RADIO in PLL mode (standby for either TX or RX)
#### <span id="page-492-3"></span>8.17.14.16 TASKS\_CSTONESSTART
Address offset: 0x0A0
Start tone processing for channel sounding
| Bit number | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | -------------------- | ---------- | ------- | -- | -- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | | |
| | Reset 0x00000000 | | | 0 | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | | | Description |
| A | W | TASKS_CSTONESSTART | | | | | | Start tone processing for channel sounding |
| | | | Trigger | 1 | | | | Trigger task |
#### <span id="page-493-0"></span>8.17.14.17 TASKS\_SOFTRESET
Address offset: 0x0A4
Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state.
#### <span id="page-493-1"></span>8.17.14.18 SUBSCRIBE\_TXEN
Address offset: 0x100
Subscribe configuration for task [TXEN](#page-489-1)
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that task TXEN will subscribe to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable subscription |
| | | | Enabled | 1 | Enable subscription |
#### <span id="page-493-2"></span>8.17.14.19 SUBSCRIBE\_RXEN
Address offset: 0x104
Subscribe configuration for task [RXEN](#page-489-0)
#### <span id="page-494-0"></span>8.17.14.20 SUBSCRIBE\_START
Address offset: 0x108
Subscribe configuration for task [START](#page-489-2)
#### <span id="page-494-1"></span>8.17.14.21 SUBSCRIBE\_STOP
Address offset: 0x10C
Subscribe configuration for task [STOP](#page-489-3)
#### <span id="page-494-2"></span>8.17.14.22 SUBSCRIBE\_DISABLE
Address offset: 0x110
Subscribe configuration for task [DISABLE](#page-490-0)
#### <span id="page-494-3"></span>8.17.14.23 SUBSCRIBE\_RSSISTART
Address offset: 0x114
Subscribe configuration for task [RSSISTART](#page-490-1)
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | B |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | CHIDX | | [0255] |
| B | RW | EN | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-495-0"></span>8.17.14.24 SUBSCRIBE\_BCSTART
Address offset: 0x118
Subscribe configuration for task [BCSTART](#page-490-2)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that task BCSTART will subscribe to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable subscription |
| | | | Enabled | 1 | Enable subscription |
#### <span id="page-495-1"></span>8.17.14.25 SUBSCRIBE\_BCSTOP
Address offset: 0x11C
Subscribe configuration for task [BCSTOP](#page-490-3)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that task BCSTOP will subscribe to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable subscription |
#### <span id="page-495-2"></span>8.17.14.26 SUBSCRIBE\_EDSTART
Address offset: 0x120
Subscribe configuration for task [EDSTART](#page-491-0)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | CHIDX | | [0255] | |
| B | RW | EN | | | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
#### <span id="page-496-0"></span>8.17.14.27 SUBSCRIBE\_EDSTOP
Address offset: 0x124
Subscribe configuration for task [EDSTOP](#page-491-1)
#### <span id="page-496-1"></span>8.17.14.28 SUBSCRIBE\_CCASTART
Address offset: 0x128
Subscribe configuration for task [CCASTART](#page-491-2)
#### <span id="page-496-2"></span>8.17.14.29 SUBSCRIBE\_CCASTOP
Address offset: 0x12C
Subscribe configuration for task [CCASTOP](#page-491-3)
#### <span id="page-496-3"></span>8.17.14.30 SUBSCRIBE\_AUXDATADMASTART
Address offset: 0x138
Subscribe configuration for task [AUXDATADMASTART](#page-492-0)
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | B |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | CHIDX | | [0255] |
| B | RW | EN | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-497-0"></span>8.17.14.31 SUBSCRIBE\_AUXDATADMASTOP
Address offset: 0x13C
Subscribe configuration for task [AUXDATADMASTOP](#page-492-1)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that task AUXDATADMASTOP will subscribe to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable subscription |
| | | | Enabled | 1 | Enable subscription |
#### <span id="page-497-1"></span>8.17.14.32 SUBSCRIBE\_PLLEN
Address offset: 0x16C
Subscribe configuration for task [PLLEN](#page-492-2)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that task PLLEN will subscribe to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable subscription |
#### <span id="page-497-2"></span>8.17.14.33 SUBSCRIBE\_CSTONESSTART
Address offset: 0x1A0
Subscribe configuration for task [CSTONESSTART](#page-492-3)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | CHIDX | | [0255] | |
| B | RW | EN | | | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
#### <span id="page-498-2"></span>8.17.14.34 SUBSCRIBE\_SOFTRESET
Address offset: 0x1A4
Subscribe configuration for task [SOFTRESET](#page-493-0)
#### <span id="page-498-0"></span>8.17.14.35 EVENTS\_READY
Address offset: 0x200
RADIO has ramped up and is ready to be started
#### <span id="page-498-3"></span>8.17.14.36 EVENTS\_TXREADY
Address offset: 0x204
RADIO has ramped up and is ready to be started TX path
#### <span id="page-498-1"></span>8.17.14.37 EVENTS\_RXREADY
Address offset: 0x208
RADIO has ramped up and is ready to be started RX path
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ---------------- | -------------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | EVENTS_RXREADY | | |
| | | | NotGenerated | 0 |
| | | | Generated | 1 |
#### <span id="page-499-1"></span>8.17.14.38 EVENTS\_ADDRESS
Address offset: 0x20C Address sent or received
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------------- | -------------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | EVENTS_ADDRESS | | |
| | | | NotGenerated | 0 |
| | | | Generated | 1 |
#### <span id="page-499-3"></span>8.17.14.39 EVENTS\_FRAMESTART
Address offset: 0x210
IEEE 802.15.4 length field received
#### <span id="page-499-0"></span>8.17.14.40 EVENTS\_PAYLOAD
Address offset: 0x214
Packet payload sent or received
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------------- | -------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | EVENTS_PAYLOAD | | | |
| | | | NotGenerated | 0 | |
| | | | Generated | 1 | |
#### <span id="page-499-2"></span>8.17.14.41 EVENTS\_END
Address offset: 0x218
Memory access for packet data has been completed
In TX: Last byte to be transmitted has been fetched from RAM
In RX: Last byte received on air has been stored to RAM
#### <span id="page-500-0"></span>8.17.14.42 EVENTS\_PHYEND
Address offset: 0x21C
The last bit is sent on air or last bit is received
#### <span id="page-500-1"></span>8.17.14.43 EVENTS\_DISABLED
Address offset: 0x220 RADIO has been disabled
#### <span id="page-500-2"></span>8.17.14.44 EVENTS\_DEVMATCH
Address offset: 0x224
A device address match occurred on the last received packet
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------------- | -------------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | EVENTS_DEVMATCH | | |
| | | | NotGenerated | 0 |
| | | | Generated | 1 |
#### <span id="page-501-3"></span>8.17.14.45 EVENTS\_DEVMISS
Address offset: 0x228
No device address match occurred on the last received packet
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ---------------- | -------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | |
| ID | | R/W Field | Value ID | Value | |
| A | RW | EVENTS_DEVMISS | | | |
| | | | NotGenerated | 0 | |
| | | | Generated | 1 | |
#### <span id="page-501-0"></span>8.17.14.46 EVENTS\_CRCOK
Address offset: 0x22C
Packet received with CRC ok
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | -------------- | -------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | EVENTS_CRCOK | | | |
| | | | NotGenerated | 0 | |
| | | | Generated | 1 | |
#### <span id="page-501-1"></span>8.17.14.47 EVENTS\_CRCERROR
Address offset: 0x230
Packet received with CRC error
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------------- | -------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | EVENTS_CRCERROR | | | |
| | | | NotGenerated | 0 | |
| | | | Generated | 1 | |
#### <span id="page-501-2"></span>8.17.14.48 EVENTS\_BCMATCH
Address offset: 0x238
Bit counter reached bit count value
#### Bit counter value is specified in the RADIO.BCC register
#### <span id="page-502-0"></span>8.17.14.49 EVENTS\_EDEND
Address offset: 0x23C
Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register)
#### <span id="page-502-1"></span>8.17.14.50 EVENTS\_EDSTOPPED
Address offset: 0x240
The sampling of energy detection has stopped
#### <span id="page-502-2"></span>8.17.14.51 EVENTS\_CCAIDLE
Address offset: 0x244
Wireless medium in idle - clear to send
#### <span id="page-503-0"></span>8.17.14.52 EVENTS\_CCABUSY
Address offset: 0x248
Wireless medium busy - do not send
#### <span id="page-503-1"></span>8.17.14.53 EVENTS\_CCASTOPPED
Address offset: 0x24C The CCA has stopped
#### <span id="page-503-2"></span>8.17.14.54 EVENTS\_RATEBOOST
Address offset: 0x250
Ble\_LR CI field received, receive mode is changed from Ble\_LR125Kbit to Ble\_LR500Kbit
#### <span id="page-503-3"></span>8.17.14.55 EVENTS\_MHRMATCH
Address offset: 0x254
MAC header match found
#### <span id="page-504-0"></span>8.17.14.56 EVENTS\_SYNC
Address offset: 0x258 Initial sync detected
MODE=Ble\_LR125Kbit, Ble\_LR500Kbit, or Ieee802154\_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered.
For MODE=Nrf\_1Mbit, Nrf\_2Mbit, Ble\_1Mbit, or Ble\_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode.
It is also possible that the event is not generated, or not generated before the ADDRESS event.
#### <span id="page-504-1"></span>8.17.14.57 EVENTS\_CTEPRESENT
Address offset: 0x25C CTEInfo byte is received
#### <span id="page-504-2"></span>8.17.14.58 EVENTS\_PLLREADY
Address offset: 0x2B0
#### PLL has settled and RADIO is ready to be enabled in either TX or RX mode
#### <span id="page-505-0"></span>8.17.14.59 EVENTS\_RXADDRESS
Address offset: 0x2BC Address received
#### <span id="page-505-1"></span>8.17.14.60 EVENTS\_AUXDATADMAEND
Address offset: 0x2C0 AUXDATA DMA end
#### <span id="page-505-2"></span>8.17.14.61 EVENTS\_CSTONESEND
Address offset: 0x2C8
The channel sounding tone processing is complete
The results are available in the CSTONES registers
#### <span id="page-506-0"></span>8.17.14.62 PUBLISH\_READY
Address offset: 0x300
Publish configuration for event [READY](#page-498-0)
#### <span id="page-506-1"></span>8.17.14.63 PUBLISH\_TXREADY
Address offset: 0x304
Publish configuration for event [TXREADY](#page-498-3)
#### <span id="page-506-2"></span>8.17.14.64 PUBLISH\_RXREADY
Address offset: 0x308
Publish configuration for event [RXREADY](#page-498-1)
#### <span id="page-506-3"></span>8.17.14.65 PUBLISH\_ADDRESS
Address offset: 0x30C
Publish configuration for event [ADDRESS](#page-499-1)
#### <span id="page-507-0"></span>8.17.14.66 PUBLISH\_FRAMESTART
Address offset: 0x310
Publish configuration for event [FRAMESTART](#page-499-3)
#### <span id="page-507-1"></span>8.17.14.67 PUBLISH\_PAYLOAD
Address offset: 0x314
Publish configuration for event [PAYLOAD](#page-499-0)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event PAYLOAD will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
#### <span id="page-507-2"></span>8.17.14.68 PUBLISH\_END
Address offset: 0x318
Publish configuration for event [END](#page-499-2)
In TX: Last byte to be transmitted has been fetched from RAM
In RX: Last byte received on air has been stored to RAM
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | B |
| | Reset 0x00000000 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | CHIDX | | [0255] |
| B | RW | EN | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-508-0"></span>8.17.14.69 PUBLISH\_PHYEND
Address offset: 0x31C
Publish configuration for event [PHYEND](#page-500-0)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event PHYEND will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
| | | | Enabled | 1 | Enable publishing |
#### <span id="page-508-1"></span>8.17.14.70 PUBLISH\_DISABLED
Address offset: 0x320
Publish configuration for event [DISABLED](#page-500-1)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event DISABLED will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
#### <span id="page-508-2"></span>8.17.14.71 PUBLISH\_DEVMATCH
Address offset: 0x324
Publish configuration for event [DEVMATCH](#page-500-2)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | CHIDX | | [0255] | |
| B | RW | EN | | | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
#### <span id="page-509-0"></span>8.17.14.72 PUBLISH\_DEVMISS
Address offset: 0x328
Publish configuration for event [DEVMISS](#page-501-3)
#### <span id="page-509-1"></span>8.17.14.73 PUBLISH\_CRCOK
Address offset: 0x32C
Publish configuration for event [CRCOK](#page-501-0)
#### <span id="page-509-2"></span>8.17.14.74 PUBLISH\_CRCERROR
Address offset: 0x330
Publish configuration for event [CRCERROR](#page-501-1)
#### <span id="page-509-3"></span>8.17.14.75 PUBLISH\_BCMATCH
Address offset: 0x338
Publish configuration for event [BCMATCH](#page-501-2)
Bit counter value is specified in the RADIO.BCC register
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | B |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | CHIDX | | [0255] |
| B | RW | EN | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-510-0"></span>8.17.14.76 PUBLISH\_EDEND
Address offset: 0x33C
Publish configuration for event [EDEND](#page-502-0)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event EDEND will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
| | | | Enabled | 1 | Enable publishing |
#### <span id="page-510-1"></span>8.17.14.77 PUBLISH\_EDSTOPPED
Address offset: 0x340
Publish configuration for event [EDSTOPPED](#page-502-1)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event EDSTOPPED will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
#### <span id="page-510-2"></span>8.17.14.78 PUBLISH\_CCAIDLE
Address offset: 0x344
Publish configuration for event [CCAIDLE](#page-502-2)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | CHIDX | | [0255] | |
| B | RW | EN | | | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
#### <span id="page-511-0"></span>8.17.14.79 PUBLISH\_CCABUSY
Address offset: 0x348
Publish configuration for event [CCABUSY](#page-503-0)
#### <span id="page-511-1"></span>8.17.14.80 PUBLISH\_CCASTOPPED
Address offset: 0x34C
Publish configuration for event [CCASTOPPED](#page-503-1)
#### <span id="page-511-2"></span>8.17.14.81 PUBLISH\_RATEBOOST
Address offset: 0x350
Publish configuration for event [RATEBOOST](#page-503-2)
#### <span id="page-511-3"></span>8.17.14.82 PUBLISH\_MHRMATCH
Address offset: 0x354
Publish configuration for event [MHRMATCH](#page-503-3)
#### <span id="page-512-0"></span>8.17.14.83 PUBLISH\_SYNC
Address offset: 0x358
Publish configuration for event [SYNC](#page-504-0)
MODE=Ble\_LR125Kbit, Ble\_LR500Kbit, or Ieee802154\_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered.
For MODE=Nrf\_1Mbit, Nrf\_2Mbit, Ble\_1Mbit, or Ble\_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode.
It is also possible that the event is not generated, or not generated before the ADDRESS event.
#### <span id="page-512-1"></span>8.17.14.84 PUBLISH\_CTEPRESENT
Address offset: 0x35C
Publish configuration for event [CTEPRESENT](#page-504-1)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event CTEPRESENT will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
| | | | Enabled | 1 | Enable publishing |
#### <span id="page-512-2"></span>8.17.14.85 PUBLISH\_PLLREADY
Address offset: 0x3B0
Publish configuration for event [PLLREADY](#page-504-2)
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event PLLREADY will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
| | | | Enabled | 1 | Enable publishing |
#### <span id="page-513-0"></span>8.17.14.86 PUBLISH\_RXADDRESS
Address offset: 0x3BC
Publish configuration for event [RXADDRESS](#page-505-0)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event RXADDRESS will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
| | | | Enabled | 1 | Enable publishing |
#### <span id="page-513-1"></span>8.17.14.87 PUBLISH\_AUXDATADMAEND
Address offset: 0x3C0
Publish configuration for event [AUXDATADMAEND](#page-505-1)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | CHIDX | | [0255] | DPPI channel that event AUXDATADMAEND will publish to |
| B | RW | EN | | | |
| | | | Disabled | 0 | Disable publishing |
| | | | Enabled | 1 | Enable publishing |
#### <span id="page-513-2"></span>8.17.14.88 PUBLISH\_CSTONESEND
Address offset: 0x3C8
Publish configuration for event [CSTONESEND](#page-505-2)
The results are available in the CSTONES registers
#### <span id="page-514-0"></span>8.17.14.89 SHORTS
Address offset: 0x400
Shortcuts between local events and tasks
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | -------------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | Q P O N M L K<br>J<br>I<br>H G<br>F E D C B<br>A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | READY_START | | | Shortcut between event READY and task START |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| B | RW | DISABLED_TXEN | | | Shortcut between event DISABLED and task TXEN |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| C | RW | DISABLED_RXEN | | | Shortcut between event DISABLED and task RXEN |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| D | RW | ADDRESS_RSSISTART | | | Shortcut between event ADDRESS and task RSSISTART |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| E | RW | END_START | | | Shortcut between event END and task START |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| F | RW | ADDRESS_BCSTART | | | Shortcut between event ADDRESS and task BCSTART |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| G | RW | RXREADY_CCASTART | | | Shortcut between event RXREADY and task CCASTART |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| H | RW | CCAIDLE_TXEN | | | Shortcut between event CCAIDLE and task TXEN |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| I | RW | CCABUSY_DISABLE | | | Shortcut between event CCABUSY and task DISABLE |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| J | RW | FRAMESTART_BCSTART | | | Shortcut between event FRAMESTART and task BCSTART |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| K | RW | READY_EDSTART | | | Shortcut between event READY and task EDSTART |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| L | RW | EDEND_DISABLE | | | Shortcut between event EDEND and task DISABLE |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| M | RW | CCAIDLE_STOP | | | Shortcut between event CCAIDLE and task STOP |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| N | RW | TXREADY_START | | | Shortcut between event TXREADY and task START |
| | | | Disabled | 0 | Disable shortcut |
| | | | Enabled | 1 | Enable shortcut |
| O | RW | RXREADY_START | | | Shortcut between event RXREADY and task START |
| | | | Disabled | 0 | Disable shortcut |
| | Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ---------------- | ---------- | ------- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | |
| | Reset 0x00000000 | | | 0 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | |
| | | | Enabled | 1 | | |
| P | RW | PHYEND_DISABLE | | | | |
| | | | Disabled | 0 | | |
| | | | Enabled | 1 | | |
| Q | RW | PHYEND_START | | | | |
| | | | Disabled | 0 | | |
| | | | Enabled | 1 | | |
#### <span id="page-515-0"></span>8.17.14.90 INTENSET00
Address offset: 0x488 Enable interrupt
| Bit number | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ------------ | ---------- | --- | ------- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | |
| | Reset 0x00000000 | | | 0 | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | | Value | | |
| A | RW | READY | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| B | RW | TXREADY | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| C | RW | RXREADY | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| D | RW | ADDRESS | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| E | RW | FRAMESTART | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| F | RW | PAYLOAD | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| Bit number | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | --------------------- | -------- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | | 0 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | Description |
| G | RW | END | | | | Write '1' to enable interrupt for event END |
| | W1S | | | | | In TX: Last byte to be transmitted has been fetched from RAM |
| | | | | | | In RX: Last byte received on air has been stored to RAM |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| H | RW | PHYEND | Enabled | 1 | | Read: Enabled<br>Write '1' to enable interrupt for event PHYEND |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| | | | Enabled | 1 | | Read: Enabled |
| I | RW | DISABLED | | | | Write '1' to enable interrupt for event DISABLED |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| | | | Enabled | 1 | | Read: Enabled |
| J | RW | DEVMATCH | | | | Write '1' to enable interrupt for event DEVMATCH |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| K | RW | DEVMISS | Enabled | 1 | | Read: Enabled<br>Write '1' to enable interrupt for event DEVMISS |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| | | | Enabled | 1 | | Read: Enabled |
| L | RW | CRCOK | | | | Write '1' to enable interrupt for event CRCOK |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| | | | Enabled | 1 | | Read: Enabled |
| M | RW | CRCERROR | | | | Write '1' to enable interrupt for event CRCERROR |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled<br>Enabled | 0<br>1 | | Read: Disabled<br>Read: Enabled |
| N | RW | BCMATCH | | | | Write '1' to enable interrupt for event BCMATCH |
| | W1S | | | | | |
| | | | Set | 1 | | Bit counter value is specified in the RADIO.BCC register<br>Enable |
| | | | Disabled | 0 | | Read: Disabled |
| | | | Enabled | 1 | | Read: Enabled |
| O | RW | EDEND | | | | Write '1' to enable interrupt for event EDEND |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| | | | Disabled | 0 | | Read: Disabled |
| | | | Enabled | 1 | | Read: Enabled |
| P | RW | EDSTOPPED | | | | Write '1' to enable interrupt for event EDSTOPPED |
| | W1S | | | | | |
| | | | Set | 1 | | Enable |
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------------- | ---------- | ------- | ---------------------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| Q | RW<br>CCAIDLE<br>W1S | | | Write '1' to enable interrupt for event CCAIDLE |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| R | RW<br>CCABUSY<br>W1S | | | Write '1' to enable interrupt for event CCABUSY |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| S | RW<br>CCASTOPPED<br>W1S | | | Write '1' to enable interrupt for event CCASTOPPED |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| T | RW<br>RATEBOOST<br>W1S | | | Write '1' to enable interrupt for event RATEBOOST |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| U | RW<br>MHRMATCH<br>W1S | | | Write '1' to enable interrupt for event MHRMATCH |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| V | RW<br>SYNC | | | Write '1' to enable interrupt for event SYNC |
| | W1S | | | MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible |
| | | | | preamble has been received. However, due to the sporadic reception of |
| | | | | noise, this event can be falsely triggered. |
| | | | | For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible |
| | | | | preamble and the first two bytes of the address field has been received. The |
| | | | | event can be generated falsely also in this mode. |
| | | | | It is also possible that the event is not generated, or not generated before<br>the ADDRESS event. |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| W | RW<br>CTEPRESENT<br>W1S | | | Write '1' to enable interrupt for event CTEPRESENT |
| | | Set | 1 | Enable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
#### <span id="page-517-0"></span>8.17.14.91 INTENSET01
Address offset: 0x48C
Enable interrupt
| | Bit number | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | --------------- | ---------- | --- | ------- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | |
| | Reset 0x00000000 | | | 0 | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | | Value | | |
| A | RW | PLLREADY | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| B | RW | RXADDRESS | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| C | RW | AUXDATADMAEND | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
| D | RW | CSTONESEND | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
#### <span id="page-518-0"></span>8.17.14.92 INTENCLR00
Address offset: 0x490 Disable interrupt
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW<br>READY | | | Write '1' to disable interrupt for event READY |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| B | RW<br>TXREADY | | | Write '1' to disable interrupt for event TXREADY |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| C | RW<br>RXREADY | | | Write '1' to disable interrupt for event RXREADY |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| D | RW<br>ADDRESS | | | Write '1' to disable interrupt for event ADDRESS |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ----------------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| | | Enabled | 1 | Read: Enabled |
| E | RW<br>FRAMESTART | | | Write '1' to disable interrupt for event FRAMESTART |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| F | RW<br>PAYLOAD | | | Write '1' to disable interrupt for event PAYLOAD |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| G | RW<br>END | | | Write '1' to disable interrupt for event END |
| | W1C | | | In TX: Last byte to be transmitted has been fetched from RAM |
| | | | | In RX: Last byte received on air has been stored to RAM |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| H | RW<br>PHYEND | | | Write '1' to disable interrupt for event PHYEND |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| I | RW<br>DISABLED | | | Write '1' to disable interrupt for event DISABLED |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| J | RW<br>DEVMATCH<br>W1C | | | Write '1' to disable interrupt for event DEVMATCH |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| K | RW<br>DEVMISS | | | Write '1' to disable interrupt for event DEVMISS |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| L | RW<br>CRCOK | | | Write '1' to disable interrupt for event CRCOK |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| M | RW<br>CRCERROR | | | Write '1' to disable interrupt for event CRCERROR |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| N | RW<br>BCMATCH | Enabled | 1 | Read: Enabled<br>Write '1' to disable interrupt for event BCMATCH |
| | W1C | | | |
| | | | | Bit counter value is specified in the RADIO.BCC register |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------------- | ---------- | ------- | ---------------------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| O | RW<br>EDEND<br>W1C | | | Write '1' to disable interrupt for event EDEND |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| P | RW<br>EDSTOPPED | | | Write '1' to disable interrupt for event EDSTOPPED |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| Q | RW<br>CCAIDLE<br>W1C | | | Write '1' to disable interrupt for event CCAIDLE |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| R | RW<br>CCABUSY | | | Write '1' to disable interrupt for event CCABUSY |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| S | RW<br>CCASTOPPED<br>W1C | | | Write '1' to disable interrupt for event CCASTOPPED |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| T | RW<br>RATEBOOST<br>W1C | | | Write '1' to disable interrupt for event RATEBOOST |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| U | RW<br>MHRMATCH | | | Write '1' to disable interrupt for event MHRMATCH |
| | W1C | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| V | RW<br>SYNC | | | Write '1' to disable interrupt for event SYNC |
| | W1C | | | MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible |
| | | | | preamble has been received. However, due to the sporadic reception of |
| | | | | noise, this event can be falsely triggered. |
| | | | | For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible |
| | | | | preamble and the first two bytes of the address field has been received. The |
| | | | | event can be generated falsely also in this mode. |
| | | | | It is also possible that the event is not generated, or not generated before<br>the ADDRESS event. |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ------------ | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value |
| | | | Enabled | 1 |
| W | RW | CTEPRESENT | | |
| | W1C | | | |
| | | | Clear | 1 |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-521-0"></span>8.17.14.93 INTENCLR01
Address offset: 0x494
Disable interrupt
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | --------------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | D<br>C B<br>A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW<br>PLLREADY | | | Write '1' to disable interrupt for event PLLREADY |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| B | RW<br>RXADDRESS | | | Write '1' to disable interrupt for event RXADDRESS |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| C | RW<br>AUXDATADMAEND | | | Write '1' to disable interrupt for event AUXDATADMAEND |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| D | RW<br>CSTONESEND | | | Write '1' to disable interrupt for event CSTONESEND |
| | W1C | | | The results are available in the CSTONES registers |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
#### <span id="page-521-1"></span>8.17.14.94 INTENSET10
Address offset: 0x4A8 Enable interrupt
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | --- | --------------------- | --------------------------------------------------------------------------------------- |
| ID | | W V U T S R Q P O N | M L K<br>J<br>I<br>H G F E D C B A |
| Reset 0x00000000 | 0 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
A RW W1S
READY Write '1' to enable interrupt for event [READY](#page-498-0)
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ------------ | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | | Value ID | Value | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| B | RW<br>W1S | TXREADY | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| C | RW<br>W1S | RXREADY | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| D | RW<br>W1S | ADDRESS | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| E | RW<br>W1S | FRAMESTART | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| F | RW<br>W1S | PAYLOAD | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| G | RW | END | | | |
| | W1S | | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| H | RW<br>W1S | PHYEND | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| I | RW<br>W1S | DISABLED | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| J | RW<br>W1S | DEVMATCH | | | |
| | | | Set | 1 | |
| | | | Disabled | 0 | |
| | | | Enabled | 1 | |
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------------------- | --------------------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID<br>K | RW | R/W Field<br>DEVMISS | Value ID | Value | Description<br>Write '1' to enable interrupt for event DEVMISS |
| | W1S | | | | |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| L | RW<br>W1S | CRCOK | | | Write '1' to enable interrupt for event CRCOK |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| M | RW<br>W1S | CRCERROR | | | Write '1' to enable interrupt for event CRCERROR |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| N | RW | BCMATCH | | | Write '1' to enable interrupt for event BCMATCH |
| | W1S | | | | Bit counter value is specified in the RADIO.BCC register |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| O | RW<br>W1S | EDEND | | | Write '1' to enable interrupt for event EDEND |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| P | RW<br>W1S | EDSTOPPED | | | Write '1' to enable interrupt for event EDSTOPPED |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| Q | RW<br>W1S | CCAIDLE | | | Write '1' to enable interrupt for event CCAIDLE |
| | | | Set | 1 | Enable |
| | | | Disabled<br>Enabled | 0<br>1 | Read: Disabled<br>Read: Enabled |
| R | RW | CCABUSY | | | Write '1' to enable interrupt for event CCABUSY |
| | W1S | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| S | RW<br>W1S | CCASTOPPED | | | Write '1' to enable interrupt for event CCASTOPPED |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| T | RW<br>W1S | RATEBOOST | | | Write '1' to enable interrupt for event RATEBOOST |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| | Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value<br>Description |
| U | RW<br>MHRMATCH | | Write '1' to enable interrupt for event MHRMATCH |
| | W1S | | |
| | | Set | 1<br>Enable |
| | | Disabled | 0<br>Read: Disabled |
| | | Enabled | 1<br>Read: Enabled |
| V | RW<br>SYNC | | Write '1' to enable interrupt for event SYNC |
| | W1S | | MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible |
| | | | preamble has been received. However, due to the sporadic reception of |
| | | | noise, this event can be falsely triggered. |
| | | | For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible |
| | | | preamble and the first two bytes of the address field has been received. The |
| | | | event can be generated falsely also in this mode. |
| | | | It is also possible that the event is not generated, or not generated before |
| | | | the ADDRESS event. |
| | | Set | 1<br>Enable |
| | | Disabled | 0<br>Read: Disabled |
| | | Enabled | 1<br>Read: Enabled |
| W | RW<br>CTEPRESENT | | Write '1' to enable interrupt for event CTEPRESENT |
| | W1S | | |
| | | Set | 1<br>Enable |
| | | Disabled | 0<br>Read: Disabled |
| | | Enabled | 1<br>Read: Enabled |
#### <span id="page-524-0"></span>8.17.14.95 INTENSET11
Address offset: 0x4AC Enable interrupt
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | --------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | D<br>C B<br>A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | | Value ID | Value | Description |
| A | RW | PLLREADY | | | Write '1' to enable interrupt for event PLLREADY |
| | W1S | | | | |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| B | RW | RXADDRESS | | | Write '1' to enable interrupt for event RXADDRESS |
| | W1S | | | | |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| C | RW | AUXDATADMAEND | | | Write '1' to enable interrupt for event AUXDATADMAEND |
| | W1S | | | | |
| | | | Set | 1 | Enable |
| | | | Disabled | 0 | Read: Disabled |
| | | | Enabled | 1 | Read: Enabled |
| Bit number | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ------------ | ---------- | ------- | -- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | |
| | Reset 0x00000000 | | | 0 | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | | |
| D | RW | CSTONESEND | | | | | |
| | W1S | | | | | | |
| | | | Set | 1 | | | |
| | | | Disabled | 0 | | | |
| | | | Enabled | 1 | | | |
#### <span id="page-525-0"></span>8.17.14.96 INTENCLR10
Address offset: 0x4B0 Disable interrupt
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW<br>READY | | | Write '1' to disable interrupt for event READY |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| B | RW<br>TXREADY<br>W1C | | | Write '1' to disable interrupt for event TXREADY |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| C | RW<br>RXREADY<br>W1C | | | Write '1' to disable interrupt for event RXREADY |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| D | RW<br>ADDRESS<br>W1C | | | Write '1' to disable interrupt for event ADDRESS |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| E | RW<br>FRAMESTART<br>W1C | | | Write '1' to disable interrupt for event FRAMESTART |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| F | RW<br>PAYLOAD | | | Write '1' to disable interrupt for event PAYLOAD |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| G | RW<br>END | | | Write '1' to disable interrupt for event END |
| | W1C | | | In TX: Last byte to be transmitted has been fetched from RAM |
| | | | | In RX: Last byte received on air has been stored to RAM |
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | --------------------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| H | RW<br>PHYEND | | | Write '1' to disable interrupt for event PHYEND |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| I | RW<br>DISABLED | | | Write '1' to disable interrupt for event DISABLED |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| J | RW<br>DEVMATCH | | | Write '1' to disable interrupt for event DEVMATCH |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| K | RW<br>DEVMISS | | | Write '1' to disable interrupt for event DEVMISS |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled<br>Enabled | 0<br>1 | Read: Disabled<br>Read: Enabled |
| L | RW<br>CRCOK | | | Write '1' to disable interrupt for event CRCOK |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| M | RW<br>CRCERROR | | | Write '1' to disable interrupt for event CRCERROR |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| N | RW<br>BCMATCH | | | Write '1' to disable interrupt for event BCMATCH |
| | W1C | | | Bit counter value is specified in the RADIO.BCC register |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| O | RW<br>EDEND | | | Write '1' to disable interrupt for event EDEND |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| P | RW<br>EDSTOPPED | | | Write '1' to disable interrupt for event EDSTOPPED |
| | W1C | | | |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| Q | RW<br>CCAIDLE | | | Write '1' to disable interrupt for event CCAIDLE |
W1C
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | W V U T S R Q P O N<br>M L K<br>J<br>I<br>H G F E D C B A |
| | Reset 0x00000000 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| R | RW<br>CCABUSY<br>W1C | | | Write '1' to disable interrupt for event CCABUSY |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| S | RW<br>CCASTOPPED<br>W1C | | | Write '1' to disable interrupt for event CCASTOPPED |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| T | RW<br>RATEBOOST<br>W1C | | | Write '1' to disable interrupt for event RATEBOOST |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| U | RW<br>MHRMATCH<br>W1C | | | Write '1' to disable interrupt for event MHRMATCH |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| V | RW<br>SYNC | | | Write '1' to disable interrupt for event SYNC |
| | W1C | | | MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible |
| | | | | preamble has been received. However, due to the sporadic reception of |
| | | | | noise, this event can be falsely triggered. |
| | | | | For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible |
| | | | | preamble and the first two bytes of the address field has been received. The |
| | | | | event can be generated falsely also in this mode. |
| | | | | It is also possible that the event is not generated, or not generated before |
| | | | | the ADDRESS event. |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
| W | RW<br>CTEPRESENT<br>W1C | | | Write '1' to disable interrupt for event CTEPRESENT |
| | | Clear | 1 | Disable |
| | | Disabled | 0 | Read: Disabled |
| | | Enabled | 1 | Read: Enabled |
#### <span id="page-527-0"></span>8.17.14.97 INTENCLR11
Address offset: 0x4B4 Disable interrupt
| Bit number | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | --------------- | ---------- | ------- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | |
| | Reset 0x00000000 | | | 0 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | | Value ID | Value | | |
| A | RW | PLLREADY | | | | |
| | W1C | | | | | |
| | | | Clear | 1 | | |
| | | | Disabled | 0 | | |
| | | | Enabled | 1 | | |
| B | RW | RXADDRESS | | | | |
| | W1C | | | | | |
| | | | Clear | 1 | | |
| | | | Disabled | 0 | | |
| | | | Enabled | 1 | | |
| C | RW | AUXDATADMAEND | | | | |
| | W1C | | | | | |
| | | | Clear | 1 | | |
| | | | Disabled | 0 | | |
| | | | Enabled | 1 | | |
| D | RW | CSTONESEND | | | | |
| | W1C | | | | | |
| | | | Clear | 1 | | |
| | | | Disabled | 0 | | |
| | | | Enabled | 1 | | |
#### <span id="page-528-0"></span>8.17.14.98 MODE
Address offset: 0x500
Data rate and modulation
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ----------------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | MODE | | | Radio data rate and modulation setting. The radio supports frequency-shift |
| | | | | | keying (FSK) modulation. |
| | | | Nrf_1Mbit | 0 | 1 Mbps Nordic proprietary radio mode |
| | | | Nrf_2Mbit | 1 | 2 Mbps Nordic proprietary radio mode |
| | | | Ble_1Mbit | 3 | 1 Mbps BLE |
| | | | Ble_2Mbit | 4 | 2 Mbps BLE |
| | | | Ble_LR125Kbit | 5 | Long range 125 kbps TX, 125 kbps and 500 kbps RX |
| | | | Ble_LR500Kbit | 6 | Long range 500 kbps TX, 125 kbps and 500 kbps RX |
| | | | Nrf_4Mbit_0BT6 | 9 | 4 Mbps Nordic proprietary radio mode (BT=0.6/h=0.5) |
| | | | Nrf_4Mbit_0BT4 | 10 | 4 Mbps Nordic proprietary radio mode (BT=0.4/h=0.5) |
| | | | Ieee802154_250Kbit 15 | | IEEE 802.15.4-2006 250 kbps |
#### <span id="page-528-1"></span>8.17.14.99 PHYENDTXDELAY
Address offset: 0x518
Configurable delay of PHYEND event for TX
There are separate values for each on-air bit rate. The maximum supported value is 3.5 us (unit is 0.5 us)
This register will not be reset by the SOFTRESET task
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000421 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 |
| ID | | R/W Field | Value ID | Value |
| A | RW | RATE4M | | |
| | | | | |
| | | | | |
| B | RW | RATE2M | | |
| | | | | |
| | | | | |
| C | RW | RATE1M | | |
| | | | | |
| | | | | |
| D | RW | RATE250K | | |
| | | | | |
| | | | | |
#### <span id="page-529-1"></span>8.17.14.100 STATE
Address offset: 0x520 Current radio state
#### <span id="page-529-0"></span>8.17.14.101 EDCTRL
Address offset: 0x530
IEEE 802.15.4 energy detect control
| | Bit number | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | ---- | ------- | -- | -- | ------------- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | | B B B B B B | |
| | Reset 0x20000000 | | | 0 | | | | | 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | | Value | | | | Description |
| A | RW | EDCNT | | | | | | | IEEE 802.15.4 energy detect loop count |
| | | | | | | | | | Number of iterations to perform an ED scan. If set to 0 one scan is |
| | | | | | | | | | performed, otherwise the specified number + 1 of ED scans will be |
| | | | | | | | | | performed and the max ED value tracked in EDSAMPLE. |
| B | RW | EDPERIOD | | | | | | | IEEE 802.15.4 energy detect period, 4us resolution, no averaging except the |
| | | | | | | | | | IEEE 802.15.4 ED range 128us (32) |
| | | | | | | | | | EDPERIOD value other than Default is not supported. |
| | | | Default | 32 | | | | | |
#### <span id="page-530-0"></span>8.17.14.102 EDSAMPLE
Address offset: 0x534
IEEE 802.15.4 energy detect level
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | R | EDLVL | | [0127] |
Register value must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by factor ED\_RSSISCALE, as shown in the code example for ED sampling
#### <span id="page-530-1"></span>8.17.14.103 CCACTRL
Address offset: 0x538
IEEE 802.15.4 clear channel assessment control
| Bit number | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | -------------- | ------------------ | ------- | -- | -- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | D | | | | D D D D D D D C C C C C C C C B B B B B B B B |
| | Reset 0x052D0000 | | | 0 | | | | 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | | | Description |
| A | RW | CCAMODE | | | | | | CCA mode of operation |
| | | | EdMode | 0 | | | | Energy above threshold |
| | | | | | | | | Will report busy whenever energy is detected above CCAEDTHRES |
| | | | CarrierMode | 1 | | | | Carrier seen |
| | | | | | | | | Will report busy whenever compliant IEEE 802.15.4 signal is seen |
| | | | CarrierAndEdMode | 2 | | | | Energy above threshold AND carrier seen |
| | | | CarrierOrEdMode | 3 | | | | Energy above threshold OR carrier seen |
| | | | EdModeTest1 | 4 | | | | Energy above threshold test mode that will abort when first ED |
| | | | | | | | | measurement over threshold is seen. No averaging. |
| B | RW | CCAEDTHRES | | | | | | CCA energy busy threshold. Used in all the CCA modes except CarrierMode. |
| | | | | | | | | Must be converted from IEEE 802.15.4 range by dividing by factor |
| | | | | | | | | ED_RSSISCALE - similar to EDSAMPLE register |
| C | RW | CCACORRTHRES | | | | | | CCA correlator busy threshold. Only relevant to CarrierMode, |
| | | | | | | | | CarrierAndEdMode, and CarrierOrEdMode. |
| D | RW | CCACORRCNT | | | | | | Limit for occurances above CCACORRTHRES. When not equal to zero the |
| | | | | | | | | corrolator based signal detect is enabled. |
#### <span id="page-531-0"></span>8.17.14.104 DATAWHITE
Address offset: 0x540
Data whitening configuration
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00890040 | | | 0 | 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | IV | | | |
| | | | | | |
| B | RW | POLY | | | |
| | | | | | |
#### <span id="page-531-1"></span>8.17.14.105 AUXDATA.CNF[n] (n=0..1)
Address offset: 0x548 + (n × 0x4)
AUXDATA configuration
This register will not be reset by the SOFTRESET task
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | B | A A A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | ACQMODE | | | Acquisition mode (data from RADIO written to memory) |
| | | | Rtt | 7 | Baseband Channel Sounding RTT Data |
| B | RW | DIR | | | Data acquisition or injection |
| | | | Acq | 0 | Peripheral to memory |
| | | | Inj | 1 | Memory to peripheral |
#### <span id="page-532-0"></span>8.17.14.106 AUXDATADMA[n].ENABLE (n=0..1)
Address offset: 0x550 + (n × 0x10) Enable or disable data acquisition
#### <span id="page-532-1"></span>8.17.14.107 AUXDATADMA[n].PTR (n=0..1)
Address offset: 0x554 + (n × 0x10)
ACQ DMA pointer
See the memory chapter for details about which memories are available for EasyDMA.
#### <span id="page-532-2"></span>8.17.14.108 AUXDATADMA[n].MAXCNT (n=0..1)
Address offset: 0x558 + (n × 0x10)
Maximum number of 32-bit words to transfer
#### <span id="page-532-3"></span>8.17.14.109 AUXDATADMA[n].AMOUNT (n=0..1)
Address offset: 0x55C + (n × 0x10)
Number of 32-bit words transferred in the last transaction
#### <span id="page-532-4"></span>8.17.14.110 TIMING
Address offset: 0x704
#### Timing
#### <span id="page-533-0"></span>8.17.14.111 FREQUENCY
Address offset: 0x708
Frequency
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000002 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | RW | FREQUENCY | | |
| B | RW | MAP | | |
| | | | | |
| | | | | |
#### <span id="page-533-1"></span>8.17.14.112 TXPOWER
Address offset: 0x710
Output power
| Bit number | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | ------- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | |
| | Reset 0x00000013 | | | 0 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 |
| ID | | R/W Field | Value ID | Value | | |
| A | RW | TXPOWER | | | | |
| | | | | | | |
| | | | MaxdBm | 0x3F | | |
| | | | Pos8dBm | 0x3F | | |
| | | | Pos7dBm | 0x39 | | |
| | | | Pos6dBm | 0x33 | | |
| | | | Pos5dBm | 0x2D | | |
| | | | Pos4dBm | 0x28 | | |
| | | | Pos3dBm | 0x23 | | |
| | | | Pos2dBm | 0x1F | | |
| | | | Pos1dBm | 0x1B | | |
| | | | 0dBm | 0x18 | | |
| | | | Neg1dBm | 0x15 | | |
| | | | Neg2dBm | 0x13 | | |
| | | | Neg3dBm | 0x11 | | |
| | | | Neg4dBm | 0xF | | |
| | | | Neg5dBm | 0xD | | |
| | | | Neg6dBm | 0xB | | |
| | | | Neg7dBm | 0xA | | |
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | A A A A A A A A A A A |
| Reset 0x00000013 | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 |
| ID<br>R/W Field | Value ID | Value | Description |
| | Neg8dBm | 0x9 | -8 dBm |
| | Neg9dBm | 0x8 | -9 dBm |
| | Neg10dBm | 0x7 | -10 dBm |
| | Neg12dBm | 0x6 | -12 dBm |
| | Neg14dBm | 0x5 | -14 dBm |
| | Neg16dBm | 0x4 | -16 dBm |
| | Neg18dBm | 0x3 | -18 dBm |
| | Neg20dBm | 0x2 | -20 dBm |
| | Neg22dBm | 0x2 | -22 dBm |
| | Neg28dBm | 0x1 | -28 dBm |
| | Neg40dBm | 0x130 | -40 dBm |
| | Neg46dBm | 0x110 | -46 dBm |
| | MindBm | 0x0 | Minimum output power |
#### <span id="page-534-1"></span>8.17.14.113 TIFS
Address offset: 0x714 Interframe spacing in μs
| ID | Reset 0x00000000<br>R/W Field<br>Value ID | | | Value | | | Description |
| ---- | ------------------------------------------- | -- | -- | ------- | --------------------------------------------------------------------------------------- | -- | ------------- |
| | | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | | |
| ID | | | | | | | |
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | |
A RW TIFS Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet.
#### <span id="page-534-0"></span>8.17.14.114 RSSISAMPLE
Address offset: 0x718
RSSI sample
| ID | | R/W Field | Value ID | Value | | Description |
| ------------ | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- | --------------------------------------------------------------- | ------------- |
| | Reset 0x0000007F | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 | |
| ID | | | | | | |
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | |
A R RSSISAMPLE RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm.
#### <span id="page-534-2"></span>8.17.14.115 RXGAIN.CONFIG
Address offset: 0x7D4
Override configuration of receiver gain control loop
Overriding the default values can result in unpredictable behavior
This register will not be reset by the SOFTRESET task
#### <span id="page-535-0"></span>8.17.14.116 FREQFINETUNE
Address offset: 0x0804
Fine tuning of the RF frequency
Receiver sensitivity may be degraded when operating on 2414, 2415, 2430, 2431, 2446, 2447, 2462, 2463, 2478 or 2479 MHz with a small but non-zero FREQFINETUNE value
This register will not be reset by the SOFTRESET task
#### <span id="page-535-1"></span>8.17.14.117 FECONFIG
Address offset: 0x908
Config register
This register will not be reset by the SOFTRESET task
#### <span id="page-535-2"></span>8.17.14.118 CFO\_STAT
Address offset: 0xB00
Carrier freq. offset estimate
This register will not be reset by the SOFTRESET task
#### <span id="page-536-0"></span>8.17.14.119 DBCCORR
Address offset: 0xB40 Correlator thresholds
This register will not be reset by the SOFTRESET task
#### <span id="page-536-1"></span>8.17.14.120 DFEMODE
Address offset: 0xD00
Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
#### <span id="page-536-2"></span>8.17.14.121 DFESTATUS
Address offset: 0xD04 DFE status information
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ---------------- | ----------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | B<br>A A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | R | SWITCHINGSTATE | | | Internal state of switching state machine |
| | | | Idle | 0 | Switching state Idle |
| | | | Offset | 1 | Switching state Offset |
| | | | Guard | 2 | Switching state Guard |
| | | | Ref | 3 | Switching state Ref |
| | | | Switching | 4 | Switching state Switching |
| | | | Ending | 5 | Switching state Ending |
| B | R | SAMPLINGSTATE | | | Internal state of sampling state machine |
| | | | Idle | 0 | Sampling state Idle |
| | | | Sampling | 1 | Sampling state Sampling |
#### <span id="page-537-0"></span>8.17.14.122 DFECTRL1
Address offset: 0xD10
Various configuration for Direction finding
| | Bit number | | | | | | | | | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ------------------- | ---------- | ------- | -- | -- | ----------------- | ------- | --------- | ---------------------------------------------------------- | -- | --------------- | -- | -- | -- | --------- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | H H H H G G G G | | | | | F F F E D D D | | | | C C C B | |
| | Reset 0x00023282 | | | 0 | | | | | | | | | | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 |
| ID | | R/W Field | Value ID | Value | | | | | | Description | | | | | | | |
| A | RW | NUMBEROF8US | | | | | | | | Length of the AoA/AoD procedure in number of 8 us units | | | | | | | |
| | | | | | | | | | | | | | | | | | Always used in TX mode, but in RX mode only when CTEINLINECTRLEN is 0 |
| B | RW | DFEINEXTENSION | | | | | | | | | | | | | | | Add CTE extension and do antenna switching/sampling in this extension |
| | | | CRC | 1 | | | | | | AoA/AoD procedure triggered at end of CRC | | | | | | | |
| | | | Payload | 0 | | | | | | Antenna switching/sampling is done in the packet payload | | | | | | | |
| C | RW | TSWITCHSPACING | | | | | | | | | | | | | | | Interval between every time the antenna is changed in the SWITCHING state |
| | | | 4us | 1 | | | | 4us | | | | | | | | | |
| | | | 2us | 2 | | | | 2us | | | | | | | | | |
| | | | 1us | 3 | | | | 1us | | | | | | | | | |
| D | RW | TSAMPLESPACINGREF | | | | | | | | Interval between samples in the REFERENCE period | | | | | | | |
| | | | 4us | 1 | | | | 4us | | | | | | | | | |
| | | | 2us | 2 | | | | 2us | | | | | | | | | |
| | | | 1us | 3 | | | | 1us | | | | | | | | | |
| | | | 500ns | 4 | | | | 0.5us | | | | | | | | | |
| | | | 250ns | 5 | | | | | 0.25us | | | | | | | | |
| | | | 125ns | 6 | | | | | 0.125us | | | | | | | | |
| E | RW | SAMPLETYPE | | | | | | | | Whether to sample I/Q or magnitude/phase | | | | | | | |
| | | | IQ | 0 | | | | | | Complex samples in I and Q | | | | | | | |
| | | | MagPhase | 1 | | | | | | Complex samples as magnitude and phase | | | | | | | |
| F | RW | TSAMPLESPACING | | | | | | | | | | | | | | | Interval between samples in the SWITCHING period when CTEINLINECTRLEN |
| | | | | | | | | is 0 | | | | | | | | | |
| | | | | | | | | | | | | | | | | | Note: Not used when CTEINLINECTRLEN is set. Then either |
| | | | | | | | | | | | | | | | | | CTEINLINERXMODE1US or CTEINLINERXMODE2US are used. |
| | | | 4us | 1 | | | | 4us | | | | | | | | | |
| | | | 2us | 2 | | | | 2us | | | | | | | | | |
| | | | 1us | 3 | | | | 1us | | | | | | | | | |
| | | | 500ns | 4 | | | | 0.5us | | | | | | | | | |
| | | | 250ns | 5 | | | | | 0.25us | | | | | | | | |
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00023282 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 |
| ID | | R/W Field | Value ID | Value | |
| | | | 125ns | 6 | |
| G | RW | REPEATPATTERN | | | |
| | | | NoRepeat | 0 | |
| H | RW | AGCBACKOFFGAIN | | | |
| | | | | | |
| | | | | | |
#### <span id="page-538-0"></span>8.17.14.123 DFECTRL2
Address offset: 0xD14
Start offset for Direction finding
| Bit number | | | | | | | | | | | | | | | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------------------------------------------- | --------------- | -- | --- | -- | -- | -- | -- | -- | -- | -- | -- | ------------- | -- | ------------------------- | -- | -- | -- | -- | -- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | | | | | | | | | | | | B B B B B B B B B B B B | | | | | | | A A A A A A A A A A A A A |
| | Reset 0x00000000 | | | 0 | | | | | | | | | | | | | | | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field<br>Value ID<br>Value<br>RW<br>TSWITCHOFFSET | | | | | | | | | | | | Description | | | | | | | | | |
| A | | | | | | | | | | | | | | | | | | | | | | Signed value offset after the end of the CRC before starting switching in |
| | | | | | | | | | | | | | | | number of 16M cycles | | | | | | | |
| B | RW | TSAMPLEOFFSET | | | | | | | | | | | | | | | | | | | | Signed value offset before starting sampling in number of 16M cycles |
| | | | | | | | | | | | | | | | | | | | | | | relative to the beginning of the REFERENCE state - 12 us after switching start |
#### <span id="page-538-1"></span>8.17.14.124 SWITCHPATTERN
Address offset: 0xD28
GPIO patterns to be used for each antenna
Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be configured in the GPIO peripheral as described in Pin configuration.
If the total number of antenna slots is bigger than the number of patterns, we loop back to the pattern used after the reference pattern.
| | Bit number |
| ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------ |
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br>ID<br>Reset 0x00000000<br>0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br>ID<br>R/W Field<br>Value ID<br>Value<br>A<br>RW<br>SWITCHPATTERN | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
#### <span id="page-538-2"></span>8.17.14.125 CLEARPATTERN
Address offset: 0xD2C
Clear the GPIO pattern array for antenna control
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | |
| Reset 0x00000000 | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID<br>R/W Field | Value ID | Value | Description |
A W CLEARPATTERN Clear the GPIO pattern array for antenna control
Behaves as a task register, but does not have PPI nor IRQ
#### <span id="page-539-0"></span>8.17.14.126 PSEL.DFEGPIO[n] (n=0..7)
Address offset: 0xD30 + (n × 0x4)
Pin select for DFE pin n
**Note:** Must be set before enabling the radio
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | -------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | C | B B B B A A A A A |
| | Reset 0xFFFFFFFF | | | 1 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | PIN | | [031] | Pin number |
| B | RW | PORT | | [01] | Port number |
| C | RW | CONNECT | | | Connection |
| | | | Disconnected | 1 | Disconnect |
| | | | Connected | 0 | Connect |
#### 8.17.14.127 DFEPACKET
DFE packet EasyDMA channel
#### <span id="page-539-1"></span>8.17.14.127.1 DFEPACKET.PTR
Address offset: 0xD50
Data pointer
| | Bit number | | | | | | | | | | | | | | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | --------------------------------------------- | -- | --- | --- | -- | -- | -- | -- | -- | ------------- | -- | -------------- | -- | -- | -- | -- | -- | -- | -- | -- | --------------------------------------------------------------- | --------------------------------------------------------------------------------------- |
| ID | | | | A | | | | | | | | | | | | | | | | | | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A |
| | Reset 0x00000000 | | 0 | | | | | | | | | | | | | | | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| ID | | | | | | | | | | Description | | | | | | | | | | | | |
| A | R/W Field<br>Value ID<br>Value<br>RW<br>PTR | | | | | | | | | | | Data pointer | | | | | | | | | | |
See the memory chapter for details about which memories are available for EasyDMA.
#### <span id="page-539-2"></span>8.17.14.127.2 DFEPACKET.MAXCNT
Address offset: 0xD54
Maximum number of bytes to transfer
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ----------------------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | |
| Reset 0x00004000 | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID<br>R/W Field<br>Value ID | Value | Description |
A RW MAXCNT Maximum number of bytes to transfer
#### <span id="page-540-3"></span>8.17.14.127.3 DFEPACKET.AMOUNT
Address offset: 0xD58
Number of bytes transferred in the last transaction
#### <span id="page-540-4"></span>8.17.14.127.4 DFEPACKET.CURRENTAMOUNT
Address offset: 0xD5C
Number of bytes transferred in the current transaction
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | R | AMOUNT | | | |
updated.
#### <span id="page-540-2"></span>8.17.14.128 CRCSTATUS
Address offset: 0xE0C
CRC status
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| Reset 0x00000000 | | | 0 | |
| ID | R/W Field | Value ID | Value | |
| A<br>R | CRCSTATUS | | | |
| | | CRCError | 0 | |
| | | CRCOk | 1 | |
#### <span id="page-540-0"></span>8.17.14.129 RXMATCH
Address offset: 0xE10 Received address
| A | R | RXMATCH | | Received address |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | R/W Field | Value ID | Value<br>Description |
| | Reset 0x00000000 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | | | |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
Logical address of which previous packet was received
#### <span id="page-540-1"></span>8.17.14.130 RXCRC
Address offset: 0xE14
#### CRC field of previously received packet
CRC field of previously received packet
#### <span id="page-541-1"></span>8.17.14.131 DAI
Address offset: 0xE18
Device address match index
| A | R | DAI | | | | | | | Device address match index |
| ---- | ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- | -- | ------------- | -- | ---------------------------- |
| ID | | R/W Field | Value ID | Value | | | Description | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | | | | |
| ID | | | | | | | | | |
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | | | |
Index (n) of device address, see DAB[n] and DAP[n], that got an address match
#### <span id="page-541-2"></span>8.17.14.132 PDUSTAT
Address offset: 0xE1C
Payload status
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | B B A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | R | PDUSTAT | | | Status on payload length vs. PCNF1.MAXLEN |
| | | | LessThan | 0 | Payload less than PCNF1.MAXLEN |
| | | | GreaterThan | 1 | Payload greater than PCNF1.MAXLEN |
| B | R | CISTAT | | | Status on what rate packet is received with in Long Range |
| | | | LR125kbit | 0 | Frame is received at 125 kbps |
| | | | LR500kbit | 1 | Frame is received at 500 kbps |
#### <span id="page-541-0"></span>8.17.14.133 PCNF0
Address offset: 0xE20
Packet configuration register 0
| | Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ----------- | ------- | ----- | --------------------------------------------------------------------------------------- |
| ID | | | | | H H | |
| | Reset 0x00000000 | | | 0 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | |
| D | RW | S1INCL | | | | |
| | | | Automatic | 0 | | |
| | | | Include | 1 | | |
| E | RW | CILEN | | | | |
| F | RW | PLEN | | | | |
| | | | 8bit | 0 | | |
| | | | 16bit | 1 | | |
| | | | 32bitZero | 2 | | |
| | | | LongRange | 3 | | |
| G | RW | CRCINC | | | | |
| | | | Exclude | 0 | | |
| | | | Include | 1 | | |
| H | RW | TERMLEN | | | | |
#### <span id="page-542-0"></span>8.17.14.134 PCNF1
Address offset: 0xE28
Packet configuration register 1
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ------------- | --------------------- | -------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | MAXLEN | | | [0255] |
| B | RW | STATLEN | | | [0255] |
| C | RW | BALEN | | [24] | |
| D | RW | ENDIAN | Little<br>Big | 0<br>1 | |
| E | RW | WHITEEN | Disabled<br>Enabled | 0<br>1 | |
| F | RW | WHITEOFFSET | Include<br>Exclude | 0<br>1 | |
#### <span id="page-542-1"></span>8.17.14.135 BASE0
Address offset: 0xE2C
#### Base address 0
#### <span id="page-543-0"></span>8.17.14.136 BASE1
Address offset: 0xE30
Base address 1
#### <span id="page-543-1"></span>8.17.14.137 PREFIX0
Address offset: 0xE34
Prefixes bytes for logical addresses 0-3
#### <span id="page-543-2"></span>8.17.14.138 PREFIX1
Address offset: 0xE38
Prefixes bytes for logical addresses 4-7
#### <span id="page-543-3"></span>8.17.14.139 TXADDRESS
Address offset: 0xE3C Transmit address select
| A | RW | TXADDRESS | | | Transmit address select |
| ---- | ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | R/W Field | Value ID | Value | Description |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | | | | A A A |
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
Logical address to be used when transmitting a packet
#### <span id="page-544-0"></span>8.17.14.140 RXADDRESSES
Address offset: 0xE40 Receive address select
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value |
| A-H | RW | ADDR[i] (i=07) | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-544-1"></span>8.17.14.141 CRCCNF
Address offset: 0xE44 CRC configuration
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------- | ------------ | ------- | ----------------------------------------------------------------------------------------------- |
| ID | | | | | B B B<br>A A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | LEN | | | CRC length in number of bytes. |
| | | | | | Note: For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set<br>to 3 is supported |
| | | | Disabled | 0 | CRC length is zero and CRC calculation is disabled |
| | | | One | 1 | CRC length is one byte and CRC calculation is enabled |
| | | | Two | 2 | CRC length is two bytes and CRC calculation is enabled |
| | | | Three | 3 | CRC length is three bytes and CRC calculation is enabled |
| B | RW | SKIPADDR | | | Control whether CRC calculation skips the address field. Other fields can<br>also be skipped. |
| | | | Include | 0 | CRC calculation includes address field |
| | | | Skip | 1 | CRC calculation starting at first byte after address field. |
| | | | Ieee802154 | 2 | CRC calculation starting at first byte after length field (as per 802.15.4 |
| | | | | | standard). |
| | | | SkipS0 | 3 | CRC calculation starting at first byte after S0 field. |
| | | | SkipS1 | 4 | CRC calculation starting at first byte after S1 field. |
#### <span id="page-544-2"></span>8.17.14.142 CRCPOLY
Address offset: 0xE48
CRC polynomial
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br>ID<br>A A A A A A A A A A A A A A A A A A A A A A A A<br>Reset 0x00000000<br>0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br>ID<br>R/W Field<br>Value ID<br>Value<br>Description |
| ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| |
A RW CRCPOLY CRC polynomial
Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/ bit is hardwired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
#### <span id="page-545-0"></span>8.17.14.143 CRCINIT
Address offset: 0xE4C
CRC initial value
| A | RW | CRCINIT | | | CRC initial value |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- | ------------------- |
| ID | | R/W Field | Value ID | Value | Description |
| | Reset 0x00000000 | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| ID | | | | | |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | |
Initial value for CRC calculation
#### <span id="page-545-2"></span>8.17.14.144 DAB[n] (n=0..7)
Address offset: 0xE50 + (n × 0x4) Device address base segment n
#### <span id="page-545-3"></span>8.17.14.145 DAP[n] (n=0..7)
Address offset: 0xE70 + (n × 0x4)
Device address prefix n
#### <span id="page-545-1"></span>8.17.14.146 DACNF
Address offset: 0xE90
Device address match configuration
| Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ----------------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A-H | RW | ENA[i] (i=07) | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
| I-P | RW | TXADD[i] (i=07) | | |
#### <span id="page-546-0"></span>8.17.14.147 BCC
Address offset: 0xE94 Bit counter compare
| A | RW | BCC | | | | | | | | | Bit counter compare |
| ---- | ------------------ | ----------- | ---------- | ------- | -- | -- | -- | -- | ------------- | -- | --------------------- |
| ID | | R/W Field | Value ID | Value | | | | | Description | | |
| | Reset 0x00000000 | | | 0 | | | | | | | |
| ID | | | | A | | | | | | | |
| | Bit number | | | | | | | | | | |
Bit counter compare register
#### <span id="page-546-1"></span>8.17.14.148 CTESTATUS
Address offset: 0xEA4
CTEInfo parsed from received packet
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000000 | | | 0 |
| ID | | R/W Field | Value ID | Value |
| A | R | CTETIME | | |
| B | R | RFU | | |
| C | R | CTETYPE | | |
#### <span id="page-546-2"></span>8.17.14.149 MHRMATCHCONF
Address offset: 0xEB4
Search pattern configuration
| ID | | R/W Field | Value ID | Value | | | Description |
| ---- | ------------------ | ----------- | ---------- | --------------------------------------------------------------------------------------- | --------------------------------------------------------------- | -- | ------------- |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | | |
| ID | | | | A | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A | | |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | | |
A RW MHRMATCHCONF Search pattern configuration
#### <span id="page-546-3"></span>8.17.14.150 MHRMATCHMASK
Address offset: 0xEB8
Pattern mask
| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ----------------------------- | --------------------------------------------------------------------------------------- |
| ID | A |
| Reset 0x00000000 | 0 |
| ID<br>R/W Field<br>Value ID | Value |
#### <span id="page-547-0"></span>8.17.14.151 SFD
Address offset: 0xEBC
IEEE 802.15.4 start of frame delimiter
A RW MHRMATCHMASK Pattern mask
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x000000A7 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | SFD | | | |
| | | | | | |
#### <span id="page-547-1"></span>8.17.14.152 CTEINLINECONF
Address offset: 0xEC0
Configuration for CTE inline mode
| | Bit number | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | -------------------- | ---------- | ------- | -- | -- | -- | ------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| ID | | | | H | | | | | H H H H H H H G G G G G G G G F F F E E E |
| | Reset 0x00002800 | | | 0 | | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | | | | Description |
| A | RW | CTEINLINECTRLEN | | | | | | | Enable parsing of CTEInfo from received packet in BLE modes |
| | | | Enabled | 1 | | | | | Parsing of CTEInfo is enabled |
| | | | Disabled | 0 | | | | | Parsing of CTEInfo is disabled |
| B | RW | CTEINFOINS1 | | | | | | | CTEInfo is S1 byte or not |
| | | | InS1 | 1 | | | | | CTEInfo is in S1 byte (data PDU) |
| | | | NotInS1 | 0 | | | | | CTEInfo is NOT in S1 byte (advertising PDU) |
| C | RW | CTEERRORHANDLING | | | | | | | Sampling/switching if CRC is not OK |
| | | | Yes | 1 | | | | | Sampling and antenna switching also when CRC is not OK |
| | | | No | 0 | | | | | No sampling and antenna switching when CRC is not OK |
| D | RW | CTETIMEVALIDRANGE | | | | | | | Max range of CTETime<br>Note: Valid range is 2-20 in BLE core spec. If larger than 20, it can<br>be an indication of an error in the received packet. |
| | | | 20 | 0 | | | | | 20 in 8us unit (default)<br>Set to 20 if parsed CTETime is larger han 20 |
| | | | 31 | 1 | | | | | 31 in 8us unit |
| | | | 63 | 2 | | | | | 63 in 8us unit |
| E | RW | CTEINLINERXMODE1US | | | | | | | Spacing between samples for the samples in the SWITCHING period when<br>CTEINLINEMODE is set<br>When the device is in AoD mode, this is used when the received CTEType is |
| | | | | | | | | | "AoD 1 us". When in AoA mode, this is used when TSWITCHSPACING is 2 us. |
| | | | 4us | 1 | | | | 4us | |
| | | | 2us | 2 | | | | 2us | |
| | | | 1us | 3 | | | | 1us | |
| | | | 500ns | 4 | | | | 0.5us | |
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | -------------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | H | H H H H H H H G G G G G G G G F F F E E E |
| | Reset 0x00002800 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | | Value ID | Value | |
| | | | 250ns | 5 | |
| | | | 125ns | 6 | |
| F | RW | CTEINLINERXMODE2US | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | 4us | 1 | |
| | | | 2us | 2 | |
| | | | 1us | 3 | |
| | | | 500ns | 4 | |
| | | | 250ns | 5 | |
| | | | 125ns | 6 | |
| G | RW | S0CONF | | | |
| | | | | | |
| H | RW | S0MASK | | | |
| | | | | | |
#### <span id="page-548-0"></span>8.17.14.153 PACKETPTR
Address offset: 0xED0
Packet pointer
See the memory chapter for details about which memories are available for EasyDMA.
#### <span id="page-548-1"></span>8.17.14.154 CSTONES.MODE
Address offset: 0x1000
Selects the mode(s) that are activated on the start signal
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----- | ---------- | --------------------------------------------------------------------------------------- |
| ID | | | | |
| | Reset 0x00000003 | | | 0 |
| ID | R/W Field | | Value ID | Value |
| A | RW | TPM | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
| B | RW | TFM | | |
| | | | Disabled | 0 |
| | | | Enabled | 1 |
#### <span id="page-549-0"></span>8.17.14.155 CSTONES.NUMSAMPLES
Address offset: 0x1004
Number of input samples at 2MHz sample rate
#### <span id="page-549-1"></span>8.17.14.156 CSTONES.NEXTFREQUENCY
Address offset: 0x1008
The value of FREQUENCY that will be used in the next step
#### <span id="page-549-2"></span>8.17.14.157 CSTONES.FAEPEER
Address offset: 0x1014
FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps.
This register will not be reset by the SOFTRESET task
#### <span id="page-549-3"></span>8.17.14.158 CSTONES.PHASESHIFT
Address offset: 0x1018
Parameter used in TPM, provided by software
#### <span id="page-549-4"></span>8.17.14.159 CSTONES.NUMSAMPLESCOEFF
Address offset: 0x101C
Parameter used in TPM, provided by software
| A | RW | NUMSAMPLESCOEFF | | | | Coefficient 2**16/(numSamples/16) in Q1.15 format (Default numsamples |
| ---- | ------------------ | ----------------- | ---------- | --------------------------------------------------------------------------------------- | -- | ----------------------------------------------------------------------- |
| ID | | R/W Field | Value ID | Value | | Description |
| | Reset 0x0000199A | | | 0<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 | | |
| ID | | | | | | |
| | Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | |
#### <span id="page-550-0"></span>8.17.14.160 CSTONES.PCT16
Address offset: 0x1020
Mean magnitude and mean phase converted to IQ
#### <span id="page-550-1"></span>8.17.14.161 CSTONES.MAGPHASEMEAN
Address offset: 0x1024
Mean magnitude and phase of the signal before it is converted to PCT16
#### <span id="page-550-2"></span>8.17.14.162 CSTONES.IQRAWMEAN
Address offset: 0x1028 Mean of IQ values
#### <span id="page-550-3"></span>8.17.14.163 CSTONES.MAGSTD
Address offset: 0x102C
Magnitude standard deviation approximation
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------- | --------------------------------------------------------------------------------------- |
| ID | | |
| Reset 0x00000000 | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID<br>R/W Field | Value ID<br>Value | Description |
A R MAGSTD Magnitude standard deviation approximation
#### <span id="page-551-0"></span>8.17.14.164 CSTONES.FFOEST
Address offset: 0x1034
FFO estimate
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ----------------------------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | A A A A A A A A A A A A |
| Reset 0x00000000 | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID<br>R/W Field<br>Value ID | Value | Description |
A R FFOEST Units 62.5 ppb. Max range +/-100 ppm plus margin.
#### <span id="page-551-1"></span>8.17.14.165 CSTONES.DOWNSAMPLE
Address offset: 0x1038
Turn on/off down sample of input IQ-signals
| | Bit number | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | -------------- | ---------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | |
| A | RW | ENABLEFILTER | | | |
| | | | OFF | 0 | |
| | | | ON | 1 | |
| B | RW | RATE | | | |
| | | | BLE1M | 0 | |
| | | | BLE2m | 1 | |
#### <span id="page-551-2"></span>8.17.14.166 CSTONES.FREQOFFSET
Address offset: 0x1044 Frequency offset estimate
A R FREQOFFSET
#### <span id="page-551-3"></span>8.17.14.167 RTT.CONFIG
Address offset: 0x1050
RTT Config.
| Bit number | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ------------- | ----------- | ------- | --------------------------------------------------------------------------------------- |
| ID | | | | | E E E E E E E E E<br>D D D D C B A |
| | Reset 0x00000000 | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | Description |
| A | RW | EN | | | Enable RTT Functionality. Only valid for BLE 1MBPS and 2MBPS mode |
| | | | Disabled | 0 | Disable RTT Block |
| | | | Enabled | 1 | Enable RTT Block |
| B | RW | ENFULLAA | | | Enabling/Disable ping over the entire access address. |
| | | | Disabled | 0 | Disable ping over the entire access address, i.e., enable only over the first |
| | | | | | 16-bit access address |
| | | | Enabled | 1 | Enable ping over the entire access address |
| C | RW | ROLE | | | Role as a Initiator or Reflector. |
| | | | Initiator | 0 | Initiator |
| | | | Reflector | 1 | Reflector |
| D | RW | NUMSEGMENTS | | | Number of 16bit payload segments available for ToA detection. Allowed |
| | | | | | values are 0, 2, 4, 6 and 8. |
| E | RW | EFSDELAY | | | Early Frame Sync Delay, i.e., number of cycles to wait for access address to |
| | | | | | anchor correctly. For 2MBPSBLE mode, the EFSDELAY value is 64 (2us) and |
| | | | | | for 1MBPSBLE mode, it can be 256 (8us). |
#### <span id="page-552-0"></span>8.17.14.168 RTT.SEGMENT01
Address offset: 0x1054 RTT segments 0 and 1
| | Bit number | | | | | | | | | | | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ---- | ------------------ | ----------- | ---------- | ------- | -- | -- | -- | -- | ------------- | ------------------ | -- | -- | -- | -- | -- | -- | -- | -- | --------------------------------------------------------------------------------------- |
| ID | | | | A | | | | | | | | | | | | | | | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A |
| | Reset 0x00000000 | | | 0 | | | | | | | | | | | | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | | R/W Field | Value ID | Value | | | | | Description | | | | | | | | | | |
| A | RW | DATA | | | | | | | | Data Bits 31 - 0 | | | | | | | | | |
#### <span id="page-552-1"></span>8.17.14.169 RTT.SEGMENT23
Address offset: 0x1058 RTT segments 2 and 3
| A | RW | DATA | | | | | | | | | Data Bits 63 - 32 |
| ---- | ------------------ | ----------- | ---------- | -- | --- | ------- | -- | -- | -- | ------------- | ------------------- |
| ID | | R/W Field | Value ID | | | Value | | | | Description | |
| | Reset 0x00000000 | | | | 0 | | | | | | |
| ID | | | | | A | | | | | | |
| | Bit number | | | | | | | | | | |
#### <span id="page-552-2"></span>8.17.14.170 RTT.SEGMENT45
Address offset: 0x105C RTT segments 4 and 5
| Bit number | | | | | | | | | | | | | | | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------ | ------------------ | ---------- | --- | ------- | -- | -- | -- | ------------------- | -- | -- | -- | -- | -- | -- | -- | -- | -- | --------------------------------------------------------------------------------------- |
| ID | | | A | | | | | | | | | | | | | | | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A |
| | Reset 0x00000000 | | 0 | | | | | | | | | | | | | | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | | Value | | | | Description | | | | | | | | | | |
| A | RW<br>DATA | | | | | | | Data Bits 95 - 64 | | | | | | | | | | |
#### <span id="page-553-1"></span>8.17.14.171 RTT.SEGMENT67
Address offset: 0x1060 RTT segments 6 and 7
Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device.
For accelerated lifetime testing (HTOL, etc.), supply voltage should not exceed the recommended operating conditions max value, see Recommended operating conditions on page 923.
| Parameter | Min. | Max. | Unit | |
|---|---|---|---|---|
| VDD | VDD supply voltage | -0.3 | 3.9 | V |
| VDDEXT | VDD supply voltage under extended operating temperature | -0.3 | 3.7 | V |
Table 93: Supply voltage
| Parameter | Min. | Max. | Unit | |
|---|---|---|---|---|
| VI/O, VDD ≤3.6 V | IO voltage | -0.3 | VDD + 0.3 | V |
| VI/O, VDD >3.6 V | IO voltage | -0.3 | 3.9 | V |
| VI/O,EXT, VDDEXT ≤3.4 V | IO voltage under extended operating temperature | -0.3 | VDD + 0.3 | V |
| VI/O,EXT, VDDEXT >3.4 V | IO voltage under extended operating temperature | -0.3 | 3.7 | V |
Table 94: I/O pin voltage
| Min. | Max. | Unit | |
|---|---|---|---|
| RF input level | 10 | dBm |
Table 95: Radio
| Note | Min. | Max. | Unit | |
|---|---|---|---|---|
| Storage temperature | -40 | +125 | °C | |
| Reflow soldering temperature | Reflow cycle time is 30 seconds with 3 maximum reflow cycles. | 260 | °C | |
| Moisture Sensitivity Level (MSL) | 2 | |||
| ESD Human Body Model (HBM) | 1 | kV | ||
| ESD Charged Device Model (CDM) | 500 | V |
Table 96: Environmental QFN package types
| Note | Min. | Max. | Unit | |
|---|---|---|---|---|
| Storage temperature | Recommended storage condition is < 40°C and < 90% RH (relative humidity) | -40 | +125 | °C |
| Reflow soldering temperature | Reflow cycle time is 30 seconds with 3 maximum reflow cycles. | 260 | °C | |
| Moisture Sensitivity Level (MSL) | 1 | |||
| ESD Human Body Model (HBM) | 3 | kV | ||
| ESD Charged Device Model (CDM) | 250 | V |
Table 97: Environmental CSP package types
| Min. | Max. | Unit | |
|---|---|---|---|
| Endurance | 10,000 | Write/ rewrite cycles | |
| Retention at 85°C | 10 | y | |
| Retention at 105°C | 2 | y |
Table 98: RRAM memory
Recommended Operating Conditions
| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| VDD,POR | VDD supply voltage needed during power-on reset. | 1.75 | V | ||
| VDD | VDD supply voltage. | 1.7 | 3.6 | V | |
| VDD,EXT | VDD supply voltage under extended operating temperature. | 1.7 | 3.4 | V |
11.14.2 Power-fail comparator
| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| VPOF | Voltage level warning thresholds (falling supply voltage). Levels are | 1.7 | 3.2 | V | |
| configurable between min. and max. in increments of 100 mV. | |||||
| VPOFTOL | Threshold voltage tolerance. | -2 | 2 | % | |
| VPOFHYST | Threshold voltage hysteresis. | 40 | 50 | 55 | mV |
| VBOR,OFF | Brownout reset voltage range System OFF mode. Brownout only applies to | 1.56 | 1.64 | V | |
| the voltage on VDD. | |||||
| VBOR,ON | Brownout reset voltage range System ON mode. Brownout only applies to the | 1.57 | 1.64 | V | |
| voltage on VDD. |
Thermal Information
A summary of the thermal characteristics for the different packages available for the device can be found below.
| Symbol | Package | Typ. | Unit |
|---|---|---|---|
| θJA,QFN48 | QFN48 | 24.86 | °C/W |
| θJC,QFN48 | QFN48 | 12.71 | °C/W |
| θJA,CSP47 | CSP47 | 83.84 | °C/W |
| θJC,CSP47 | CSP47 | 7.82 | °C/W |
Table 90: Package thermal characteristics
Values for θJA are obtained by simulation following the EIA/JESD51-2 for still air condition using JEDEC PCB.
Values for θJC are obtained by simulation. A cold plate and the grease between package and cold plate are modeled.
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.
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