NRF54L

Wireless System-on-Chip (SoC)

The NRF54L is a wireless system-on-chip (soc) from Nordic Semiconductor ASA. View the full NRF54L datasheet below including electrical characteristics.

Manufacturer

Nordic Semiconductor ASA

Overview

Part: nRF54L15, nRF54L10, nRF54L05 — Nordic Semiconductor Type: Wireless System-on-Chip (SoC) Description: Ultra-low power multiprotocol 2.4 GHz wireless SoC integrating a 128 MHz Arm Cortex-M33 processor, a RISC-V coprocessor, comprehensive peripherals, and scalable memory up to 1524 KB NVM and 256 KB RAM.

Operating Conditions:

Supply voltage: 1.7 V to 3.6 V
Operating temperature: -40°C to 105°C
CPU clock speed: 128 MHz

Absolute Maximum Ratings:

Key Specs:

CPU: 128 MHz Arm Cortex-M33 with TrustZone
NVM (nRF54L15): 1524 KB RRAM
RAM (nRF54L15): 256 KB
Bluetooth LE TX current (1 Mbps, 0 dBm): 4.8 mA @3.0 V
Bluetooth LE RX current (1 Mbps): 3.4 mA @3.0 V
System OFF current: 0.6 μA @3.0 V
Bluetooth LE sensitivity (1 Mbps): -96 dBm (0.1% BER)
Bluetooth LE sensitivity (125 kbps long range): -104 dBm (0.1% BER)
Output power: Up to +8 dBm (1 dB step size from -8 dBm to +8 dBm)
ADC resolution/sample rate: 14-bit at 31.25 ksps, 12-bit at 250 ksps, up to 10-bit at 2 Msps

Features:

Multiprotocol 2.4 GHz radio (Bluetooth 6.0, 802.15.4-2020, proprietary 2.4 GHz up to 4 Mbps)
128 MHz RISC-V coprocessor
Advanced security (TrustZone isolation, tamper detection, cryptographic engine side-channel leakage protection)
Global RTC available in System OFF
14-bit ADC
High-speed serial interfaces (SPI up to 32 MHz, UARTE up to 4 Mbps, I2C up to 400 kHz)
Single-precision floating-point unit (FPU)
Memory protection unit (MPU)
NFC interface

Applications:

Package:

QFN48 (6.0x6.0 mm, 31 GPIO pins)
CSP47 (2.4x2.2 mm, 300 μm pitch, 32 GPIO pins)

Features

■ 128 MHz Arm® Cortex®-M33 processor
■ Scalable memory configurations up to 1524 KB NVM and up to 256 KB RAM
■ Multiprotocol 2.4 GHz radio supporting Bluetooth Low Energy, 802.15.4-2020, and 2.4 GHz proprietary modes (up to 4 Mbps)
■ Comprehensive set of peripherals including new Global RTC available in System OFF, 14-bit ADC, and high-speed serial interfaces
■ 128 MHz RISC-V coprocessor
■ Advanced security including TrustZone® isolation, tamper detection, and cryptographic engine side-channel leakage protection
■ Ultra-compact WL CSP (2.4x2.2 mm) and QFN (6.0x6.0 mm) packages

Pin Configuration

The GPIO port peripheral implements up to 32 pins, PIN[n] (n = 0..31), that can be individually configured in the PIN_CNF[n] registers (n=0..31).

The following parameters can be enabled or configured in these registers:

Direction
Drive strength
Pull-up and pull-down resistors
Pin sensing
Input buffer disconnect
Analog input (for selected pins)

All write-capable registers are retained registers. See POWER - Power control on page 92 for more information.

When not used as an input, disconnect the input buffer of the GPIO pin to save power. An input must be connected to get a valid value in the IN register and for the sense mechanism to have access to the pin.

Other peripherals in the system can connect to GPIO pins to override their output value, override their configuration, or read their analog or digital input value.

Selected pins also support analog input signals (ANAIN). The assignment of the analog pins can be found in Pin assignments on page 837.

GPIO drive strength is configured using the DRIVE0 and DRIVE1 fields of register PIN_CNF[n] (n=0..31) (Retained) on page 281. Some pins may not support every drive configuration, see Pin assignments on page 837 for more information.

When a pin is configured as digital input, it is important to minimize increased current consumption when the input voltage is between VIL and VIH. It is a good practice to ensure that the external circuitry does not drive the pin to levels between VIL and VIH for a long period of time.

For more information on pin assignment and the corresponding effect of read and write operations of GPIO registers, see Peripheral and subsystem assignment on page 275.

Note: NFCT uses two pins to connect to the antenna, which are shared with GPIOs. NFC pins are enabled from reset. To use them as GPIO pins, NFC use must be disabled using register PADCONFIG on page 392. For more details, see NFCT - Near field communication tag on page 354.

Electrical Characteristics


For scaling between hardware value and dBm, see Clear channel assessment (CCA) on page 472.

The mlme-scan.req primitive of the MAC layer uses the ED measurement to detect channels where there might be wireless activity. To assist this primitive, a tailored mode of operation is available where the ED measurement runs for a defined number of iterations keeping track of the maximum ED level. This is engaged by writing the EDCNT field of the EDCTRL register to a value different from 0 , where it will run the specified number of iterations and report the maximum energy measurement in the EDSAMPLE register. The scan is started with the EDSTART task and the end indicated with the EDEND event. This significantly reduces the interrupt frequency and therefore power consumption. The following figure shows how the ED measurement will operate depending on the EDCNT and EDPERIOD fields of the EDCTRL register.

Figure 125: Energy detection measurement for a single iteration (EDCNT = 0)

![]({{img:images/dd2431ce95000f08785268709d2ffc072def5cd95e302084762e742e6bb04285.jpg}})

Figure 126: Energy detection measurement example with multiple iterations

![]({{img:images/2cd1679c53af6e019057001ee534a5dd571e7e55755570e8fcabac901b60ba9c.jpg}})

The scan is stopped by writing the EDSTOP task. It is followed by the EDSTOPPED event when the module has terminated.

## 8.17.12.4 Clear channel assessment (CCA)

IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when transmitting. This is known as carrier sense multiple access with collision avoidance (CSMA-CA). The key part of this method is measuring if the wireless medium is busy or not.

The following clear channel assessment modes are supported:

- CCA Mode 1 (energy above threshold) - The medium is reported busy upon detecting any energy above the ED threshold.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

- CCA Mode 2 (carrier sense only) - The medium is reported busy upon detection of a signal compliant with IEEE 802.15.4 with the same modulation and spreading characteristics.
- CCA Mode 3 (carrier sense with energy above threshold) - The medium is reported busy using a logical combination (AND/OR) between the results from CCA Mode 1 and CCA Mode 2.

The clear channel assessment should survey a period equal to 8 symbols or 128 μs.

RADIO must be in RX mode and be able to receive correct packets when performing the CCA. The shortcut between READY and START must be disabled if baseband processing is not to be performed while the measurement is running.

Register EDSAMPLE on page 514 is updated at the end of the clear channel assessment and can be used to read the energy level measured during the procedure. For CCACTRL.CCAMODE = EdModeEdModeTest1, EDSAMPLE holds the first ED measurement. For the other CCA modes, EDSAMPLE holds the average ED value.

## CCA Mode 1

CCA Mode 1 is enabled by first configuring the field CCACTRL.CCAMODE = EdMode and writing the CCACTRL.CCAEDTHRES field to a chosen value. Once the CCASTART task is written, RADIO will perform an ED measurement for 8 symbols and compare the measured level with that found in the CCACTRL.CCAEDTHRES field. If the measured value is higher than or equal to this threshold, the CCABUSY event is generated. If the measured level is less than the threshold, the CCAIDLE event is generated.

## CCA Mode 2

CCA Mode 2 is enabled by configuring the field CCACTRL.CCAMODE = CarrierMode. RADIO will sample to see if a valid SFD is found during the 8 symbols. If a valid SFD is detected, the CCABUSY event is generated and the device should not send any data. The CCABUSY event is also generated if the scan was performed during an ongoing frame reception. If the measurement period completes with no SFD detection, the CCAIDLE event is generated. When CCACTRL.CCACORRCNT is not zero, the algorithm will look at the correlator output in addition to the SFD detection signal. If an SFD is reported during the scan period, it will terminate immediately indicating busy medium. Similarly, if the number of peaks above CCACTRL.CCACORRTHRES crosses the CCACTRL.CCACORRCNT, the CCACTRL.CCABUSY event is generated. If less than CCACORRCOUNT crossings are found and no SFD is reported, the CCAIDLE event will be generated and the device can send data.

## CCA Mode 3

CCA Mode 3 is enabled by configuring CCACTRL.CCAMODE = CarrierAndEdMode or CCACTRL.CCAMODE = CarrierOrEdMode and performing the required logical combination of the result from CCA Mode 1 and CCA Mode 2. The CCABUSY or CCAIDLE events are generated by ANDing or ORing the energy above threshold and carrier detection scans.

## Shortcuts

An ongoing CCA can be stopped by issuing the CCASTOP task. This will trigger the associated CCASTOPPED event.

For CCA mode automation, the following shortcuts are available:

- To automatically switch between RX mode (when performing the CCA) and to TX mode where the packet is sent, the shortcut between CCAIDLE and TXEN, in conjunction with the short between CCAIDLE and STOP, must be used.
- To automatically disable RADIO whenever the CCA reports a busy medium, the shortcut between CCABUSY and DISABLE can be used.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

- To immediately start a CCA after ramping up into RX mode, the shortcut between RXREADY and CCASTART can be used.

## Conversion

The conversion from a CCAEDTHRES, LQI, or EDSAMPLE value to dBm can be done with the following equation, where VALHARDWARE is either CCAEDTHRES, LQI, or EDSAMPLE. LQI and EDSAMPLE are hardwarereported values, while CCAEDTHRES is set by software. Constants ED\_RSSISCALE and ED\_RSSIOFFS are from the electrical specifications.

PRF[dBm] = ED_RSSIOFFS + VALHARDWARE


The ED\_RSSISCALE constant is used to calculate power in 802.15.4 units (0-255), using the following formula:

PRF[802.15.4 units] = MIN( ED_RSSISCALE x VALHARDWARE, 255 )


## 8.17.12.5 Cyclic redundancy check (CRC)

IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MAC header (MHR) and MAC service data unit (MSDU).

The standard defines the following generator polynomial:

<!-- formula-not-decoded -->

In RX mode, RADIO will trigger the CRC module when the first octet after the frame length (PHR) is received. The CRC will then update on each consecutive octet received. When a complete frame is received, the CRCSTATUS register will be updated accordingly and the CRCOK or CRCERROR events will be generated. When the CRC module is enabled, it will not write the two last octets (CRC) to the frame RAM. When transmitting, the CRC will be computed on the fly, starting with the first octet after PHR, and inserted as the two last octets in the frame. The EasyDMA will fetch the frame length minus 2 octets from RAM and insert the CRC octets at their correct positions in the frame.

The following code shows how to configure the CRC module for correct operation when in IEEE 802.15.4 mode. The CRCCNF is written to 16-bit CRC and the CRCPOLY is written to 0x11021 . The start value used by IEEE 802.15.4 is 0 and CRCINIT is configured to reflect this.

/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/ NRF_RADIO->CRCCNF = ((RADIO_CRCCNF_SKIPADDR_Ieee802154 << RADIO_CRCCNF_SKIPADDR_Pos) | (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos)); NRF_RADIO->CRCPOLY = 0x11021; NRF_RADIO->CRCINIT = 0;


The ENDIANESS subregister must be set to little-endian since the FCS field is transmitted from the left bit to the right bit.

## 8.17.12.6 Transmit sequence

The transmission is started by first putting RADIO in RX mode and triggering the RXEN task .

An outline of the IEEE 802.15.4 transmission is illustrated in the following figure.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 127: IEEE 802.15.4 transmit sequence

![]({{img:images/b49e92d7c53aaca180af140887ab7b690fb9a9e569beadce2bf7f342e94042f9.jpg}})

The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving the READY event, the CCA is started by triggering the CCASTART task. The chosen mode of assessment (register CCACTRL.CCAMODE) will be performed and signal the CCAIDLE event or CCABUSY event 128 μs later. If the event CCABUSY is received, RADIO will have to retry the CCA after a specific back-off period. This is outlined in the IEEE 802.15.4 standard, Figure 69 in section 7.5.1.4 The CSMA-CA algorithm .

If the event CCAIDLE is generated, a write to the task register TXEN enters RADIO in TXRU state. The READY event will be generated when RADIO is in the TXIDLE state and ready to transmit. With the PACKETPTR pointing to the length (PHR) field of the frame, the START task can be written. RADIO will send the four octet preamble sequence followed by the start of frame delimiter (register SFD). The first byte read from RAM is the length field (PHR) followed by the transmission of the number of bytes indicated as the frame length. If the CRC module is configured, it will run for PHR-2 octets. The last two octets will be substituted with the results from running the CRC. The necessary CRC parameters are sampled on the START task. The FCS field of the frame is little endian.

In addition to the available shortcuts, one is provided between the READY event and the CCASTART task so that a CCA can automatically start when the receiver is ready. A second shortcut has been added between the CCAIDLE event and the TXEN task, when a clear channel is detected, RADIO can immediately enter TX mode.

## 8.17.12.7 Receive sequence

RADIO must be in RX mode before the receive sequence can begin. After writing to the RXEN task, RADIO will start ramping up and enter the RXRU state.

When the READY event is generated, RADIO enters the RXIDLE mode. For the baseband processing to be enabled, the START task must be written. An outline of the IEEE 802.15.4 receive sequence can be found in the following figure.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 128: IEEE 802.15.4 receive sequence

![]({{img:images/22a3fd0f406597e9b9ea09e447392d5a166dff489dea0098443b6e38a9578dee.jpg}})

When a valid SHR is received, RADIO will start storing future octets (starting with PHR) to the data memory pointed to by PACKETPTR. After the SFD octet is received, the FRAMESTART event is generated. If the CRC module is enabled, it will start updating with the second byte received (first byte in payload) and run for the full frame length. The two last bytes in the frame are not written to RAM when CRC is configured. However, if the result of the CRC is zero after running the full frame, the CRCOK event will be generated. The END event is generated when the last octet has been received and is available in data memory.

When a packet is received, a link quality indicator (LQI) is generated and appended immediately after the last received octet. When using an IEEE 802.15.4 compliant frame, this will be just after the MSDU since the FCS is not reported. In the case of a non-compliant frame, it will be appended after the full frame. The LQI reported by the hardware must be converted to the IEEE 802.15.4 range by an 8-bit saturating multiplication of 4, as shown in IEEE 802.15.4 ED measurement example on page 472. The LQI is only valid for frames equal to, or longer than, three octets. When receiving a frame, the RSSI (reported as negative dB) will be measured at three points during the reception. These three values will be sorted with the middle value selected (median 3) to be remapped within the LQI range. The following figure illustrates the LQI measurement and how the data is arranged in data memory.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## On air frame

Figure 129: IEEE 802.15.4 frame in data memory

![]({{img:images/70bc559b8a9decfa2c1ccaaa7d5b0ed51fbfe478c563925abfa3e159add05f42.jpg}})

A shortcut has been added between the FRAMESTART event and the BCSTART task. This can be used to trigger a BCMATCH event after N bits, such as when inspecting the MAC addressing fields.

## 8.17.12.8 Interframe spacing (IFS)

IEEE 802.15.4 defines a specific time that is allotted for the MAC sublayer to process received data. The interframe spacing (IFS) is used to prevent two frames from being transmitted too close together. If the transmission is requesting an acknowledgement, the space before the second frame must be at least one IFS period.

## IFS is determined to be one of the following:

- IFS = macMinSIFSPeriod (12 symbols) if MPDU ≤ aMaxSIFSFrameSize (18 octets) octets
- IFS = macMinLIFSPeriod (40 symbols) if MPDU > aMaxSIFSFrameSize

Using the efficient assisted modes in RADIO, the TIFS will be programmed with the correct value based on the frame being transmitted. If the assisted modes are not in use, the TIFS register must be updated manually. The following figure shows what IFS period is valid in both acknowledged and unacknowledged transmissions.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## Acknowledged transmission

Figure 130: Interframe spacing examples

![]({{img:images/9a4473da58074f9437eec0ad77f79d3d5b9eb2f4195a135d47985dba612f9ee7.jpg}})

## 8.17.13 EasyDMA

RADIO uses EasyDMA to read and write packets to RAM without CPU involvement.

As illustrated in RADIO block diagram on page 459, the RADIO peripheral's EasyDMA utilizes the same PACKETPTR for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before RADIO is started by the START task. The PACKETPTR register is double-buffered, meaning that it can be updated and prepared for the next transmission.

The END event indicates that the last bit has been processed by RADIO. The DISABLED event is issued to acknowledge that the DISABLE task is done.

The structure of a packet is described in detail in Packet configuration on page 459. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:

- S0
- LENGTH
- S1
- PAYLOAD

In addition, a static add-on is sent immediately after the payload.

The size of each of the listed fields in the frame is configurable (see Packet configuration on page 459), and the space occupied in RAM depends on these settings. The size of the field can be zero, as long as the resulting frame complies with the chosen RF protocol.

All fields are extended in size to align with a byte boundary in RAM. For instance, a 3-bit long field on-air will occupy 1 byte in RAM while a 9-bit long field will be extended to 2 bytes.

The packet's elements can be configured as follows:

- CI, TERM1, and TERM2 fields are only present in Bluetooth Low Energy Long Range mode
- S0 is configured through the field PCNF0.S0LEN
- LENGTH is configured through the field PCNF0.LFLEN
- S1 is configured through the field PCNF0.S1LEN
- Payload size is configured through the value in RAM corresponding to the LENGTH field
- Static add-on size is configured through the field PCNF1.STATLEN

The PCNF1.MAXLEN field configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by RADIO. This feature can be used to ensure that RADIO does not overwrite or read beyond the RAM assigned to the packet payload. This means that if the LENGTH

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

field of the packet payload exceeds PCNF1.STATLEN, and the LENGTH field in the packet specifies a packet larger than configured in PCNF1.MAXLEN, the payload will be truncated to the length specified in PCNF1.MAXLEN.

Note: The PCNF1.MAXLEN field includes the payload and the add-on, but excludes the size occupied by the S0, LENGTH, and S1 fields. This has to be taken into account when allocating RAM.

If the payload and add-on length is specified larger than PCNF1.MAXLEN, RADIO will transmit or receive in the same way as before, except the payload is now truncated to PCNF1.MAXLEN. The packet's LENGTH field will not be altered when the payload is truncated. RADIO will calculate CRC as if the packet length is equal to PCNF1.MAXLEN.

Note: If PACKETPTR is not pointing to the RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 14 for more information about the different memory regions.

The END event indicates that the last bit has been processed by RADIO. The DISABLED event is issued to acknowledge that the DISABLE task is done.

## 8.17.14 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| ---------------------- | ---------- | ----------------------- | ------------- | ------------- | ------------- | --------- | ------------------------------ |
|  |  |  | Map | Att | DMA | access |  |
| RADIO : S RADIO : NS | GLOBAL | 0x5008A000 0x4008A000 | US | S | SA | No | See pinout for GPIO options for DFE antenna switch control |


| Instance | Domain | Configuration |
| ------------ | ---------- | ------------------------------ |
| RADIO : S | GLOBAL | For the PSEL registers, use only dedicated pins on port P1 |
| RADIO : NS |  | No internal instantiation of DmaChannelPeripheral |


| Register | Offset | TZ | Description |
| ----------------- | ---------- | ------ | ------------------------------ |
| TASKS_TXEN | 0x000 |  | Enable RADIO in TX mode |
| TASKS_RXEN | 0x004 |  | Enable RADIO in RX mode |
| TASKS_START | 0x008 |  | Start RADIO |
| TASKS_STOP | 0x00C |  | Stop RADIO |
| TASKS_DISABLE | 0x010 |  | Disable RADIO |
| TASKS_RSSISTART | 0x014 |  | Start the RSSI and take one single sample of the receive signal strength |
| TASKS_BCSTART | 0x018 |  | Start the bit counter |
| TASKS_BCSTOP | 0x01C |  | Stop the bit counter |
| TASKS_EDSTART | 0x020 |  | Start the energy detect measurement used in IEEE 802.15.4 mode |
| TASKS_EDSTOP | 0x024 |  | Stop the energy detect measurement |
| TASKS_CCASTART | 0x028 |  | Start the clear channel assessment used in IEEE 802.15.4 mode |
| TASKS_CCASTOP | 0x02C |  | Stop the clear channel assessment |
| Register | Offset | TZ | Description |
| TASKS_SOFTRESET | 0x0A4 |  | Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/ SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. |
| SUBSCRIBE_TXEN | 0x100 |  | Subscribe configuration for task TXEN |
| SUBSCRIBE_RXEN | 0x104 |  | Subscribe configuration for task RXEN |
| SUBSCRIBE_START | 0x108 |  | Subscribe configuration for task START |
| SUBSCRIBE_STOP | 0x10C |  | Subscribe configuration for task STOP |
| SUBSCRIBE_DISABLE | 0x110 |  | Subscribe configuration for task DISABLE |
| SUBSCRIBE_RSSISTART | 0x114 |  | Subscribe configuration for task RSSISTART |
| SUBSCRIBE_BCSTART | 0x118 |  | Subscribe configuration for task BCSTART |
| SUBSCRIBE_BCSTOP | 0x11C |  | Subscribe configuration for task BCSTOP |
| SUBSCRIBE_EDSTART | 0x120 |  | Subscribe configuration for task EDSTART |
| SUBSCRIBE_EDSTOP | 0x124 |  | Subscribe configuration for task EDSTOP |
| SUBSCRIBE_CCASTART | 0x128 |  | Subscribe configuration for task CCASTART |
| SUBSCRIBE_CCASTOP | 0x12C |  | Subscribe configuration for task CCASTOP |
| SUBSCRIBE_SOFTRESET | 0x1A4 |  | Subscribe configuration for task SOFTRESET |
| EVENTS_READY | 0x200 |  | RADIO has ramped up and is ready to be started |
| EVENTS_TXREADY | 0x204 |  | RADIO has ramped up and is ready to be started TX path |
| EVENTS_RXREADY | 0x208 |  | RADIO has ramped up and is ready to be started RX path |
| EVENTS_ADDRESS | 0x20C |  | Address sent or received |
| EVENTS_FRAMESTART | 0x210 |  | IEEE 802.15.4 length field received |
| EVENTS_PAYLOAD | 0x214 |  | Packet payload sent or received |
| EVENTS_END | 0x218 |  | Memory access for packet data has been completed |
| EVENTS_PHYEND | 0x21C |  | The last bit is sent on air or last bit is received |
| EVENTS_DISABLED | 0x220 |  | RADIO has been disabled |
| EVENTS_DEVMATCH | 0x224 |  | A device address match occurred on the last received packet |
| EVENTS_DEVMISS | 0x228 |  | No device address match occurred on the last received packet |
| EVENTS_CRCOK | 0x22C |  | Packet received with CRC ok |
| EVENTS_CRCERROR | 0x230 |  | Packet received with CRC error |
| EVENTS_BCMATCH | 0x238 |  | Bit counter reached bit count value |
| EVENTS_EDEND | 0x23C |  | Sampling of energy detection complete (a new ED sample is ready for readout from the |
| EVENTS_EDSTOPPED | 0x240 |  | The sampling of energy detection has stopped |
| EVENTS_CCAIDLE | 0x244 |  | Wireless medium in idle - clear to send |
| EVENTS_CCABUSY | 0x248 |  | Wireless medium busy - do not send |
| EVENTS_CCASTOPPED | 0x24C |  | The CCA has stopped |
| EVENTS_RATEBOOST | 0x250 |  | Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit |
| EVENTS_MHRMATCH | 0x254 |  | MAC header match found |
| EVENTS_SYNC | 0x258 |  | Initial sync detected |
| EVENTS_CTEPRESENT | 0x25C |  | CTEInfo byte is received |
| PUBLISH_READY | 0x300 |  | Publish configuration for event READY |
| PUBLISH_TXREADY | 0x304 |  | Publish configuration for event TXREADY |
| PUBLISH_RXREADY | 0x308 |  | Publish configuration for event RXREADY |
| PUBLISH_ADDRESS | 0x30C |  | Publish configuration for event ADDRESS |
| PUBLISH_FRAMESTART | 0x310 |  | Publish configuration for event FRAMESTART |
| PUBLISH_PAYLOAD | 0x314 |  | Publish configuration for event PAYLOAD |
| PUBLISH_END | 0x318 |  | Publish configuration for event END |
| PUBLISH_PHYEND | 0x31C |  | Publish configuration for event PHYEND |
| PUBLISH_DISABLED | 0x320 |  | Publish configuration for event DISABLED |
| PUBLISH_DEVMATCH | 0x324 |  | Publish configuration for event DEVMATCH |
| PUBLISH_DEVMISS | 0x328 |  | Publish configuration for event DEVMISS |
| PUBLISH_CRCOK | 0x32C 0x330 |  | Publish configuration for event CRCOK Publish configuration for event CRCERROR |
| PUBLISH_CRCERROR |  |  |  |
| PUBLISH_BCMATCH | 0x338 |  | Publish configuration for event BCMATCH |
| Register | Offset | TZ | Description |
| PUBLISH_EDEND | 0x33C |  | Publish configuration for event EDEND |
| PUBLISH_EDSTOPPED | 0x340 |  | Publish configuration for event EDSTOPPED |
| PUBLISH_CCAIDLE | 0x344 |  | Publish configuration for event CCAIDLE |
| PUBLISH_CCABUSY | 0x348 |  | Publish configuration for event CCABUSY |
| PUBLISH_CCASTOPPED | 0x34C |  | Publish configuration for event CCASTOPPED |
| PUBLISH_RATEBOOST | 0x350 |  | Publish configuration for event RATEBOOST |
| PUBLISH_MHRMATCH | 0x354 |  | Publish configuration for event MHRMATCH |
| PUBLISH_SYNC | 0x358 |  | Publish configuration for event SYNC |
| PUBLISH_CTEPRESENT | 0x35C |  | Publish configuration for event CTEPRESENT |
| SHORTS | 0x400 |  | Shortcuts between local events and tasks |
| INTENSET00 | 0x488 |  | Enable interrupt |
| INTENCLR00 | 0x490 |  | Disable interrupt |
| INTENSET10 | 0x4A8 |  | Enable interrupt |
| INTENCLR10 | 0x4B0 |  | Disable interrupt |
| MODE | 0x500 |  | Data rate and modulation |
| STATE | 0x520 |  | Current radio state |
| EDCTRL | 0x530 |  | IEEE 802.15.4 energy detect control |
| EDSAMPLE | 0x534 |  | IEEE 802.15.4 energy detect level |
| CCACTRL | 0x538 |  | IEEE 802.15.4 clear channel assessment control |
| DATAWHITE | 0x540 |  | Data whitening configuration |
| TIMING | 0x704 |  | Timing |
| FREQUENCY | 0x708 |  | Frequency |
| TXPOWER | 0x710 |  | Output power |
| TIFS | 0x714 |  | Interframe spacing in μs |
| RSSISAMPLE | 0x718 |  | RSSI sample |
| FREQFINETUNE | 0x0804 |  | Fine tuning of the RF frequency |
| FECONFIG | 0x908 |  | Config register |
| DFEMODE | 0xD00 |  | Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure |
| DFESTATUS | 0xD04 |  | DFE status information |
| DFECTRL1 | 0xD10 |  | Various configuration for Direction finding Start offset for Direction finding |
| DFECTRL2 SWITCHPATTERN | 0xD14 0xD28 |  | GPIO patterns to be used for each antenna |
| CLEARPATTERN | 0xD2C |  | Clear the GPIO pattern array for antenna control |
| PSEL.DFEGPIO[n] | 0xD30 |  | Pin select for DFE pin n |
| DFEPACKET.PTR | 0xD50 |  | Data pointer |
| DFEPACKET.MAXCNT |  |  | Maximum number of bytes to transfer |
|  | 0xD54 |  | transaction |
| DFEPACKET.AMOUNT | 0xD58 |  | Number of bytes transferred in the last |
| CRCSTATUS | 0xE0C |  | CRC status |
| RXMATCH | 0xE10 |  | Received address |
| RXCRC | 0xE14 |  | CRC field of previously received packet |
| DAI | 0xE18 |  | Device address match index |
| PDUSTAT | 0xE1C |  | Payload status |
| PCNF0 | 0xE20 |  | Packet configuration register 0 |
| PCNF1 | 0xE28 |  | Packet configuration register 1 |
| BASE0 | 0xE2C |  | Base address 0 |
| BASE1 | 0xE30 |  | Base address 1 |
| PREFIX0 | 0xE34 |  | Prefixes bytes for logical addresses 0-3 |
| PREFIX1 | 0xE38 |  | Prefixes bytes for logical addresses 4-7 |
| TXADDRESS | 0xE3C |  | Transmit address select |
| CRCCNF | 0xE44 |  | CRC configuration |
| CRCPOLY | 0xE48 |  | CRC polynomial |
| Register | Offset | TZ | Description |
| CRCINIT | 0xE4C |  | CRC initial value |
| DAB[n] | 0xE50 |  | Device address base segment n |
| DAP[n] | 0xE70 |  | Device address prefix n |
| DACNF | 0xE90 |  | Device address match configuration |
| BCC | 0xE94 |  | Bit counter compare |
| CTESTATUS | 0xEA4 |  | CTEInfo parsed from received packet |
| MHRMATCHCONF | 0xEB4 |  | Search pattern configuration |
| MHRMATCHMASK | 0xEB8 |  | Pattern mask |
| SFD | 0xEBC |  | IEEE 802.15.4 start of frame delimiter |
| CTEINLINECONF | 0xEC0 |  | Configuration for CTE inline mode |
| PACKETPTR | 0xED0 |  | Packet pointer |
| CSTONES.MODE | 0x1000 |  | Selects the mode(s) that are activated on the start signal |
| CSTONES.NUMSAMPLES | 0x1004 |  | Number of input samples at 2MHz sample rate |
| CSTONES.NEXTFREQUENCY | 0x1008 |  | The value of FREQUENCY that will be used in the next step |
| CSTONES.FFOIN | 0x100C |  | Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived from CnAcc (autocorrelation of the scaled input signal) value |
| CSTONES.FFOSOURCE | 0x1010 |  | Source of FFO |
| CSTONES.FAEPEER | 0x1014 |  | FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. |
| CSTONES.PHASESHIFT | 0x1018 |  | Parameter used in TPM, provided by software |
| CSTONES.NUMSAMPLESCOEFF | 0x101C |  | Parameter used in TPM, provided by software |
| CSTONES.PCT16 | 0x1020 |  | Mean magnitude and mean phase converted to IQ |
| CSTONES.MAGPHASEMEAN | 0x1024 |  | Mean magnitude and phase of the signal before it is converted to PCT16 |
| CSTONES.IQRAWMEAN | 0x1028 |  | Mean of IQ values |
| CSTONES.MAGSTD | 0x102C |  | Magnitude standard deviation approximation |
| CSTONES.CNACC | 0x1030 |  | Output of the autocorrelation of the accumulated IQ signal |
| CSTONES.FFOEST | 0x1034 |  | FFO estimate |
| CSTONES.DOWNSAMPLE | 0x1038 |  | Turn on/off down sample of input IQ-signals |
| CSTONES.FINETUNENEXT | 0x103C |  | Number of full ADPLL finetune steps |
| CSTONES.CFOPHASE | 0x1040 |  | Cordic output of CnAcc |
| CSTONES.FREQOFFSET | 0x1044 |  | Frequency offset estimate |
| CSTONES.PCT11 | 0x1048 |  | Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023]. |
| CSTONES.LFAENEXT | 0x104C |  | Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values limited to [-64,63] with units 7.6294 Hz. |
| RTT.CONFIG | 0x1050 |  | RTT Config. |
| RTT.SEGMENT01 | 0x1054 |  | RTT segments 0 and 1 |
| RTT.SEGMENT23 | 0x1058 |  | RTT segments 2 and 3 |
| RTT.SEGMENT45 | 0x105C |  | RTT segments 4 and 5 |
| RTT.SEGMENT67 | 0x1060 |  | RTT segments 6 and 7 |

## 8.17.14.1 TASKS\_TXEN

Address offset: 0x000

Enable RADIO in TX mode

![]({{img:images/a3d4c2f95c6b4b8ac0499f8123905746936e66f81d0c8aecf73f232378c73e87.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | W TASKS_TXEN |  | Enable RADIO in TX mode |
|  |  | Trigger | 1 Trigger task |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.17.14.2 TASKS\_RXEN

Address offset: 0x004

Enable RADIO in RX mode

![]({{img:images/825774a708eb2581b9732d028337a8408d00274c6d18dde0e003c5b420164417.jpg}})

## 8.17.14.3 TASKS\_START

Address offset: 0x008

Start RADIO

![]({{img:images/252c8fb74aaed998e292c6b37fb3f49353f58c55eaddf7a21ecf28ffef290ab9.jpg}})

## 8.17.14.4 TASKS\_STOP

Address offset: 0x00C

Stop RADIO

![]({{img:images/4ad57b227599ed4798d6e409c250fc3c9fb8ea5e9c9c8729bf11dcd612da2017.jpg}})

## 8.17.14.5 TASKS\_DISABLE

Address offset: 0x010

Disable RADIO

![]({{img:images/594f02969844e0946bd206049559043e1bc0df1f1ebb04c5bef4d19ba2306e4d.jpg}})

## 8.17.14.6 TASKS\_RSSISTART

Address offset: 0x014

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

Start the RSSI and take one single sample of the receive signal strength

![]({{img:images/8cca94e41cad6f983081e53bcdfc318151fdfcacde12b0e04ea52f5c23b594e6.jpg}})

## 8.17.14.7 TASKS\_BCSTART

Address offset: 0x018

Start the bit counter

![]({{img:images/2e9f02708806d2014995d69d5b203c414d07680f446305944a862c8fa5223db2.jpg}})

## 8.17.14.8 TASKS\_BCSTOP

Address offset: 0x01C

Stop the bit counter

![]({{img:images/49d4fa4e8f9fc5840dd635d2cc0d54216fd2a25218d8c86efdb3d57a654f7ea4.jpg}})

## 8.17.14.9 TASKS\_EDSTART

Address offset: 0x020

Start the energy detect measurement used in IEEE 802.15.4 mode

![]({{img:images/8e2f5a3dfb58b6bdcf3ab8dfcf6e7e6dedefc7c5149dbec736b10485866fdc87.jpg}})

## 8.17.14.10 TASKS\_EDSTOP

Address offset: 0x024

Stop the energy detect measurement

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/9d13eae1ec153d430ddbc5955c4b270c04c4a91b70fc39df482b38aff3ddf77f.jpg}})

## 8.17.14.11 TASKS\_CCASTART

Address offset: 0x028

Start the clear channel assessment used in IEEE 802.15.4 mode

![]({{img:images/f8f099fbcc3640ee4c52ad8b9456959bd1bb88892816bc5c3eefc3ff4dd4dd26.jpg}})

## 8.17.14.12 TASKS\_CCASTOP

Address offset: 0x02C

Stop the clear channel assessment

![]({{img:images/f3fdcbbf64879b6914011590fea0f46e1edcbabdc3968275997e2a1ef8567b2f.jpg}})

## 8.17.14.13 TASKS\_SOFTRESET

## Address offset: 0x0A4

Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state.

![]({{img:images/7868d4fb06a9b2b1b103df90ca3762538ab91ed296f240d96857f9e48a1a4510.jpg}})

## 8.17.14.14 SUBSCRIBE\_TXEN

Address offset: 0x100

Subscribe configuration for task TXEN

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/bf4e6c15e904c5d71c4c4917c49b06a074e1f4e6a9f1f46cd160d90866b850d5.jpg}})

## 8.17.14.15 SUBSCRIBE\_RXEN

Address offset: 0x104

Subscribe configuration for task RXEN

![]({{img:images/5456226607d6ad3c917f3f769e3d5c3b07aad8ae1e7e7cc0107880607fe183f1.jpg}})

## 8.17.14.16 SUBSCRIBE\_START

Address offset: 0x108

Subscribe configuration for task START

![]({{img:images/0f476d59410136b4b5e449080432ea2191ac291daffa99b83f9947915a1b6ac6.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that task START will subscribe to |
| B | RW | EN |  |  |
|  |  | Disabled | 0 | Disable subscription |
|  |  | Enabled | 1 | Enable subscription |

## 8.17.14.17 SUBSCRIBE\_STOP

Address offset: 0x10C

Subscribe configuration for task STOP

![]({{img:images/cbcd1a0d1032419ffcdce26e2e9f85b35abfa4c02a651be6eaafcd70807817e3.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task STOP will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.17.14.18 SUBSCRIBE\_DISABLE

Address offset: 0x110

Subscribe configuration for task DISABLE

![]({{img:images/6b12b95ac73e4717403349636cff67167a195ca9895e3ab29c5bc5bb567ad7b5.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task DISABLE will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.17.14.19 SUBSCRIBE\_RSSISTART

Address offset: 0x114

Subscribe configuration for task RSSISTART

![]({{img:images/3685314d4e9683cc2d1c50e711bc96d3188fcf90cfe864655b0d2d89d888d99f.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task RSSISTART will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

## 8.17.14.20 SUBSCRIBE\_BCSTART

Address offset: 0x118

Subscribe configuration for task BCSTART

![]({{img:images/1def9d152caab16cfb870dbdda5cdecaabe18639f21406f32d66ec0e0b067a94.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task BCSTART will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.17.14.21 SUBSCRIBE\_BCSTOP

Address offset: 0x11C

Subscribe configuration for task BCSTOP

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/53faa771e214a0fac2df38e5ee4b60811098dfb414572dd0449a081121d200ec.jpg}})

## 8.17.14.22 SUBSCRIBE\_EDSTART

Address offset: 0x120

Subscribe configuration for task EDSTART

![]({{img:images/365b2109d6a55f86776ac3d92671a99347da2b9c4983531097b9898f24de1789.jpg}})

## 8.17.14.23 SUBSCRIBE\_EDSTOP

Address offset: 0x124

Subscribe configuration for task EDSTOP

![]({{img:images/bcd0de3a8c5b52bf24416383126f9fdb75d4c49334c606f2056a8d0aaf089e5d.jpg}})

## 8.17.14.24 SUBSCRIBE\_CCASTART

Address offset: 0x128

Subscribe configuration for task CCASTART

![]({{img:images/2b69ca8a9de433b91ffe1c17302aaff610d0bff3d0593faff74dfe2b56cfc0a6.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task CCASTART will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.17.14.25 SUBSCRIBE\_CCASTOP

Address offset: 0x12C

Subscribe configuration for task CCASTOP

![]({{img:images/9d7167c53733b2de719b554f37af8c12ac47ba8dae82c3ba6b646a241169689a.jpg}})

## 8.17.14.26 SUBSCRIBE\_SOFTRESET

Address offset: 0x1A4

Subscribe configuration for task SOFTRESET

![]({{img:images/d30886a8f45ab9fa3f9fbb1ab1afec5ea72a157aceef2d96549b267096783311.jpg}})

## 8.17.14.27 EVENTS\_READY

Address offset: 0x200

RADIO has ramped up and is ready to be started

![]({{img:images/c85cae8d1b4a94f5d8460a6bec72544b485d7fd57a3db72a711018f6db98a67c.jpg}})

## 8.17.14.28 EVENTS\_TXREADY

Address offset: 0x204

RADIO has ramped up and is ready to be started TX path

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/d3b744a1dbe79175077f7e982a3e276bff948a530dd200a1317b653c79e2e8c3.jpg}})

## 8.17.14.29 EVENTS\_RXREADY

Address offset: 0x208

RADIO has ramped up and is ready to be started RX path

![]({{img:images/c7b721c1befa6415318e9fa32e6d2f8e6d5675f12a16d204aff8e4da18e53144.jpg}})

## 8.17.14.30 EVENTS\_ADDRESS

Address offset: 0x20C

Address sent or received

![]({{img:images/6a032e68cd684956a1b813c62d5db67fc77c15f626fb88bf2e11fbde20c94dab.jpg}})

## 8.17.14.31 EVENTS\_FRAMESTART

Address offset: 0x210

IEEE 802.15.4 length field received

![]({{img:images/6a7f4a6720cb6fc2bbbe57c3bef7f77eae47a5edeca3cb23f50b490555e56c28.jpg}})

## 8.17.14.32 EVENTS\_PAYLOAD

Address offset: 0x214

Packet payload sent or received

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/56d95c72430b6f93be12bf2919c3dbb1a80b67069dfeb9014c9738c126a91390.jpg}})

## 8.17.14.33 EVENTS\_END

Address offset: 0x218

Memory access for packet data has been completed

In TX: Last byte to be transmitted has been fetched from RAM

In RX: Last byte received on air has been stored to RAM

![]({{img:images/107ebf6ef7ef10ea4646d0aba5a0879df03fe1c11e3e183d7e21345e7dedd85b.jpg}})

## 8.17.14.34 EVENTS\_PHYEND

Address offset: 0x21C

The last bit is sent on air or last bit is received

![]({{img:images/9e4031d4825bfd252ff04b2353283264f951720f58b402e64160b22e75eaa7da.jpg}})

## 8.17.14.35 EVENTS\_DISABLED

Address offset: 0x220

RADIO has been disabled

![]({{img:images/dd2362d1bf66c7ceaf7437b8678aa88901026da98c6a66da90cbf434baf59a6c.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.17.14.36 EVENTS\_DEVMATCH

Address offset: 0x224

A device address match occurred on the last received packet

![]({{img:images/9f339411b752c5ec17fbcf0946819a8dc08964d89534fab759536a366495a94c.jpg}})

## 8.17.14.37 EVENTS\_DEVMISS

Address offset: 0x228

No device address match occurred on the last received packet

![]({{img:images/6ed945a4da88c6d93df782fea46307195144a14b8bb8541cea2dbfad9f37210a.jpg}})

## 8.17.14.38 EVENTS\_CRCOK

Address offset: 0x22C

Packet received with CRC ok

![]({{img:images/0aee3f9dc4f19a9ec4d1f2d2debe854d4648cf0a6c9daba94e21804d83f5d353.jpg}})

## 8.17.14.39 EVENTS\_CRCERROR

Address offset: 0x230

Packet received with CRC error

![]({{img:images/22fddfec9facd36680375166a71d0bb74f172d94e10221afe03572c42cb79aa4.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.17.14.40 EVENTS\_BCMATCH

## Address offset: 0x238

Bit counter reached bit count value

Bit counter value is specified in the RADIO.BCC register

![]({{img:images/bdb365534f6606679d7a505d2a1e80900ab1e5192457b29a1a543407a82af36d.jpg}})

## 8.17.14.41 EVENTS\_EDEND

## Address offset: 0x23C

Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register)

![]({{img:images/5d80aeb266c98747b267c80e16e31ab0f043c90761704433943b6ed63b075947.jpg}})

## 8.17.14.42 EVENTS\_EDSTOPPED

Address offset: 0x240

The sampling of energy detection has stopped

![]({{img:images/60c1008059c611ba0fa0a22aadc70f1657eeca5b1331f4a90eb8578e3d33df31.jpg}})

## 8.17.14.43 EVENTS\_CCAIDLE

Address offset: 0x244

Wireless medium in idle - clear to send

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/b2379f6572e50dac79363d15b796a02688b888da8cf9072f29abb7c206696179.jpg}})

## 8.17.14.44 EVENTS\_CCABUSY

Address offset: 0x248

Wireless medium busy - do not send

![]({{img:images/76903f9776f42fb9dd96aec5723cc9d12d5ee4772b954323c4f60558257d023e.jpg}})

## 8.17.14.45 EVENTS\_CCASTOPPED

Address offset: 0x24C

The CCA has stopped

![]({{img:images/5809bbe599f1c7b7bdf87dc18d23537243247fbdb0f12e6c191468cbb9057185.jpg}})

## 8.17.14.46 EVENTS\_RATEBOOST

Address offset: 0x250

Ble\_LR CI field received, receive mode is changed from Ble\_LR125Kbit to Ble\_LR500Kbit

![]({{img:images/9797ac3a769fd0df9b93cdf2ca04576db1ad73fe234a9d82584a3fff41ca89e0.jpg}})

## 8.17.14.47 EVENTS\_MHRMATCH

Address offset: 0x254

MAC header match found

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/40c8fa26bd654359744900414191de8279177b8e2dda5df1cbfa7e6481d4c7b8.jpg}})

## 8.17.14.48 EVENTS\_SYNC

Address offset: 0x258

Initial sync detected

MODE=Ble\_LR125Kbit, Ble\_LR500Kbit, or Ieee802154\_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered.

For MODE=Nrf\_1Mbit, Nrf\_2Mbit, Ble\_1Mbit, or Ble\_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode.

It is also possible that the event is not generated, or not generated before the ADDRESS event.

![]({{img:images/7c3ec6179a6b5281e729c73160655970aec4e3332a666c5daaf88f598f9ff4aa.jpg}})

## 8.17.14.49 EVENTS\_CTEPRESENT

Address offset: 0x25C

CTEInfo byte is received

![]({{img:images/7a61b9d4302e747438122f06cf4ed622e5c8864a80d71cbda97608f5b032243e.jpg}})

## 8.17.14.50 PUBLISH\_READY

Address offset: 0x300

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## Publish configuration for event READY

![]({{img:images/7b0ace3a512f59f13122aad2df32c199e64138f07eae358cecc06b66921c8927.jpg}})

## 8.17.14.51 PUBLISH\_TXREADY

Address offset: 0x304

Publish configuration for event TXREADY

![]({{img:images/ea61e54d2b9839001bdf1ef2632c34e97c65fd9c30350bfafc29c467013de046.jpg}})

## 8.17.14.52 PUBLISH\_RXREADY

Address offset: 0x308

Publish configuration for event RXREADY

![]({{img:images/8261e385431239eaa793de00d23a14910ecc9da86705e8b864b8d5e57a7f3d9e.jpg}})

## 8.17.14.53 PUBLISH\_ADDRESS

Address offset: 0x30C

Publish configuration for event ADDRESS

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/aeee8d865f50f1eb78c71260424e6e7b6690a679982c3aa423c5af9cf44e04f6.jpg}})

## 8.17.14.54 PUBLISH\_FRAMESTART

Address offset: 0x310

Publish configuration for event FRAMESTART

![]({{img:images/1b4c6315c53d3e580bad8a90f227deaa34fb2e8340f7af8f8dbb5b83d40aaec9.jpg}})

## 8.17.14.55 PUBLISH\_PAYLOAD

Address offset: 0x314

Publish configuration for event PAYLOAD

![]({{img:images/62e2a3c13ac73965785c6780feba306bfa4c20b9bc0d3a4bbe6770516f49fe13.jpg}})

## 8.17.14.56 PUBLISH\_END

Address offset: 0x318

Publish configuration for event END

In TX: Last byte to be transmitted has been fetched from RAM

In RX: Last byte received on air has been stored to RAM

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/1ed4abdd9d03d5bdfe89e2456143bfe243dc5d46162e4eb3619f1873c4f45c54.jpg}})

## 8.17.14.57 PUBLISH\_PHYEND

Address offset: 0x31C

Publish configuration for event PHYEND

![]({{img:images/291d52d4828debff478f31567b757313665dfba874ad6524aa5bb98a48d343da.jpg}})

## 8.17.14.58 PUBLISH\_DISABLED

Address offset: 0x320

Publish configuration for event DISABLED

![]({{img:images/729d336194bd7579003b7ae90054a4c92010a1af8b4d7345e67f088b547eee28.jpg}})

## 8.17.14.59 PUBLISH\_DEVMATCH

Address offset: 0x324

Publish configuration for event DEVMATCH

![]({{img:images/f985c9b32e3c82c831c184b26a79e7299d56ec37474767f843d0315ff6486b75.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event DEVMATCH will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

![]({{img:images/a0a44d2b35b0d413dc799ff5e02e910655b9c5213e7877696945759ccce904b8.jpg}})

## 8.17.14.60 PUBLISH\_DEVMISS

Address offset: 0x328

Publish configuration for event DEVMISS

![]({{img:images/8cfbe6e06a19b37bfa6997c97f42958bebb15d2f161cd45204ce6a65f00c6f06.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that event DEVMISS will publish to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable publishing<br>1 Enable publishing |

## 8.17.14.61 PUBLISH\_CRCOK

Address offset: 0x32C

Publish configuration for event CRCOK

![]({{img:images/615f2ad15a9c6c1f64c9d9d0a714940db27b18c4d535e31d4709658a9bed6367.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event CRCOK will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.17.14.62 PUBLISH\_CRCERROR

Address offset: 0x330

Publish configuration for event CRCERROR

![]({{img:images/1dc4255c226b9503c020b70f244ea8341f66b57c91f92e8c135ce9c82b61d2a5.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event CRCERROR will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.17.14.63 PUBLISH\_BCMATCH

Address offset: 0x338

Publish configuration for event BCMATCH

Bit counter value is specified in the RADIO.BCC register

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/61a90f55363c6c8d0fa9a35291f79b43216211f780ed9303b0df873d25631066.jpg}})

## 8.17.14.64 PUBLISH\_EDEND

Address offset: 0x33C

Publish configuration for event EDEND

![]({{img:images/1c1a47983caade58dd97d24a943616feab348a19054c630f9f35b2954c4374ad.jpg}})

## 8.17.14.65 PUBLISH\_EDSTOPPED

Address offset: 0x340

Publish configuration for event EDSTOPPED

![]({{img:images/f2454fb904797197e3d8466654a397d49e4a5b01a2e0f847dcbd441c58efb254.jpg}})

## 8.17.14.66 PUBLISH\_CCAIDLE

Address offset: 0x344

Publish configuration for event CCAIDLE

![]({{img:images/90b1c7ff2ab2053a28533127b0b0552938c8116a19d1b69fe943e82d3f17511e.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event CCAIDLE will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.17.14.67 PUBLISH\_CCABUSY

Address offset: 0x348

Publish configuration for event CCABUSY

![]({{img:images/26e985d2a5178de9d69d626d1c15b086db048375738af262f1b27fa33a712a12.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that event CCABUSY will publish to |
| B | RW | EN |  |  |
|  |  | Disabled | 0<br>Enabled 1 | Disable publishing<br>Enable publishing |

## 8.17.14.68 PUBLISH\_CCASTOPPED

Address offset: 0x34C

Publish configuration for event CCASTOPPED

![]({{img:images/807894bfa9306d8a3e61aebc3eed0fd1abc6447b53549a1f530b038f0a1a8835.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event CCASTOPPED will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.17.14.69 PUBLISH\_RATEBOOST

Address offset: 0x350

Publish configuration for event RATEBOOST

![]({{img:images/fbe22bde3265ad67fc2b4535ef22a2c97499657d788fae46fc138a15a7ac82b3.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event RATEBOOST will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.17.14.70 PUBLISH\_MHRMATCH

Address offset: 0x354

Publish configuration for event MHRMATCH

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/db46c122ed9343614bf0b0939699f1d2c8bfd7994e80500f4adef726f5d64c89.jpg}})

## 8.17.14.71 PUBLISH\_SYNC

Address offset: 0x358

Publish configuration for event SYNC

MODE=Ble\_LR125Kbit, Ble\_LR500Kbit, or Ieee802154\_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered.

For MODE=Nrf\_1Mbit, Nrf\_2Mbit, Ble\_1Mbit, or Ble\_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode.

It is also possible that the event is not generated, or not generated before the ADDRESS event.

![]({{img:images/226740a19e20f86cc7e1a96f9fb9d69d0b213a51feeea570cedc93a64f1e71e2.jpg}})

## 8.17.14.72 PUBLISH\_CTEPRESENT

Address offset: 0x35C

Publish configuration for event CTEPRESENT

![]({{img:images/860faf4b161c6bc1358de3184a8c3061bdd7ff47dc253e6c803148c98fa1d9ae.jpg}})

## 8.17.14.73 SHORTS

Address offset: 0x400

Shortcuts between local events and tasks

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

| Bit | number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ----------------------- | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID |  |  |  | Q P O N M L K J I | C B A | C B A | C B A | C B A | C B A | C B A | C B A | C B A | C B A | C B A | C B A |  |  |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description | between event | between event | between event | between event | between event | between event | between event | between event | between event | between event | between event |  |  |
| A RW | READY_START | Disabled | 0 | Disable | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut | READY shortcut |  |  |
|  |  | Enabled | 1 |  | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut |  |  |
| B | RW DISABLED_TXEN | Disabled | 0 |  | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut | between event DISABLED shortcut |  |  |
|  | DISABLED_RXEN | Enabled Disabled | 1 | Enable Shortcut | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED | shortcut between event DISABLED |  |  |
| C | RW | Enabled | 1 |  | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut |  |  |
| D | RW ADDRESS_RSSISTART | Disabled Enabled Disabled | 0 0 |  | shortcut Shortcut between event ADDRESS shortcut | Disable Enable Shortcut Disable | shortcut between shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut | shortcut Shortcut between event ADDRESS shortcut |  |  |
| E | END_START | Enabled Disabled | 0 1 0 1 |  | event END and task START event ADDRESS and task BCSTART | Enable | shortcut | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART | event END and task START event ADDRESS and task BCSTART |  |  |
| F | RW RW ADDRESS_BCSTART | Enabled RXREADY_CCASTART Disabled Enabled | 1 0 1 0 1 | Enable shortcut Shortcut between Disable shortcut Enable shortcut Shortcut between Disable shortcut Enable shortcut Shortcut between Disable shortcut | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART | RXREADY and task CCASTART |  |  |
| G | RW RW CCAIDLE_TXEN | Disabled Enabled Disabled | 0 |  | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE | CCAIDLE and task DISABLE |  |  |
| H |  | CCABUSY_DISABLE | 1 |  | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task | Disable shortcut shortcut between event FRAMESTART and task |  |  |
| I | RW | Enabled |  |  | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY | Shortcut between event CCABUSY |  |  |
|  |  |  |  |  | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable | Enable Shortcut Disable |  |  |
|  |  | Disabled | 1 |  | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART | event READY and task EDSTART |  |  |
| J | RW | FRAMESTART_BCSTART Enabled | 0 |  | BCSTART shortcut shortcut | Enable | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut | BCSTART shortcut shortcut |  |  |
| K | RW READY_EDSTART<br>EDEND_DISABLE | Disabled<br>Enabled | 0 1<br>0 |  | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut | Shortcut between Disable shortcut Enable shortcut |  |  |
| L | RW CCAIDLE_STOP | Disabled Enabled Disabled | 1 0 1 |  | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Disable Enable | shortcut shortcut | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP | Shortcut between event EDEND and task DISABLE Disable shortcut Enable shortcut Shortcut between event CCAIDLE and task STOP |  |  |
| M RW | RW TXREADY_START | Enabled Disabled Enabled | 0 1 |  | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START | event TXREADY and task START event RXREADY and task START |  |  |
| N | RW RXREADY_START | Enabled | 0 1 |  | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE | event PHYEND and task DISABLE |  |  |
| O | PHYEND_DISABLE | Disabled | 0 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
| P |  |  |  |  | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut |  |  |
|  |  |  | 1 |  | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut |  |  |
|  | RW | Enabled |  |  | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START | between event PHYEND and task START |  |  |
|  |  |  |  |  | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut | Enable shortcut |  |  |
|  |  | Disabled |  |  | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut | Shortcut between Disable shortcut |  |  |
| Q |  | Disabled |  |  | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut | Shortcut |  |  |
|  | RW<br>PHYEND_START |  | 0 | Disable | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut | shortcut |  |  |

![]({{img:images/6561191bfce692a09adc0f499f2d6618ad8e9dc8f7521d343b9ed5593c79dc77.jpg}})

## 8.17.14.74 INTENSET00

Address offset: 0x488

Enable interrupt

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 0 |
| ------------------ | ------------------ | ---------- | ------------------------------ | ------------------------------ |
| ID |  |  |  | W V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | READY |  |  | Write '1' to enable interrupt for event READY |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| B | TXREADY |  |  | Write '1' to enable interrupt for event TXREADY |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| C | RXREADY |  |  | Write '1' to enable interrupt for event RXREADY |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| D | ADDRESS |  |  | Write '1' to enable interrupt for event ADDRESS |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| E | FRAMESTART |  |  | Write '1' to enable interrupt for event FRAMESTART |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| F | PAYLOAD |  |  | Write '1' to enable interrupt for event PAYLOAD |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| G | END |  |  | Write '1' to enable interrupt for event END<br>In TX: Last byte to be transmitted has been fetched from RAM<br>In RX: Last byte received on air has been stored to RAM |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| H | PHYEND |  |  | Write '1' to enable interrupt for event PHYEND |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| I | DISABLED |  |  | Write '1' to enable interrupt for event DISABLED |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| Bit number | Bit number | Bit number | 31 30 29 28 | 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ID | ID | ID | W V U T S R Q P O N M L K J I H G F E D C B A<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | W V U T S R Q P O N M L K J I H G F E D C B A<br>0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| J | RW DEVMATCH |  |  | Write '1' to enable interrupt for event DEVMATCH |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| K | RW DEVMISS |  |  | Write '1' to enable interrupt for event DEVMISS |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| L | RW CRCOK |  |  | Write '1' to enable interrupt for event CRCOK |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| M | RW CRCERROR |  |  | Write '1' to enable interrupt for event CRCERROR |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| N | RW BCMATCH |  |  | Write '1' to enable interrupt for event BCMATCH<br>Bit counter value is specified in the RADIO.BCC register |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| O | RW EDEND |  |  | Write '1' to enable interrupt for event EDEND |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
| P | RW EDSTOPPED | Enabled<br>Set<br>Disabled | 1 | Read: Enabled Write '1' to enable interrupt for event EDSTOPPED |
|  |  | Enabled | 0 1 | Read: Disabled Read: Enabled |
|  | CCAIDLE |  | 1 | Enable |
| Q | RW |  |  | Write '1' to enable interrupt for event CCAIDLE |
|  |  | Enabled | 1 | Read: Disabled |
| R | CCABUSY |  |  | Read: Enabled |
|  | RW | Set<br>Disabled | 1<br>0 | Enable<br>event CCABUSY<br>Write '1' to enable interrupt for |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| S | RW CCASTOPPED |  |  | Write '1' to enable interrupt for event CCASTOPPED |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| T | RW RATEBOOST |  |  | Write '1' to enable interrupt for event RATEBOOST |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| U | RW MHRMATCH |  |  | Write '1' to enable interrupt for event MHRMATCH |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/6b40c617ea2e57123469c47ec0f9ae6024ff3773a0ab1418890f10c4ca522151.jpg}})

| Bit number |
| -------------- |

## 8.17.14.75 INTENCLR00

Address offset: 0x490

Disable interrupt

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |  |  |  |  |  |  |  |  |  | 0 | 0 |
| ------------------ | ------------------ | ---------- | ------------------------------ | ------- | ------- | --------- | ---------------- | --------------- | ------------------ | ---------- | ---------- | ---------- | ---------- | ---------- |
| ID |  |  |  |  |  | W | V U T S R Q | P O N | M L K | F | J I H G | E D C | B A | B A |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 0 | 0 0 0 | 0 0 0 | 0 | 0 0 0 0 | 0 0 0 0 0 | 0 0 0 | 0 0 0 | 0 0 0 | 0 0 | 0 0 | 0 0 |
| ID | R/W Field | Value ID | Value |  |  |  | Description |  |  |  |  |  |  |  |
| A | RW READY |  |  |  |  | Write | '1' to disable | interrupt for | event READY |  |  |  |  |  |
|  |  | Clear<br>Disabled | 1<br>0 |  |  |  | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
|  |  | Enabled | 1 |  |  | Read:<br>Read: | Disabled<br>Enabled | Disabled | Disabled | Disabled | Disabled | Disabled | Disabled | Disabled |
| B | RW TXREADY | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable<br>Disabled<br>Enabled | interrupt for | event TXREADY |  |  |  |  |  |
| C | RW RXREADY | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable<br>Disabled<br>Enabled | interrupt for | event RXREADY |  |  |  |  |  |
| D | RW ADDRESS | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable<br>Disabled<br>Enabled | interrupt for | event ADDRESS |  |  |  |  |  |
| E | RW FRAMESTART | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable<br>Disabled<br>Enabled | interrupt for | event FRAMESTART |  |  |  |  |  |
| F | RW | PAYLOAD<br>Clear | 1 |  |  | Write<br>Disable | '1' to disable | interrupt for | event PAYLOAD |  |  |  |  |  |

| Bit number |  |  | 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| -------------- | ---------------------- | ------------------------------ | ------------------- | ------------------------------ | ------------------------------ |
| ID |  |  |  | W V U T S R Q P O N M L K J I H G F E D C B | W V U T S R Q P O N M L K J I H G F E D C B |
| ID | R/W Field | Value ID | Value | Description | Description |
|  |  | Disabled | 0 | Read: Disabled | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled | Read: Enabled |
| G | RW END |  |  | Write '1' to disable interrupt for event END In TX: Last byte to be transmitted has been fetched from RAM | Write '1' to disable interrupt for event END In TX: Last byte to be transmitted has been fetched from RAM |
| H | RW PHYEND | Disabled Enabled Clear | 0 1 | In RX: Last byte received on air has been stored to RAM Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event PHYEND | Disable |
| I J RW | RW DISABLED DEVMATCH | Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled | 1 0 1 1 0 1 1 0 | Read: Read: Write Read: Read: Write '1' to disable interrupt for event DEVMATCH Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event DEVMISS Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event CRCOK Disable Read: Disabled | Disabled Enabled '1' to disable interrupt for Disable Disabled Enabled |
| K | RW DEVMISS | Clear Disabled Enabled Clear | 1 1 0 1 1 0 1 1 0 | Write '1' to disable interrupt for event CRCERROR Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event BCMATCH | Write '1' to disable interrupt for event CRCERROR Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event BCMATCH |
|  | CRCOK | Disabled Enabled | 1 0 1 |  |  |
| L | RW |  |  | Read: Enabled | Read: Enabled |
| M | RW CRCERROR | Clear Disabled |  | Bit counter value is specified in the RADIO.BCC Disable | Bit counter value is specified in the RADIO.BCC Disable |
| N | BCMATCH | Enabled | 1 | Read: Disabled Read: Enabled Write '1' to disable interrupt for event EDEND Disable | Read: Disabled Read: Enabled Write '1' to disable interrupt for event EDEND Disable |
|  | RW | Clear Disabled<br>Enabled | 1 0 1 1 0 | register | register |
| O | RW | Enabled Clear Disabled | 1 0 | Disable | Disable |
| P | EDEND | Clear Disabled |  | Read: Disabled | Read: Disabled |
|  | RW EDSTOPPED |  |  | Write '1' to disable interrupt for | Write '1' to disable interrupt for |
| Q | RW | Disabled Enabled |  |  |  |
|  |  | Clear |  | event<br>CCAIDLE | event<br>CCAIDLE |
|  |  | Enabled | 1 | Read: Disabled Read: Enabled<br>Read: Disabled Read: Enabled Write '1' to disable interrupt for event<br>Disable<br>EDSTOPPED | Read: Disabled Read: Enabled<br>Read: Disabled Read: Enabled Write '1' to disable interrupt for event<br>Disable<br>EDSTOPPED |
|  | CCAIDLE |  | 1 | Read: Enabled | Read: Enabled |

| Bit ID |  |  | number | 31 30 29 28 27 26 25 24 23 | 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 W V U T S R Q P O N M L K J I H G F E D | 2 1 C B |
| ------------------ | ------------------ | ------------ | ------------------ | ------------------------------ | ------------------------------ | ------------------ |
| Reset 0x00000000 | Reset 0x00000000 |  |  | 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 |
| ID | R/W Field | Value ID |  | Value | Description |  |
| R RW | CCABUSY |  | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | Write '1' to disable interrupt for event CCABUSY<br>Disable<br>Read: Disabled<br>Read: Enabled |  |
| S | RW | CCASTOPPED | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | Write '1' to disable interrupt for event CCASTOPPED<br>Disable<br>Read: Disabled<br>Read: Enabled |  |
| T | RW | RATEBOOST | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | Write '1' to disable interrupt for event RATEBOOST<br>Disable<br>Read: Disabled<br>Read: Enabled |  |
| U | RW | MHRMATCH | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | Write '1' to disable interrupt for event MHRMATCH<br>Disable<br>Read: Disabled<br>Read: Enabled |  |
| V | RW | SYNC | Clear<br>Disabled Enabled | 1<br>0 1 | Write '1' to disable interrupt for event SYNC<br>MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered.<br>For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or<br>Ble_2Mbit: A possible preamble and the first two bytes of the address field has been received. The in this mode.<br>event can be generated falsely also<br>the event<br>It is also possible that is not generated, or not the ADDRESS event.<br>Disable Read: Disabled<br>Read: Enabled | generated before |
| W | RW | CTEPRESENT | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | Write '1' to disable interrupt for event CTEPRESENT<br>Disable<br>Read: Disabled<br>Read: Enabled |  |
## 8.17.14.76 INTENSET10

Address offset: 0x4A8

Enable interrupt

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------------------------------ |
| ID |  | W V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW READY |  | Write '1' to enable interrupt for event READY |
|  | Set | 1 Enable |
|  | Disabled | 0 Read: Disabled |
|  | Enabled | 1 Read: Enabled |
| B RW TXREADY |  | Write '1' to enable interrupt for event TXREADY |
|  | Set | 1 Enable |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ---------------- | ------------------------------ |
| ID |  |  | W V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID Value | Description |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| C RW | RXREADY |  | Write '1' to enable interrupt for event RXREADY |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| D RW | ADDRESS |  | Write '1' to enable interrupt for event ADDRESS |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| E RW | FRAMESTART |  | Write '1' to enable interrupt for event FRAMESTART |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| F RW | PAYLOAD |  | Write '1' to enable interrupt for event PAYLOAD |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| G RW | END |  | Write '1' to enable interrupt for event END<br>In TX: Last byte to be transmitted has been fetched from RAM<br>In RX: Last byte received on air has been stored to RAM |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| H RW | PHYEND |  | Write '1' to enable interrupt for event PHYEND |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled | 1 Read: Enabled |
| I RW | DISABLED |  | Write '1' to enable interrupt for event DISABLED |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| J RW | DEVMATCH |  | Write '1' to enable interrupt for event DEVMATCH |
|  |  | Set 1 | Enable |
|  |  | Disabled | 0 Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| K RW | DEVMISS |  | Write '1' to enable interrupt for event DEVMISS |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled 1 | Read: Enabled |
| L RW | CRCOK |  | Write '1' to enable interrupt for event CRCOK |
|  |  | Set 1 | Enable |
|  |  | Disabled 0 | Read: Disabled |
|  |  | Enabled | Read: Enabled |
| M |  |  | Write '1' to enable interrupt for event CRCERROR<br>1<br>1 |
| RW | CRCERROR |  |  |
|  |  | Set | Enable |
|  |  | Disabled | 0 Read: Disabled |
|  |  | Enabled | 1 Read: Enabled |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

| Bit number |  |  | 31 30 29 28 | 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------- | ---------------------------- | ------------------------------ | --------------- | ------------------------------ | ------------------------------ |
| ID |  |  |  | W V U T S R Q P O N M L K J I H G F E D C B A | W V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0 0 0 0 ID | 0x00000000 R/W Field | Value ID | Value | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description |
| N | RW BCMATCH |  |  | Write '1' Bit counter value is specified in the RADIO.BCC register Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event EDEND | to enable interrupt for event BCMATCH |
| 0 1 O | EDEND | Set Disabled Enabled Set | 1 |  |  |
| 0 | RW | Disabled Enabled Set | 1 1 | Enable Read: Read: Write '1' Write '1' to enable interrupt for event RATEBOOST Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event MHRMATCH Enable Read: Disabled | Disabled Enabled to enable interrupt for event EDSTOPPED |
| P Q 1 0 1 R 1 0 1 | RW EDSTOPPED RW CCASTOPPED | Disabled Enabled Set Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled | 1 0 1 | Enable Read: Read: Write '1' Read: Enabled Write '1' to enable interrupt for event SYNC MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A | Disabled Enabled to enable interrupt for event CCASTOPPED |
| 1 0 1 1 0 1 T 1 | RW CCAIDLE RW CCABUSY | Disabled Enabled |  | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CCAIDLE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CCABUSY Enable Read: Read: | Disabled Enabled |
| S 0 1 U | RW RATEBOOST RW MHRMATCH |  |  | preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered. For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible preamble and the first two bytes of the address field has been received. event can be generated falsely also in this mode. | preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered. For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible preamble and the first two bytes of the address field has been received. event can be generated falsely also in this mode. |
| V |  | Set Disabled Enabled |  | possible It is also possible that the event is not generated, or not generated before<br>The | possible It is also possible that the event is not generated, or not generated before<br>The |
| 1 |  | Set Disabled Enabled | 0 | the ADDRESS event. Enable | the ADDRESS event. Enable |
|  | RW<br>SYNC |  |  | Read: Disabled | Read: Disabled |
|  | RW |  | 1 | Read: Enabled<br>Write '1' to enable interrupt for event CTEPRESENT | Read: Enabled<br>Write '1' to enable interrupt for event CTEPRESENT |
| W | CTEPRESENT | Set<br>Disabled | 1<br>0 | Enable | Enable |
|  |  | Enabled | 1 | Read: Disabled<br>Read: Enabled | Read: Disabled<br>Read: Enabled |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.17.14.77 INTENCLR10

Address offset: 0x4B0

Disable interrupt

| Bit number |  |  | 31 30 29 | 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| -------------- | --------------- | ---------- | ------------ | ------------------------------ |
| Reset | 0x00000000 |  | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW READY |  |  | Write '1' to disable interrupt for event READY |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| B | RW TXREADY |  |  | Write '1' to disable interrupt for event TXREADY |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| C | RW RXREADY |  |  | Write '1' to disable interrupt for event RXREADY |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| D | RW ADDRESS |  |  | Write '1' to disable interrupt for event ADDRESS |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| E | RW FRAMESTART |  |  | Write '1' to disable interrupt for event FRAMESTART |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| F | RW PAYLOAD |  |  | Write '1' to disable interrupt for event PAYLOAD |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| G | RW END |  |  | Write '1' to disable interrupt for event END<br>In TX: Last byte to be transmitted has been fetched from RAM<br>In RX: Last byte received on air has been stored to RAM |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| H | RW PHYEND |  |  | Write '1' to disable interrupt for event PHYEND |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
| I | RW DISABLED |  |  | Write '1' to disable interrupt for event DISABLED |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| J | RW DEVMATCH | Disabled<br>Clear | 1<br>1 | Write '1' to disable interrupt for event DEVMATCH<br>Disable<br>Read: Disabled |
|  |  | Enabled | 0 | Read: Enabled |
| K | RW DEVMISS |  |  | Write '1' to disable interrupt for event DEVMISS |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Clear

1

Disable

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 | 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID |  |  |  | W V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| L RW | CRCOK |  |  | Write '1' to disable interrupt for event CRCOK |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| M RW | CRCERROR |  |  | Write '1' to disable interrupt for event CRCERROR |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| N RW | BCMATCH |  |  | Write '1' to disable interrupt for event BCMATCH<br>Bit counter value is specified in the RADIO.BCC register |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| O RW | EDEND |  |  | Write '1' to disable interrupt for event EDEND |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| P RW | EDSTOPPED |  |  | Write '1' to disable interrupt for event EDSTOPPED |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| Q RW | CCAIDLE |  |  | Write '1' to disable interrupt for event CCAIDLE |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| R RW | CCABUSY |  |  | Write '1' to disable interrupt for event CCABUSY |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| S RW | CCASTOPPED |  |  | Write '1' to disable interrupt for event CCASTOPPED |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| T RW | RATEBOOST |  |  | Write '1' to disable interrupt for event RATEBOOST |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| U RW | MHRMATCH |  |  | Write '1' to disable interrupt for event MHRMATCH |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/6cfff3f8c02894b616bcf6a54443be7c6ce65950fa3633a36effdd2b29507732.jpg}})

| Bit number |  | 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------------------ |
| ID |  | W V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Description |
| V RW SYNC |  | Write '1' to disable interrupt for event SYNC MODE=Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered. For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode. It is also possible that the event is not generated, or not generated before the ADDRESS event. |
| W RW |  | Write '1' to |
|  | Disabled | Read: Disabled |
|  | Enabled | Read: Enabled |
|  | CTEPRESENT | disable interrupt for event CTEPRESENT |
|  | Clear | Disable |
|  | Enabled | Read: Enabled |

## 8.17.14.78 MODE

Address offset: 0x500

Data rate and modulation

![]({{img:images/0745de69507b268160de48f385845e591142e5d2ae20b4f45664a16ea7cfe3a3.jpg}})

| Bit number |
| -------------- |

## 8.17.14.79 STATE

Address offset: 0x520

Current radio state

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/a0236b51cdf5ea4261f179532781219158995a8f9983aff1aee828441b72d089.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID A A A A | ID A A A A | ID A A A A | ID A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value | Description |
| A R STATE | A R STATE | A R STATE | Current radio state |
|  | Disabled | 0 | RADIO is in the DISABLED state |
|  | RxRu | 1 | RADIO is in the RXRU state |
|  | RxIdle | 2 | RADIO is in the RXIDLE state |
|  | Rx | 3 | RADIO is in the RX state |
|  | RxDisable | 4 | RADIO is in the RXDISABLE state |
|  | TxRu | 9 | RADIO is in the TXRU state |
|  | TxIdle | 10 | RADIO is in the TXIDLE state |
|  | Tx | 11 | RADIO is in the TX state |
|  | TxDisable | 12 | RADIO is in the TXDISABLE state |

## 8.17.14.80 EDCTRL

Address offset: 0x530

IEEE 802.15.4 energy detect control

![]({{img:images/a7bf973598964e275f22512d9433449574f4b2eed8039f0c904b980de77e6177.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ |
| ID | B B B B B B A A A A A A A A A A A A A A A A A A A A A |
| Reset 0x20000000 | 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value Description |
| A RW EDCNT | IEEE 802.15.4 energy detect loop count Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE. |
| B RW EDPERIOD | IEEE 802.15.4 energy detect period, 4us resolution, no averaging except the IEEE 802.15.4 ED range 128us (32) EDPERIOD value other than Default is not supported. |

## 8.17.14.81 EDSAMPLE

Address offset: 0x534

IEEE 802.15.4 energy detect level

![]({{img:images/64e8c5ff264c2dc10d8dff197c0e3ccc3d47e24b5975f8ded3ae23334095651d.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ |
| ID | A A A A A A A A |
| Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value Description |
| A R EDLVL | [0..127] IEEE 802.15.4 energy detect level |

Register value must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by factor ED\_RSSISCALE, as shown in the code example for ED sampling

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.17.14.82 CCACTRL

Address offset: 0x538

IEEE 802.15.4 clear channel assessment control

![]({{img:images/5ff4356ee6f0c61c5954c39123c3e97acfe7c195da2e64f556db8133d107d706.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | ID | D D | D D | D | D D D | C C C | C C C C C | B B B B | B B | B B |  | A | A A |  |  |  |
| Reset 0x052D0000 | Reset 0x052D0000 | Reset 0x052D0000 | Reset 0x052D0000 | 0 0 | 0 0 | 0 | 1 0 1 | 0 0 1 0 1 1 | 0 1 | 0 0 0 0 0 | 0 | 0 0 0 0 | 0 0 | 0 0 | 0 0 |  |  |  |
| ID | R/W | Field | Value ID | Value |  |  |  | Description |  |  |  |  |  |  |  |  |  |  |
| A | RW | CCAMODE | EdMode | 0 |  |  |  | CCA mode of operation<br>Energy above threshold<br>Will report busy whenever energy detected above CCAEDTHRES | Will report busy whenever energy detected above CCAEDTHRES | Will report busy whenever energy detected above CCAEDTHRES | is<br>Will report busy whenever energy detected above CCAEDTHRES | Will report busy whenever energy detected above CCAEDTHRES | Will report busy whenever energy detected above CCAEDTHRES | Will report busy whenever energy detected above CCAEDTHRES | Will report busy whenever energy detected above CCAEDTHRES |  |  |  |
|  |  |  | CarrierMode<br>CarrierAndEdMode<br>CarrierOrEdMode<br>EdModeTest1 | 1<br>2<br>3<br>4 |  |  |  | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen<br>Energy above threshold AND carrier<br>Energy above threshold OR carrier<br>Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen<br>seen<br>seen | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen | Carrier seen<br>Will report busy whenever compliant IEEE 802.15.4 signal is seen |  |  |  |
| B | RW | CCAEDTHRES |  |  |  |  |  | CCA energy busy threshold. Used in all the CCA modes except CarrierMode.<br>Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register | Must be converted from IEEE 802.15.4 range by dividing by factor<br>ED_RSSISCALE - similar to EDSAMPLE register |  |  |  |
| C | RW | CCACORRTHRES |  |  |  |  |  | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. | CCA correlator busy threshold. Only relevant to CarrierMode,<br>CarrierAndEdMode, and CarrierOrEdMode. |  |  |  |
| D | RW | CCACORRCNT |  |  |  |  |  | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. | Limit for occurances above CCACORRTHRES. When not equal to zero the<br>corrolator based signal detect is enabled. |  |  |  |
## 8.17.14.83 DATAWHITE

Address offset: 0x540

Data whitening configuration

![]({{img:images/9dd64e70c34484f5e0803e600094bb1dca33ca0e0bf791952b4a1dc9bcd587b6.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ |
| ID | B B B B B B B B B B A A A A A A A A A |
| Reset 0x00890040 | 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 |
| ID R/W Field | Value Description |
| A RW IV | Whitening initial value Data whitening initial value. |
| B RW POLY | Whitening polynomial |

## 8.17.14.84 TIMING

Address offset: 0x704

Timing

![]({{img:images/2e561a536875b72a036f4cbeeea476e887a4661d5aff1e996e3e837dd6718464.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID A | ID A | ID A | ID A |
| Reset 0x00000001 | Reset 0x00000001 | Reset 0x00000001 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 |
| ID | Field | Value ID | Value Description |
| A | RU |  | Ramp-up time |
|  |  | Legacy | 0 Legacy ramp-up time |
|  |  | Fast | 1 Fast ramp-up (default) |

## 8.17.14.85 FREQUENCY

Address offset: 0x708

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## Frequency

![]({{img:images/a98f406eda15032e0019cd04d67a048f406487701b665f1bff533685f6713ff5.jpg}})

## 8.17.14.86 TXPOWER

Address offset: 0x710

Output power

![]({{img:images/c6d5a93f5ef5f1d95841c1279026cbbd3709bfd82512c3e9db4a501cd9a0e8fb.jpg}})

![]({{img:images/75e5a4a2d14cdf33d2a0f2d0d4e1e7118c18709910748b3a2809360256ffd88c.jpg}})

## 8.17.14.87 TIFS

## Address offset: 0x714

Interframe spacing in μs

![]({{img:images/2506abc31d8d3dc6975e2f1c0e88a97a1ff9bfa363ed944c86eb21e93cc9e09f.jpg}})

## 8.17.14.88 RSSISAMPLE

Address offset: 0x718

RSSI sample

![]({{img:images/d8db43f8ca01687b8c921dc8e2c971e39b1067a64ba91d4ebc13100291a8e77e.jpg}})

## 8.17.14.89 FREQFINETUNE

Address offset: 0x0804

Fine tuning of the RF frequency

Receiver sensitivity may be degraded when operating on 2414, 2415, 2430, 2431, 2446, 2447, 2462, 2463, 2478 or 2479 MHz with a small but non-zero FSFREQFINETUNE value

This register will not be reset by the SOFTRESET task

![]({{img:images/ab42cee9094154d01fb6953ed9cb0ffe57bffc13ef822e91d1b214364a2ee00c.jpg}})

## 8.17.14.90 FECONFIG

Address offset: 0x908

Config register

This register will not be reset by the SOFTRESET task

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/d226de7c8529364c32d2835ac784a5498aafcfb12256a02f02ba77ff72d66611.jpg}})

## 8.17.14.91 DFEMODE

Address offset: 0xD00

Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)

![]({{img:images/182a86ffd89495cd536edd804b024802dc7d826961d20e571579f159b613899c.jpg}})

## 8.17.14.92 DFESTATUS

Address offset: 0xD04

DFE status information

![]({{img:images/871470cec11da36f6b79f48d8c4257a69effad3ad1f57e6ae514e92b973fcce5.jpg}})

## 8.17.14.93 DFECTRL1

Address offset: 0xD10

Various configuration for Direction finding

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

| Bit | number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 |  |  |  | 9 8 5 4 | 7 3 |  |  | 6 |  |  | 0 | 2 1 |
| ------- | ------------ | ------------------- | ----------- | ------------------------------ | ----------- | ------------------------------ | ---------------------------- | ------------ | ----------------- | ------- | ------------------- | ------------------------------ | ----- | ---- | ----- | ------- |
| ID |  |  |  |  | H H H | F E D | H G G G | D D C C | C B | A | A A |  |  | A |  | A A |
| Reset | 0x00023282 |  |  | 0 0 | 0 0 0 0 0 | 0 0 | 0 0 0 | 0 | 1 1 0 | 0 0 | 0 0 | 1 0 | 1 0 |  |  | 1 0 |
| ID | R/W | Field | Value ID | Value |  |  | 0 Description |  |  |  |  | 0 |  |  |  |  |
| A | RW | NUMBEROF8US |  |  |  | AoA/AoD procedure<br>but in RX | Length of the<br>Always used in TX | in<br>mode, mode | 8 us units<br>CTEINLINECTRLEN | is 0 |  | number of<br>only when |  |  |  |  |
| B | RW | DFEINEXTENSION | CRC<br>Payload | 1<br>0 | Add CTE | and do antenna triggered at end | extension AoA/AoD<br>Antenna switching/sampling | of CRC<br>is done in | in this<br>payload |  | extension | switching/sampling<br>the packet |  |  |  |  |
| C | RW | TSWITCHSPACING | 4us 2us | 1 2 |  | every time the antenna | Interval between 4us<br>2us 1us |  | in the | state | SWITCHING | is changed |  |  |  |  |
| D | RW | TSAMPLESPACINGREF | 1us<br>1us 500ns<br>250ns | 3<br>3 4<br>5 |  | samples in the REFERENCE | Interval between<br>1us 0.5us 0.25us<br>0.125us |  | period |  |  |  |  |  |  |  |
| E | RW | SAMPLETYPE | IQ |  |  | I/Q or magnitude/phase and | Whether Complex samples | Q |  |  |  |  |  |  |  |  |
| F | RW | TSAMPLESPACING | 4us<br>2us<br>1us<br>500ns<br>250ns | 1<br>2 3<br>4<br>5 |  | when CTEINLINERXMODE1US or | Note:<br>4us<br>2us<br>1us<br>0.5us<br>0.25us |  | are |  | Then either used. | CTEINLINECTRLEN is set. CTEINLINERXMODE2US |  |  |  |  |
## 8.17.14.94 DFECTRL2

Address offset: 0xD14

Start offset for Direction finding

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/63ddc78a71b21e632e65c91d6c150b1676dc3c83f3656a91be2fd25162e4014d.jpg}})

## 8.17.14.95 SWITCHPATTERN

## Address offset: 0xD28

GPIO patterns to be used for each antenna

Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be configured in the GPIO peripheral as described in Pin configuration.

If the total number of antenna slots is bigger than the number of patterns, we loop back to the pattern used after the reference pattern.

![]({{img:images/9f5c0003450ae8765d76b9bbadf801ec05209578227d5faa2f2024ca754ee327.jpg}})

## 8.17.14.96 CLEARPATTERN

Address offset: 0xD2C

Clear the GPIO pattern array for antenna control

![]({{img:images/2533b2dba6392f4a672342db36cf31b398d3ab64408bd5c50a72ca7d0e858aef.jpg}})

Behaves as a task register, but does not have PPI nor IRQ

## 8.17.14.97 PSEL.DFEGPIO[n] (n=0..7)

Address offset: 0xD30 + (n × 0x4)

Pin select for DFE pin n

Note:

Must be set before enabling the radio

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/867853058e485dd86fa843b0b8d30ef2bd6aea632fbc1b03da4e0d51ca086750.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..1] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.17.14.98 DFEPACKET

DFE packet EasyDMA channel

## 8.17.14.98.1 DFEPACKET.PTR

Address offset: 0xD50

Data pointer

![]({{img:images/a729e52a42480b51bac7d076a4529c9c55e8e6ac4aec00eb57fe5198c89da90a.jpg}})

See the memory chapter for details about which memories are available for EasyDMA.

## 8.17.14.98.2 DFEPACKET.MAXCNT

Address offset: 0xD54

Maximum number of bytes to transfer

![]({{img:images/3f2cd673aea0b069cc7f42fcf747b042af6aeb5b70b7a71ac8737b8917909359.jpg}})

## 8.17.14.98.3 DFEPACKET.AMOUNT

Address offset: 0xD58

Number of bytes transferred in the last transaction

![]({{img:images/6e105c631f2f95a7a26554ec3e2833c9840b1cce410e8b3dde93af948e83944f.jpg}})

## 8.17.14.98.4 DFEPACKET.CURRENTAMOUNT

Address offset: 0xD5C

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## Number of bytes transferred in the current transaction

![]({{img:images/6e5a73cb56972671df363ff8c64ae03d6a2609770cc317056b171ed9995679ea.jpg}})

## 8.17.14.99 CRCSTATUS

Address offset: 0xE0C

CRC status

![]({{img:images/dbe0b25f2d0b61f912b3da0b7237b1ea1e2030b0dc03eba714ed87241799958c.jpg}})

## 8.17.14.100 RXMATCH

Address offset: 0xE10

Received address

![]({{img:images/4f09339cbe5300db9581526087c13583c06adc6707a0caddea4948dd714a4616.jpg}})

Logical address of which previous packet was received

## 8.17.14.101 RXCRC

Address offset: 0xE14

CRC field of previously received packet

![]({{img:images/0b9337030f83e0043d9a5a3a07af0dd8b37f6d0235239ec72f83c440037cc746.jpg}})

CRC field of previously received packet

## 8.17.14.102 DAI

Address offset: 0xE18

Device address match index

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/0945cb86dee93c8a1ac85d2164d5e99a3c6f9f7da7ee4fa0f229b596f1c6b1c2.jpg}})

## 8.17.14.103 PDUSTAT

Address offset: 0xE1C

Payload status

![]({{img:images/444b22c1df0d45154b10158c06b45fd87bf4d796583fe7a8183bf55fd9fef778.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | -------------------- | ------------------ | ------------------------------ |
| ID B B A | ID B B A | ID B B A | ID B B A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field Value ID | Value | Description |
| A | R PDUSTAT |  | Status on payload length vs. PCNF1.MAXLEN |
|  |  | LessThan 0 | Payload less than PCNF1.MAXLEN |
|  |  | GreaterThan 1 | Payload greater than PCNF1.MAXLEN |
| B | R CISTAT |  | Status on what rate packet is received with in Long Range |
|  |  | LR125kbit 0 | Frame is received at 125 kbps |
|  |  | LR500kbit 1 | Frame is received at 500 kbps |

## 8.17.14.104 PCNF0

Address offset: 0xE20

Packet configuration register 0

| Bit number | Bit number | Bit number | Bit number | Bit number |
| -------------- | -------------- | -------------- | -------------- | -------------- |

## 8.17.14.105 PCNF1

Address offset: 0xE28

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## Packet configuration register 1

| Bit number |  |  |  | 31 30 29 28 27 | 26 | 25 24 | 22 21 20 19 18 | 17 16 15 14 | 13 12 11 10 9 | 2 1 0 | 2 1 0 |
| -------------- | ------- | ------------- | ----------- | ------------------ | ------ | --------- | ------------------------------ | ------------------------------ | ------------------------------ | --------- | --------- |
| ID |  |  |  |  |  | F E |  | C C C B | B B B B B B | A A | A A |
| Reset | Reset | 0x00000000 |  | 0 0 0 | 0 0 | 0 0 | 0 0 | 0 0 0 0 | 0 0 0 0 0 0 0 | 0 0 0 | 0 0 0 |
| ID | R/W | Field | Value ID | Value |  |  | Description |  |  |  |  |
| A | RW | MAXLEN |  | [0..255] |  |  | Maximum MAXLEN, the | length of packet radio will | payload. If the packet truncate the payload |  |  |
| B | RW | STATLEN |  | [0..255] |  |  | Static length The static sending and will receive | in number of length parameter receiving send N bytes | bytes is added to the packets, e.g. if the more than what |  |  |
| C | RW | BALEN |  | [2..4] |  |  | Base address The address address prefix, | length in number field is composed e.g. set | of bytes of the base BALEN=2 to get a |  |  |
| D | RW | ENDIAN |  |  |  |  | On-air endianness PAYLOAD fields. | of packet, | this applies to the S0, |  |  |
| E | RW | WHITEEN | Disabled | 1 |  |  | Most significant Enable or Including<br>the packets. Disable Enable | bit on disable packet address field<br>to S0 | whitening<br>CRC check is not supported |  |  |
| F | RW | WHITEOFFSET | Include 0 |  |  |  | whitening<br>included | is enabled can<br>in whitening | be configured to be |  |  |
## 8.17.14.106 BASE0

Address offset: 0xE2C

Base address 0

![]({{img:images/2c14fa509b484cdae6ff2235a4450ec448898054e88f98e313e8f6b51df425db.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ |
| ID | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A |
| Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value Description |

## 8.17.14.107 BASE1

Address offset: 0xE30

Base address 1

![]({{img:images/890af77ea64a2b40e6734a24a73232577dc7b3e430bbbeb7b0e3f306aff7b3e0.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ |
| ID | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A |
| Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value Description |
| A RW BASE1 | Base address 1 |

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.17.14.108 PREFIX0

Address offset: 0xE34

Prefixes bytes for logical addresses 0-3

![]({{img:images/161819d6570d33a1deadbdf552a7b10c96954f47d0096cc9cf145fdab36b670c.jpg}})

## 8.17.14.109 PREFIX1

Address offset: 0xE38

Prefixes bytes for logical addresses 4-7

![]({{img:images/8f5754c255621e2ad7da5ac3c5d2d7a39340d2214d49a2881e6d0eb823165f3a.jpg}})

## 8.17.14.110 TXADDRESS

Address offset: 0xE3C

Transmit address select

![]({{img:images/af6b644baf0f94e383af0c6df49da11349c0353f8d9c8d4122a1e72725b1b32a.jpg}})

Logical address to be used when transmitting a packet

## 8.17.14.111 RXADDRESSES

Address offset: 0xE40

Receive address select

![]({{img:images/e1f140a0571d20bf60010bf7a21c258704c322a4431dadfabf5118f5885c4d6a.jpg}})

## 8.17.14.112 CRCCNF

Address offset: 0xE44 CRC configuration

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/00faa8c5defcaec76f584ec2dafd31970076e1c7e5964e6e162333c873d6f76b.jpg}})

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------------------ |
| ID |  | B B B A A |
| Reset 0x00000000 | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID Value | Description |
| A RW LEN |  | CRC length in number of bytes. |
|  | Disabled 0 One 1 | CRC length is zero and CRC calculation is disabled CRC length is one byte and CRC calculation is enabled |
|  | Two 2 | CRC length is two bytes and CRC calculation is enabled |
|  | Three 3 | CRC length is three bytes and CRC calculation is enabled |
| B RW SKIPADDR | Include 0 | Control whether CRC calculation skips the address field. Other fields can also be skipped. CRC calculation includes address field |
|  | Skip 1 | CRC calculation starting at first byte after address field. |
|  | Ieee802154 2 | CRC calculation starting at first byte after length field (as per 802.15.4 standard). |
| SkipS0 | 3 | CRC calculation starting at first byte after S0 field. |
|  | 4 | CRC calculation starting at first byte after S1 field. |
| SkipS1 |  |  |
## 8.17.14.113 CRCPOLY

## Address offset: 0xE48

CRC polynomial

![]({{img:images/fed80b82fa6438b72b23a80b67ee61e3510c295e20193977af73195085e83c39.jpg}})

Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/ bit is hardwired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .

## 8.17.14.114 CRCINIT

## Address offset: 0xE4C

CRC initial value

![]({{img:images/3844001d1990659cd533ad85722d77eae69b3d8890c83d985173f333d1e5b129.jpg}})

Initial value for CRC calculation

## 8.17.14.115 DAB[n] (n=0..7)

Address offset: 0xE50 + (n × 0x4)

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## Device address base segment n

![]({{img:images/c6683c52174a8e0c727160432930b095f70e99a4d03615215852343216592d76.jpg}})

## 8.17.14.116 DAP[n] (n=0..7)

Address offset: 0xE70 + (n × 0x4)

Device address prefix n

![]({{img:images/38471cf993feb1179ea4cdef4d821bb1ca33b7b1ed4b764001c241103a978bbf.jpg}})

## 8.17.14.117 DACNF

Address offset: 0xE90

Device address match configuration

![]({{img:images/320cb4aaa1b0e11c26e107cae3cd05f2a2139d776f9d27f749ad0e657f98268b.jpg}})

## 8.17.14.118 BCC

Address offset: 0xE94

Bit counter compare

![]({{img:images/129d0dbf6e97e220ca0ef318b23a7fce8001db1534b297d64d6ae153ca0b2940.jpg}})

Bit counter compare register

## 8.17.14.119 CTESTATUS

Address offset: 0xEA4

CTEInfo parsed from received packet

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/c2ebc8f52785ba53e35c44c5aa65a36b0f5f3eb2e4a7a3f0b9a158ceb33574a2.jpg}})

## 8.17.14.120 MHRMATCHCONF

Address offset: 0xEB4

Search pattern configuration

![]({{img:images/6290575a860d86d4a634c311a8aabb78eae9af64875480930ac20f29060f8b46.jpg}})

## 8.17.14.121 MHRMATCHMASK

Address offset: 0xEB8

Pattern mask

![]({{img:images/cc543387017135c9e7d6c600a00ab784b14cbe6162500ac5e8c8ee1e060ed9fd.jpg}})

A

RW

MHRMATCHMASK

## 8.17.14.122 SFD

Address offset: 0xEBC

IEEE 802.15.4 start of frame delimiter

![]({{img:images/749b96024159e5fc8d875d451c1858563b13a42309e6a62f0354f7b061e78513.jpg}})

## 8.17.14.123 CTEINLINECONF

Address offset: 0xEC0

Configuration for CTE inline mode

Pattern mask

IEEE 802.15.4 start of frame delimiter. Note: the least significant 4 bits of the SFD cannot all be zeros.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

| Bit | number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 |  | 2 1 0 |
| ---------- | ---------------- | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID |  |  |  | H H H H H H H G G G | H G G G G G F F | A |
| Reset ID | 0x00002800 R/W | Field | Value ID | 0 0 0 0 0 0 0 0 Value | 0 0 0 0 0 0 0 0 0 0 Description | 0 0 0 |
| A | RW | CTEINLINECTRLEN |  |  | Enable parsing of CTEInfo from | received packet in BLE modes |
| B | RW | CTEINFOINS1 | Enabled Disabled InS1 | 1 0 | Parsing of CTEInfo is enabled Parsing of CTEInfo is disabled | PDU) |
|  |  |  | NotInS1 | not 1 (data CTEInfo is NOT in S1 byte | CTEInfo is S1 byte or CTEInfo is in S1 byte | (advertising PDU) |
| C | RW | CTEERRORHANDLING CTETIMEVALIDRANGE | Yes No | 0 | Max range of CTETime Note: Valid range is 2-20 in BLE core spec. If larger be an indication of an error in the received 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 31 in 8us unit in | Sampling/switching if CRC is not OK Sampling and antenna switching also when CRC is not OK sampling and antenna switching when CRC is not OK |
| D | RW |  |  | 1 0 | No |  |
| E | RW |  | 20 31 63 CTEINLINERXMODE1US 4us<br>2us 1us 500ns | 0 1 2 the device is in 1 us". When in AoA 1<br>2 3 4 0.5us 5 0.25us 0.125us | 63 When AoD "AoD 4us 2us 1us<br>mode, this is mode, this is | 8us unit<br>packet. Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set |
| F | RW |  | 250ns 125ns<br>250ns | "AoD 2 us". 1 2<br>3 4 5 | for the mode, this mode, this is | samples samples in the SWITCHING period when is set is in AoD is used when the received CTEType When in AoA used when TSWITCHSPACING is 4 |
| G |  | S0CONF |  | 4us 2us | to match significant bit always<br>to set which bit to match | bit pattern<br>corresponds to the first bit of S0 received |
| H | RW<br>RW | S0MASK<br>CTEINLINERXMODE2US | 4us 2us 1us 500ns<br>125ns | 6<br>6 | The least S0 bit mask<br>The<br>1us 0.5us 0.25us 0.125us<br>Spacing between CTEINLINEMODE<br>When the device<br>S0 | least<br>significant bit always corresponds to the first bit of S0 received<br>is us. |
## 8.17.14.124 PACKETPTR

Address offset: 0xED0

Packet pointer

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/df56db7014c95eb11b460bc0f5074a71276df14a926967be156c10ea2ab45540.jpg}})

## 8.17.14.125 CSTONES.MODE

Address offset: 0x1000

Selects the mode(s) that are activated on the start signal

![]({{img:images/d8241ce5a3de271913a6e7a0b82f851dd5720d65adc673feead23ab529001aa5.jpg}})

## 8.17.14.126 CSTONES.NUMSAMPLES

Address offset: 0x1004

Number of input samples at 2MHz sample rate

![]({{img:images/e0ae263cd31faa5783570f3cc25c8867bc2dbb0240a9deb2b0d69af783d5f25d.jpg}})

## 8.17.14.127 CSTONES.NEXTFREQUENCY

Address offset: 0x1008

The value of FREQUENCY that will be used in the next step

![]({{img:images/d130b52338239a3bd7a6b8474008d51f2876c6a298158ed05f22b7fe60fb1e74.jpg}})

A

RW

NEXTFREQUENCY

## 8.17.14.128 CSTONES.FFOIN

Address offset: 0x100C

Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived from CnAcc (autocorrelation of the scaled input signal) value

Frequency = 2400 + FREQUENCY (MHz)

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/2d2c4248a13fe992573a1eb722c76a5c6ca852684d2222b46e2202708f31968b.jpg}})

## 8.17.14.129 CSTONES.FFOSOURCE

Address offset: 0x1010

Source of FFO

![]({{img:images/2b64b2e0e42a551707046a315e162e1db0fd0dc91956b5086d93c32dfbe07d41.jpg}})

## 8.17.14.130 CSTONES.FAEPEER

Address offset: 0x1014

FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps.

![]({{img:images/3796c34f29e40611fad3e0e5968bcfe6d0b5bda50a197058a6917a5502bc4e5d.jpg}})

## 8.17.14.131 CSTONES.PHASESHIFT

Address offset: 0x1018

Parameter used in TPM, provided by software

![]({{img:images/37818b1114be5cae10624aee0bb84180a6b2b73aff5ff64f7c245cb84256deab.jpg}})

## 8.17.14.132 CSTONES.NUMSAMPLESCOEFF

## Address offset: 0x101C

Parameter used in TPM, provided by software

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/49d787268bbb0599ca92544d20d53364944744f1ef61ec67ae56c1b60e8b8ae1.jpg}})

## 8.17.14.133 CSTONES.PCT16

Address offset: 0x1020

Mean magnitude and mean phase converted to IQ

![]({{img:images/12c9b7ff7428295ee2da75bfbaf3767579f562a12129b2bcf091dd2de7b98cdf.jpg}})

## 8.17.14.134 CSTONES.MAGPHASEMEAN

Address offset: 0x1024

Mean magnitude and phase of the signal before it is converted to PCT16

![]({{img:images/bf0e797b95a61c301cbc73d137299b964786fe0d648b10ef3a99b2afcb8aa591.jpg}})

## 8.17.14.135 CSTONES.IQRAWMEAN

Address offset: 0x1028

Mean of IQ values

![]({{img:images/c477c59964525f940dc251b5a4dd845b431ca35e95cda37f5c2dd299acd31126.jpg}})

## 8.17.14.136 CSTONES.MAGSTD

Address offset: 0x102C

Magnitude standard deviation approximation

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/f59dde088db61ad725f6118f8e951f06b7b607b03e7f718de9fec996223ff06f.jpg}})

A

R

MAGSTD

## 8.17.14.137 CSTONES.CNACC

Address offset: 0x1030

Output of the autocorrelation of the accumulated IQ signal

![]({{img:images/12efcaa7fb6d7c7464c774ac89372646ca45b0e327f95d848007ebfb784c6ffc.jpg}})

## 8.17.14.138 CSTONES.FFOEST

Address offset: 0x1034

FFO estimate

![]({{img:images/8e84edbc20837274d4b4cb4895daba1705d263e3c0735d71a5dbbba4e9afba8f.jpg}})

A

R

FFOEST

## 8.17.14.139 CSTONES.DOWNSAMPLE

Address offset: 0x1038

Turn on/off down sample of input IQ-signals

![]({{img:images/188cf30e867fbab284a3f6dbb66f036ef4be4281dbd46fdbb7c316706eba1bac.jpg}})

## 8.17.14.140 CSTONES.FINETUNENEXT

Address offset: 0x103C

Number of full ADPLL finetune steps

Magnitude standard deviation approximation

Units 62.5 ppb. Max range +/-100 ppm plus margin.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/301fc25c83ac9d6f342f292fc8f158126124e84cc0d62215b0660d9bd5455370.jpg}})

## 8.17.14.141 CSTONES.CFOPHASE

Address offset: 0x1040

Cordic output of CnAcc

![]({{img:images/afa36d24c903389d9afd2813a346ae1f7137b46533b401cf998d67f31bfc0193.jpg}})

## 8.17.14.142 CSTONES.FREQOFFSET

## Address offset: 0x1044

Frequency offset estimate

![]({{img:images/a768daffa3d96eccce515a877f7aab8eca1674ff8d6ead22171584f8a9dd5d75.jpg}})

## 8.17.14.143 CSTONES.PCT11

## Address offset: 0x1048

Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023].

![]({{img:images/4e2f7a438d361b3a18a177f5200d4a79860f24a39ca773e023dd6de5b0abcf6b.jpg}})

## 8.17.14.144 CSTONES.LFAENEXT

## Address offset: 0x104C

Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values limited to [-64,63] with units 7.6294 Hz.

![]({{img:images/a37e95ceeee89bd8ab00135425bcfa878d145a66d34f4cdc246b7c80e85f3f13.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.17.14.145 RTT.CONFIG

Address offset: 0x1050

RTT Config.

![]({{img:images/ec30f867833ae0467e224e9fd473e23ca156d3de01bb79c5159ed7327342efc7.jpg}})

| Bit number |
| -------------- |

## 8.17.14.146 RTT.SEGMENT01

Address offset: 0x1054

RTT segments 0 and 1

![]({{img:images/8e299dec98de85d8eb68fe017e7204848172b0064aecc3c2f5bfae4436b70579.jpg}})

## 8.17.14.147 RTT.SEGMENT23

Address offset: 0x1058

RTT segments 2 and 3

![]({{img:images/6cfe493a4efec988b6c9ee2e3a58546440881ba696c13400ea90249430276dc6.jpg}})

## 8.17.14.148 RTT.SEGMENT45

Address offset: 0x105C

RTT segments 4 and 5

Data Bits 63 - 32

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/e8a1b8fb3232a3ed2039feff39046fc8d0a680ecc36f0d466f801748e734d614.jpg}})

## 8.17.14.149 RTT.SEGMENT67

Address offset: 0x1060

RTT segments 6 and 7

![]({{img:images/052e0e95f4291dce557bd46f2d77814f8c67b17af9307b801c5c89a6f52f4eb5.jpg}})

## 8.18 SAADC - Successive approximation analog-todigital converter

The SAADC peripheral is a differential successive approximation register (SAR) analog-to-digital converter.

The main features of SAADC are the following:

- Four accuracy modes
- 10-bit mode with a maximum sample rate of 2 Msps
- 12-bit mode with a sample rate of 250 ksps
- 14-bit mode with a sample rate of 31.25 ksps
- Oversampling mode with configurable sample rate
- 10-bit resolution in single-ended mode, 11-bit resolution in differential mode, and 12/14-bit resolution with oversampling
- Multiple analog inputs
- GPIO pins with analog function (input range 0 to VDD)
- VDD (divided down to a valid range)
- Up to eight input channels
- One input per single-ended channel, and two inputs per differential channel
- Scan mode can be configured with both single-ended inputs and differential inputs
- Each channel can be configured to select any of the above analog inputs
- Sampling triggered by a task from software or a DPPI channel for full flexibility on sample frequency source from low-power 32.768 kHz RTC or more accurate 1/16 MHz timers
- One-shot conversion mode to sample a single channel
- Scan mode to sample a series of channels in sequence with configurable sample delay
- Support for direct sample transfer to RAM using EasyDMA
- Interrupts on single sample and full buffer events
- Samples stored as 16-bit two's complement values for differential and single-ended sampling
- Continuous sampling without the need of an external timer
- On-the-fly limit checking

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.18.1 Shared resources

The ADC can coexist with COMP and other peripherals using one of AIN0-AIN7 , provided these are assigned to different pins.

It is not recommended to select the same analog input pin for both modules.

## 8.18.2 Overview

The ADC supports up to eight external analog inputs. It can be operated in One-shot mode with sampling under software control, or Continuous mode with a programmable sampling rate.

The analog inputs can be configured as eight single-ended inputs, four differential inputs or a combination of these. Each channel can be configured to select:

- GPIO pins with analog input function, see Pin assignments on page 837, also marked with name AIN . Input range is 0 to VDD.
- VDD (divided down to a valid range)
- DVDD
- AVDD

Channels can be sampled individually in one-shot or continuous sampling modes, or, using scan mode, multiple channels can be sampled in sequence. To improve noise performance, channels can be oversampled.

Oversampling can be done with either noise shaping or by accumulation and averaging.

Figure 131: Simplified ADC block diagram

![]({{img:images/80698d55e510ebf2f92892e8993b7a50dad31050850478a39a99e1ab12b30e5a.jpg}})

Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with single-ended input in the MODE field of the CH[n].CONFIG register. In single-ended mode, the negative input will be shorted to ground internally.

The assumption in single-ended mode is that the internal ground of the ADC is the same as the external ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB in single-ended mode. If this is a concern we recommend using differential measurement.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## 8.18.3 Digital output

The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as follows:

RESULT = [V(P) - V(N) ] * GAIN/REFERENCE * 2 (RESOLUTION - m)


where

V(P)

is the voltage at input P

V(N)

is the voltage at input N

GAIN

is the selected gain setting

m

is the mode setting. Use m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff

## REFERENCE

is the selected reference voltage

The result generated by the ADC will deviate from the expected due to DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors due to high source impedance and sampling jitter. For battery measurement, the DC errors are most noticeable.

The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.9 V differentially, and the input must be scaled accordingly with proper gain setting.

The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, we recommend running CALIBRATEOFFSET at regular intervals. The CALIBRATEDONE event will be generated when the calibration has been completed. Note that the DONE and RESULTDONE events will also be generated.

## 8.18.4 Analog inputs and channels

Up to eight analog input channels, CH[n](n=0..7), can be configured.

See Shared resources on page 537 for shared input with comparators.

Any one of the available channels can be enabled for the ADC to operate in one-shot mode. If more than one CH[n] is configured, the ADC enters scan mode.

An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also enables the particular channel.

An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register will have no effect unless differential mode is enabled and CH[n].PSELP is set, see MODE field in CH[n].CONFIG register.

Important: It is not recommended to use the same analog input pin for multiple analog peripheral functions. See also Shared resources on page 537.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.18.5 Operation modes

The ADC input configuration supports several modes of sampling.

- One-shot, one channel
- One-shot, scan (one sample for each channel)
- Continuous, one channel
- Continuous, scan

Note: Scan mode and oversampling should not be combined without burst.

1. The ADC must be enabled and started via the ENABLE register and START task.
2. At least one channel must be enabled (via the CH[n].CONFIG registers).
3. Now the ADC can be sampled, by triggering the SAMPLE task.

The ADC indicates a single ongoing conversion via the register STATUS. During scan mode, oversampling, noise shaping, or continuous modes, more than a single conversion takes place in the ADC. As consequence, the value reflected in STATUS register will toggle at the end of each single conversion.

## 8.18.5.1 One-shot mode

One-shot operation is configured by enabling only one of the available channels defined by CH[n].PSELP, CH[n].PSELN, and CH[n].CONFIG registers.

Upon a SAMPLE task, the ADC powers up and starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the acquisition time.

The time it takes to perform the first sample is tPWRUP + tACQ + tCONV, where tACQ is the acquisition time, t CONV  is the conversion time, and t PWRUP  is the time it takes to power up the ADC.

If multiple samples are taken, some combinations of tACQ and tCONV will allow SAADC to pipeline sampling and conversion, at which point the actual sampling time is just tCONV.

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. For more information, see EasyDMA on page 541.

## 8.18.5.2 Continuous mode

Continuous sampling can be achieved by using the internal timer in the ADC, or triggering the SAMPLE task from one of the general purpose timers through the PPI system.

Care shall be taken to ensure that the sample rate fulfils the following criteria, depending on how many channels are active:

tSAMPLE > tACQ + tCONV


If tACQ=0 and tCONV=0, SAADC will use pipelining to increase sampling speed. In this case, the time for the first sample to arrive is

tSAMPLE = tPWRUP + tACQ + tCONV


and for subsequent samples

fSAMPLE = 1/(tCONV)


The SAMPLERATE register can be used as a local timer instead of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to start the SAADC and triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the sample rate.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA.

## 8.18.5.3 Improving sampling accuracy

SAADC offers multiple techniques to improve accuracy. Noise shaping modes provide the highest performance by enabling a delta-sigma configuration with analog filtering, oversampling, and digital filtering. Pure oversampling is also supported.

## Oversampling

Oversampling can improve the signal-to-noise ratio (SNR) by approximately 10log(OSR), where OSR is the oversampling ratio. Each oversampled result is obtained by acquiring 2 OVERSAMPLE samples and combining them in an accumulate-and-average filter.

Oversampling and scanning can only be combined with BURST mode enabled. Without BURST mode, oversampling and scanning will average across multiple input channels.

The OVERSAMPLE register controls the accumulator. 2 OVERSAMPLE samples must be taken before the result is written to RAM. This can be achieved by either of the following:

- Use the built-in SAADC local timer and the SAMPLERATE register to perform sampling.
- Use the TIMER peripheral and DPPI to trigger the SAADC SAMPLE task, to sample 2 OVERSAMPLE times at a fixed rate.
- Trigger the SAMPLE task 2 OVERSAMPLE times from software.
- Enable BURST mode and trigger the SAMPLE task once.

BURST mode can be enabled to avoid manually triggering the SAMPLE task 2 OVERSAMPLE times. When BURST is enabled, the ADC automatically samples the input 2 OVERSAMPLE times consecutively, with an approximate timing of (tACQ + tCONV) × 2 OVERSAMPLE . Apart from extending the conversion time, it otherwise behaves like one-shot mode.

A DONE event indicates that a single sample has been acquired, while a RESULTDONE event indicates that enough samples have been gathered to transfer an oversampled result to RAM.

## Noise shaping

Noise shaping is implemented using the successive approximation ADC within a first-order delta-sigma loop. The output is decimated and subsequently filtered with FIR filters. In the noisehaping modes, the sampling rate is 1 MS/s, and high-resolution settings (RESOLUTION ≥ 12) are recommended. Enable noise shaping by configuring the NOISESHAPE register. Depending on the selected mode, the input signal must be bandwidth limited. See Electrical specification parameters fBW,NS for details.

The noise shaping are configured using the NOISESHAPE register.

- 0: Disabled: Disable noise shaping.
- NS1: Noise shaping and decimation by 8, giving a samplerate of 125 kS/s.
- NS2: Noise shaping and decimation by 32, giving a samplerate of 31.25 kS/s. Recommended resolution setting is 14 bits.

## 8.18.5.4 Scan mode

A channel is considered enabled if CH[n].PSELP is set. If more than one channel, CH[n], is enabled, the ADC enters scan mode.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

In scan mode, one SAMPLE task will trigger one conversion per enabled channel. The time it takes to sample all channels is:

Total time < Sum(CH[x].tACQ+tCONV), x=0..enabled channels


A DONE event signals that one channel has been sampled.

In this mode, the RESULTDONE event comes after each sample, that is, once for each channel.

## 8.18.6 EasyDMA

After configuring RESULT.PTR and RESULT.MAXCNT, the ADC resources are started by triggering the START task. The ADC is using EasyDMA to store results in a Result buffer in RAM.

The Result buffer is located at the address specified in the RESULT.PTR register. The RESULT.PTR register is double-buffered and it can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the Result buffer (in bytes) is specified in the RESULT.MAXCNT register and the ADC will generate an END event when it has filled up the Result buffer, see ADC on page 541. Results are stored in little-endian byte order in Data RAM. Every sample will be sign extended to 16 bit before stored in the Result buffer.

The ADC is stopped by triggering the STOP task. The STOP task will terminate an ongoing sampling. The ADC will generate a STOPPED event when it has stopped. If the ADC is already stopped when the STOP task is triggered, the STOPPED event will still be generated.

Figure 132: ADC

![]({{img:images/9c3c9fcb3ba8914c59c312ad03ec798bfeaaedf34adbb2c835fbaaf9d736bd0e.jpg}})

If the RESULT.PTR is not pointing to a RAM region accessible from the peripheral, an EasyDMA transfer may result in a HardFault and/or memory corruption. See Memory on page 14 for more information about the different memory regions.

The EasyDMA will have finished accessing the RAM when the END or STOPPED event has been generated.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

The RESULT.AMOUNT register can be read following an END event or a STOPPED event to see how many bytes have been transferred to the Result buffer in RAM since the START task was triggered.

In scan mode, SAMPLE tasks can be triggered once the START task is triggered. The END event is generated when the number of samples transferred to memory reaches the value specified by RESULT.MAXCNT. After an END event, the START task needs to be triggered again before new samples can be taken.For more information about the scan mode, see Scan mode on page 540.

Note: Ensure the Result buffer can hold at least one result for each enabled channel by setting RESULT.MAXCNT ≥ 2 × (number of enabled channels). Each sample requires two bytes. Insufficient space leads to undefined behavior.

## 8.18.7 Reference

The ADC can use different reference voltages VREF, controlled in the REFSEL field of the CH[n].CONFIG register.

These are:

- Internal reference, VREF = 0.9 V
- External reference, VREF provided by the EXTREF pin

Note: The external reference voltage should be close the internal reference voltage. Preferably no more than 5% deviation from the internal reference voltage, VREF. Using a reference voltage >1.2V will lead to increased leakage, and can lead to undefined behaviour.

The SAADC is preceded by a gain stage which has a programmable gain. The voltage range seen at the input of the gain stage is:

VRangeDifferential = ± VREF/GAIN

VRangeSingleEnded = ± 0.5*VREF/GAIN


The AIN0-AIN7 inputs cannot exceed VDD, or be lower than VSS. The input ranges are also limited by the REFERENCE and GAIN used. The condition

[V(P) - V(N) ] * GAIN/REFERENCE <= 1


must always hold true for valid measurements, otherwise the ADC will saturate and report the max value determined by the RESOLUTION.

## 8.18.8 Acquisition time

To sample the input voltage, the ADC connects a capacitor to the input.

For illustration, see the following figure. The acquisition time indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required acquisition time depends on the source (Rsource ) resistance. For high source resistance the acquisition time should be increased, see Acquisition time on page 543.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 133: Simplified ADC sample network

![]({{img:images/464f734a27b3fa267215702db38776cf77c189450954dfbba2eaca2d09d867a4.jpg}})

Table 56: Acquisition time

| TACQ [μs] | Maximum source resistance [kOhm] |
| ------------- | ------------------------------ |
| ≤1 | <1 |
| 3 | 10 |
| 5 | 40 |
| 10 | 100 |
| 15 | 200 |
| 20 | 400 |
| 40 | 800 |

## 8.18.9 Limits event monitoring

A channel can be event monitored by configuring limit register CH[n].LIMIT.

If the conversion result is higher than the defined high limit, or lower than the defined low limit, the appropriate event will be generated.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Figure 134: Example of limits monitoring on channel 'n'

![]({{img:images/dfe46dd7e91926408196ebe7c5a573172c709eb75108d03f4d38ed4f1fa9ed89.jpg}})

Note that when setting the limits, CH[n].LIMIT.HIGH shall always be higher than or equal to CH[n].LIMIT.LOW. In other words, an event can be generated only when the input signal has been sampled outside of the defined limits. It is not possible to fire an event when the input signal is inside a defined range by swapping high and low limits.

The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a channel, the software shall simply ignore the related events. In that situation, the value of the limits registers is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not.

## 8.18.10 Performance factors

Clock jitter, affecting sample timing accuracy, and circuit noise can affect ADC performance.

Jitter can be between START tasks or from START task to acquisition. START timer accuracy and startup times of regulators and references will contribute to variability. Sources of circuit noise may include CPU activity and the DC/DC regulator. Best ADC performance is achieved using START timing based on the TIMER module, HFXO clock source, and Constant Latency mode.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.18.11 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| ------------ | ---------- | ---------------- | ------------- | ------------- | ------------- | --------- | ------------------------------ |
|  |  |  | Map | Att | DMA | access |  |
| SAADC : S | GLOBAL | 0x500D5000 | US | S | SA | No | Successive approximation analog- to-digital converter SAADC |
| SAADC : NS |  | 0x400D5000 |  |  |  |  |  |
| Instance | Domain | Configuration |  |  |  |  |  |
| ------------ | ---------- | -------------------------------------- |  |  |  |  |  |
| SAADC : S | GLOBAL | CURRENTAMOUNT register not included. |  |  |  |  |  |


| Register | Offset | TZ | Description |
| --------------------------- | ---------- | ------ | ------------------------------ |
| TASKS_START | 0x000 |  | Start the ADC and prepare the result buffer in RAM |
| TASKS_SAMPLE | 0x004 |  | Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. |
| TASKS_STOP | 0x008 |  | Stop the ADC and terminate any on-going conversion |
| TASKS_CALIBRATEOFFSET | 0x00C |  | Starts offset auto-calibration |
| SUBSCRIBE_START | 0x080 |  | Subscribe configuration for task START |
| SUBSCRIBE_SAMPLE | 0x084 |  | Subscribe configuration for task SAMPLE |
| SUBSCRIBE_STOP | 0x088 |  | Subscribe configuration for task STOP |
| SUBSCRIBE_CALIBRATEOFFSET | 0x08C |  | Subscribe configuration for task CALIBRATEOFFSET |
| EVENTS_STARTED | 0x100 |  | The ADC DMA has started |
| EVENTS_END | 0x104 |  | The ADC has filled up the Result buffer |
| EVENTS_DONE | 0x108 |  | A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. |
| EVENTS_RESULTDONE | 0x10C |  | A result is ready to get transferred to RAM. |
| EVENTS_CALIBRATEDONE | 0x110 |  | Calibration is complete |
| EVENTS_STOPPED | 0x114 |  | The ADC DMA has stopped |
| EVENTS_CH[n].LIMITH | 0x118 |  | Last results is above CH[n].LIMIT.HIGH |
| EVENTS_CH[n].LIMITL | 0x11C |  | Last results is below CH[n].LIMIT.LOW |
| PUBLISH_STARTED | 0x180 |  | Publish configuration for event STARTED |
| PUBLISH_END | 0x184 |  | Publish configuration for event END |
| PUBLISH_DONE | 0x188 |  | Publish configuration for event DONE |
| PUBLISH_RESULTDONE | 0x18C |  | Publish configuration for event RESULTDONE |
| PUBLISH_CALIBRATEDONE | 0x190 |  | Publish configuration for event CALIBRATEDONE |
| PUBLISH_STOPPED | 0x194 |  | Publish configuration for event STOPPED |
| PUBLISH_CH[n].LIMITH | 0x198 |  | Publish configuration for event CH[n].LIMITH |
| PUBLISH_CH[n].LIMITL | 0x19C |  | Publish configuration for event CH[n].LIMITL |
| SHORTS | 0x200 |  | Shortcuts between local events and tasks |
| INTEN | 0x300 |  | Enable or disable interrupt |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| STATUS | 0x400 |  | Status |
| TRIM.LINCALCOEFF[n] | 0x440 |  | Linearity calibration coefficient |
| ENABLE | 0x500 |  | Enable or disable ADC |
| Register | Offset | TZ | Description |
| CH[n].PSELP | 0x510 |  | Input positive pin selection for CH[n] |
| CH[n].PSELN | 0x514 |  | Input negative pin selection for CH[n] |
| CH[n].CONFIG | 0x518 |  | Input configuration for CH[n] |
| CH[n].LIMIT | 0x51C |  | High/low limits for event monitoring a channel |
| RESOLUTION | 0x5F0 |  | Resolution configuration |
| OVERSAMPLE | 0x5F4 |  | Oversampling configuration. OVERSAMPLE should not be combined with SCAN unless burst is enabled. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. |
| SAMPLERATE | 0x5F8 |  | Configures the sampling rate for either task-triggered or continuous operation using a local timer |
| RESULT.PTR | 0x62C |  | Data pointer |
| RESULT.MAXCNT | 0x630 |  | Maximum number of buffer bytes to transfer. Note that one sample is two bytes. |
| RESULT.AMOUNT | 0x634 |  | Number of buffer bytes transferred since last START, updated after the END or STOPPED events |
| RESULT.CURRENTAMOUNT | 0x638 |  | Number of buffer bytes transferred since last START, continuously updated |
| NOISESHAPE | 0x654 |  | SAADC provides two operational noise shaping modes (one that prioritizes higher bandwith, while the other prioritizes higher accuracy) that allow trade-offs between ADC resolution, power consumption, and signal bandwidth. |

## 8.18.11.1 TASKS\_START

Address offset: 0x000

Start the ADC and prepare the result buffer in RAM

![]({{img:images/13359e3619f81d2589febb6dcb1f92f1a8418a4e93dd736f3f336ca6b6e069fe.jpg}})

## 8.18.11.2 TASKS\_SAMPLE

## Address offset: 0x004

Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS\_STARTED was set and EVENTS\_STOPPED was not.

![]({{img:images/b96a7cf025fbd45c485c94d622d67985dcfd410c21cbe2c15f4513d776fbb973.jpg}})

## 8.18.11.3 TASKS\_STOP

Address offset: 0x008

Stop the ADC and terminate any on-going conversion

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/5fdc6e8d7bd97713c5d2cfdc3e760a0f0adc808a49313bf0f407ac25884a5e36.jpg}})

## 8.18.11.4 TASKS\_CALIBRATEOFFSET

Address offset: 0x00C

Starts offset auto-calibration

![]({{img:images/97a278bf0209d05b45296b80ad1be7e08dfa066e590cb356c98b2c1285df9161.jpg}})

## 8.18.11.5 SUBSCRIBE\_START

Address offset: 0x080

Subscribe configuration for task START

![]({{img:images/6eee7dce3750a7dee7e23c4f2587f0c2eda82c8f35ba63daed398c2f26e6f128.jpg}})

## 8.18.11.6 SUBSCRIBE\_SAMPLE

Address offset: 0x084

Subscribe configuration for task SAMPLE

![]({{img:images/33d21a190f7717459ad2f032e27cde8b885f1f7406fff59e1a345a7e35bcec7e.jpg}})

## 8.18.11.7 SUBSCRIBE\_STOP

Address offset: 0x088

Subscribe configuration for task STOP

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/d6958b157a304bdee6ded14b576bb08350bf6f85e6ebeb24e960481f583a6ffc.jpg}})

## 8.18.11.8 SUBSCRIBE\_CALIBRATEOFFSET

Address offset: 0x08C

Subscribe configuration for task CALIBRATEOFFSET

![]({{img:images/53119b9c4fa69cf164265d4bb6bd451c6c38e013fb18fec01f2bdef828261abf.jpg}})

## 8.18.11.9 EVENTS\_STARTED

Address offset: 0x100

The ADC DMA has started

![](picture_1586.jpg)

## 8.18.11.10 EVENTS\_END

Address offset: 0x104

The ADC has filled up the Result buffer

![]({{img:images/287428083a739e66f8ebacfe0c455414165ae56cfbe35584f8c78eb23b97b84c.jpg}})

## 8.18.11.11 EVENTS\_DONE

Address offset: 0x108

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.

![]({{img:images/35a63a92d3ef4173a5de8dcb516635b697fc03fe38cdf54efe1bf92cdf327975.jpg}})

## 8.18.11.12 EVENTS\_RESULTDONE

Address offset: 0x10C

A result is ready to get transferred to RAM.

![]({{img:images/b5996161dad1f6caccef7cb9092404096a50a7ae379e38a13c48ee2c2088d45c.jpg}})

## 8.18.11.13 EVENTS\_CALIBRATEDONE

Address offset: 0x110

Calibration is complete

![]({{img:images/da1e5ef41571964ca60bcab38b40e0cc02c1dd58904354681023dd55289dbc5b.jpg}})

## 8.18.11.14 EVENTS\_STOPPED

Address offset: 0x114

The ADC DMA has stopped

![]({{img:images/1f33ceaf8839e246cc305caceb17fd5e504d528c69caf369b31556e0792a0177.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.18.11.15 EVENTS\_CH[n] (n=0..7)

Peripheral events.

## 8.18.11.15.1 EVENTS\_CH[n].LIMITH (n=0..7)

Address offset: 0x118 + (n × 0x8)

Last results is above CH[n].LIMIT.HIGH

![]({{img:images/0ce708abc2e8030cb3e1b6f2a490d6e938b2ffda1aa098a93e0b5a7233419b29.jpg}})

## 8.18.11.15.2 EVENTS\_CH[n].LIMITL (n=0..7)

Address offset: 0x11C + (n × 0x8)

Last results is below CH[n].LIMIT.LOW

![]({{img:images/b9e684a65e5c47f3195fa57a32c7d023d6314c6bbba816fbce021bd9b5a33cda.jpg}})

## 8.18.11.16 PUBLISH\_STARTED

Address offset: 0x180

Publish configuration for event STARTED

![]({{img:images/05c0196103e04af979693174c059d5a0735ad66369c3fcfd1d7b93b306d1ca05.jpg}})

## 8.18.11.17 PUBLISH\_END

Address offset: 0x184

Publish configuration for event END

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/d67ee193a74a21def0cfd490d716bc75dd8f183cebca7601357a5992587b6314.jpg}})

## 8.18.11.18 PUBLISH\_DONE

Address offset: 0x188

Publish configuration for event DONE

![]({{img:images/50123c8691ac03abf0d380368a4bec31988e2592e836854a908f5d358851b934.jpg}})

## 8.18.11.19 PUBLISH\_RESULTDONE

Address offset: 0x18C

Publish configuration for event RESULTDONE

![]({{img:images/bf36049cf286e4ded7172b516f1fa193ea4581b768a36058b958d9b67ebffae8.jpg}})

## 8.18.11.20 PUBLISH\_CALIBRATEDONE

Address offset: 0x190

Publish configuration for event CALIBRATEDONE

![]({{img:images/146bed4c52f11a646654c2c6c1ea88b12c707c6378052d2408a70108f55f9aaa.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event CALIBRATEDONE will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.18.11.21 PUBLISH\_STOPPED

Address offset: 0x194

Publish configuration for event STOPPED

![]({{img:images/ce5bbe473ed246881e7be0ad4c91121f1a0fa642fc02d1fcbb0010f20a318959.jpg}})

## 8.18.11.22 PUBLISH\_CH[n] (n=0..7)

Publish configuration for events

## 8.18.11.22.1 PUBLISH\_CH[n].LIMITH (n=0..7)

Address offset: 0x198 + (n × 0x8)

Publish configuration for event CH[n].LIMITH

![]({{img:images/47de60a3aa3a1ea38f357a7041470fbcd3bbae78fb4ac05ad1d454de6e269de5.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event CH[n].LIMITH will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.18.11.22.2 PUBLISH\_CH[n].LIMITL (n=0..7)

Address offset: 0x19C + (n × 0x8)

Publish configuration for event CH[n].LIMITL

![]({{img:images/5bd38e31e370daa6c210004ec75db359e5ad980d02e2a67d2ace34289ef14bcf.jpg}})

## 8.18.11.23 SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/b6a4e67a8f3a47a609f7a036d7f0acd3b8da9108057c0ef4022c5d6962d241a7.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID B A | ID B A | ID B A | ID B A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID Value | Description |
| A | RW DONE_SAMPLE |  | Shortcut between event DONE and task SAMPLE |
|  |  | Disabled 0 | Disable shortcut |
|  |  | Enabled 1 | Enable shortcut |
| B | RW END_START |  | Shortcut between event END and task START |
|  |  | Disabled 0 | Disable shortcut |
|  |  | Enabled 1 | Enable shortcut |

## 8.18.11.24 INTEN

Address offset: 0x300

Enable or disable interrupt

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 |  |  |  |  |  |  |  | 0 | 1 |
| ------------------ | ----- | --------------- | ------------------------------ | ----- | --------- | ---------------- | ------------------- | --------- | --------------------- | ----------- | --------- | ------- |
| ID |  |  | U T |  |  | V | S R Q P | O E D C | N M L I H G F | K J B A |  |  |
| Reset 0x00000000 |  |  | 0 0 0 0 | 0 0 | 0 0 0 0 | 0 0 0 0 | 0 0 0 | 0 0 | 0 0 0 | 0 0 0 | 0 0 0 0 | 0 0 0 |
| ID | R/W | Field | Value ID |  | Value | Description |  |  |  |  |  |  |
| A | RW | STARTED | Disabled<br>Enabled | 0<br>1 |  | Enable<br>or<br>Disable<br>Enable | disable interrupt | for | event STARTED |  |  |  |
| B | RW | END | disable<br>Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | interrupt | for | event END |  |  |  |
| C | RW | DONE | Disabled | 0 | Enable | Enable or<br>Disable | disable interrupt | for | event DONE |  |  |  |
| D | RW | RESULTDONE | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable Enable | disable interrupt | for | event RESULTDONE |  |  |  |
| E | RW | CALIBRATEDONE | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable interrupt | for | event CALIBRATEDONE |  |  |  |
| F | RW | STOPPED | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable interrupt | for | event STOPPED |  |  |  |
| G | RW | CH0LIMITH | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable interrupt | for | event | CH0LIMITH |  |  |
| H | RW | CH0LIMITL | Disabled | 0 |  | Enable or<br>Disable | disable interrupt | for | event | CH0LIMITL |  |  |
| I | RW | CH1LIMITH | Disabled<br>1<br>Enabled | 0 |  | Enable<br>Enable or<br>Disable<br>Enable | disable interrupt<br>disable | for | event | CH1LIMITH |  |  |
| J | RW | CH1LIMITL | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | interrupt | for | event | CH1LIMITL |  |  |
| K | RW | CH2LIMITH | disable<br>Disabled | 0 |  | Enable or<br>Disable | interrupt | for | event | CH2LIMITH |  |  |

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 | 1 |
| ------------------ | ------------------ | ---------- | ------------------------------ | ------------------------------ |
| ID |  |  |  | V U T S R Q P O N M L K J I H G F E D C B |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value | Description |
| L RW | CH2LIMITL |  |  | Enable or disable interrupt for event CH2LIMITL |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| M RW | CH3LIMITH |  |  | Enable or disable interrupt for event CH3LIMITH |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| N RW | CH3LIMITL |  |  | Enable or disable interrupt for event CH3LIMITL |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| O RW | CH4LIMITH |  |  | Enable or disable interrupt for event CH4LIMITH |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| P RW | CH4LIMITL |  |  | Enable or disable interrupt for event CH4LIMITL |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| Q RW | CH5LIMITH |  |  | Enable or disable interrupt for event CH5LIMITH |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| R RW | CH5LIMITL |  |  | Enable or disable interrupt for event CH5LIMITL |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| S RW | CH6LIMITH |  |  | Enable or disable interrupt for event CH6LIMITH |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| T RW | CH6LIMITL |  |  | Enable or disable interrupt for event CH6LIMITL |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| U RW | CH7LIMITH |  |  | Enable or disable interrupt for event CH7LIMITH |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |
| V | RW CH7LIMITL |  |  | Enable or disable interrupt for event CH7LIMITL |
|  |  | Disabled | 0 | Disable |
|  |  | Enabled | 1 | Enable |

## 8.18.11.25 INTENSET

Address offset: 0x304

Enable interrupt

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------------------------------ |
| ID |  | V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW STARTED |  | Write '1' to enable interrupt for event STARTED |
|  | Set | 1 Enable |
|  | Disabled | 0 Read: Disabled |
|  | Enabled | 1 Read: Enabled |
| B RW END |  | Write '1' to enable interrupt for event END |
|  | Set | 1 Enable |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 |
| ------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID |  |  | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description | Description |
|  |  | Disabled | 0 | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled |
| C | RW DONE |  |  | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event | Write '1' to enable interrupt for event |
|  |  | Set Disabled | 1 | Enable Read: Disabled | 0 | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled | Enable Read: Disabled |
|  | RW RESULTDONE | Enabled | 1 | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable | Read: Enabled Write '1' to enable |
| D F | Set RW CALIBRATEDONE RW STOPPED | Disabled Enabled Set Disabled Enabled | 1 0 | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | 1 1 0 1 | '1' | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable | interrupt for event RESULTDONE Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CALIBRATEDONE Enable Read: Disabled Read: Enabled Write to enable |
| E G H I | Set RW CH0LIMITH Set RW CH0LIMITL Set RW RW CH1LIMITL RW CH2LIMITH | Disabled Enabled Disabled Enabled Set Disabled Enabled Set | 1 0 | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled | Read: Disabled Read: Enabled Write to enable Read: Disabled Read: Enabled Write to enable Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled |
| K | CH1LIMITH<br>Disabled | Enabled | 1 | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled |
|  | RW CH2LIMITL | Enabled Set Disabled | 1 | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL | Write '1' to enable interrupt for event CH2LIMITL |
| J |  |  | 1 0 1 | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable |
|  |  |  | 0<br>1 | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled | Read: Disabled Read: Enabled |
| L |  | Disabled<br>Enabled |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
|  | Set | Disabled Enabled | 1 1 0 1 | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable | Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable |
|  | CH3LIMITH | Set Disabled Enabled |  | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for | Read: Disabled Read: Enabled Write '1' to enable interrupt for |
| M | RW CH3LIMITL |  |  | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL |
|  | RW |  |  | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable | Enable |
|  |  |  |  | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for | Write '1' to enable interrupt for |
|  |  |  |  | event | event | event | event | event | event | event | event | event | event | event | event | event | event | event | event | event | event |
|  |  |  | 1<br>0<br>1 | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable | CH3LIMITH Enable |
| N |  | Set | 1 | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL | event CH3LIMITL |
|  |  | Disabled | 0 | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled | Read: Enabled |

| Bit number ID |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 0 V U T S R Q P O N M L K J I |
| ----------------- | -------------- | ---------- | ------------------------------ | ------------------------------ |
|  |  |  | 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value | Description |
| O RW | CH4LIMITH |  |  | Write '1' to enable interrupt for event CH4LIMITH |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| P RW | CH4LIMITL |  |  | Write '1' to enable interrupt for event CH4LIMITL |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| Q RW | CH5LIMITH |  |  | Write '1' to enable interrupt for event CH5LIMITH |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| R RW | CH5LIMITL |  |  | Write '1' to enable interrupt for event CH5LIMITL |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| S RW | CH6LIMITH |  |  | Write '1' to enable interrupt for event CH6LIMITH |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| T RW | CH6LIMITL |  |  | Write '1' to enable interrupt for event CH6LIMITL |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| U | RW CH7LIMITH |  |  | Write '1' to enable interrupt for event CH7LIMITH |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| V | RW CH7LIMITL |  |  | Write '1' to enable interrupt for event CH7LIMITL |
|  |  | Set | 1 | Enable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |

## 8.18.11.26 INTENCLR

Address offset: 0x308

Disable interrupt

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------------------------------ |
| ID |  | V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW STARTED |  | Write '1' to disable interrupt for event STARTED |
|  | Clear | 1 Disable |
|  | Disabled | 0 Read: Disabled |
|  | Enabled | 1 Read: Enabled |
| B RW END |  | Write '1' to disable interrupt for event END |
|  | Clear | 1 Disable |
|  | Disabled | 0 Read: Disabled |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

| Bit number |  |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| -------------- | ------------------------- | ------------------------------ | ------- | ------------------------------ |
| ID Reset | 0x00000000 |  |  | V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
|  |  | Enabled | 1 | Read: Enabled |
| C | RW DONE | Clear |  | Write '1' to disable interrupt for event DONE Disable |
| D | RW RW | Clear | 1 | interrupt for event RESULTDONE Read: Enabled Write '1' to disable interrupt for event Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event STOPPED |
|  | RESULTDONE | Disabled Enabled |  | Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event Disable |
| E | CALIBRATEDONE | Clear Disabled Enabled | 0 1 | CALIBRATEDONE CH0LIMITH Read: Disabled |
| F | RW STOPPED RW CH0LIMITH | Clear Disabled Enabled Clear Disabled | 1 | Read: Disabled |
| G | RW CH0LIMITL | Enabled Enabled Clear Disabled | 1 0 1 | interrupt for event CH0LIMITL Disable Read: Disabled Read: Enabled |
| H |  | Clear Disabled Enabled |  | Write '1' to disable interrupt for event |
|  | RW<br>RW CH1LIMITH RW | Enabled<br>Clear Disabled | 1 0 | CH2LIMITL Disable Read: Disabled |
|  | CH1LIMITL | Clear Disabled | 1 | Read: Enabled Write '1' to disable interrupt for event CH3LIMITH Disable |
| M | CH2LIMITH CH2LIMITL | Enabled Clear<br>Disabled Enabled | 0 1 | Read: Disabled<br>Read: Enabled |
| N | CH3LIMITL | Clear | 1 | Write '1' to disable interrupt for event CH3LIMITL Disable |
|  | RW<br>RW | Disabled Enabled | 0<br>1 | Read: Disabled<br>Disable Read: Disabled Read: Enabled |
|  |  | Clear Disabled Enabled | 1 0<br>1 | Disable Read: Disabled event CH2LIMITH<br>Read: Enabled |
| I |  |  | 1 0<br>1 | Write '1' to disable interrupt for event CH1LIMITH<br>for |
| J |  |  | 1 | Write '1' to disable interrupt event CH1LIMITL |
|  |  |  | 0 1 | Disable |
| K | CH3LIMITH |  |  | Read: Enabled Write '1' to disable interrupt for |
| L | RW<br>CH4LIMITH |  | 1 | Read: Enabled<br>interrupt for event CH4LIMITH |
| O | RW |  |  | disable<br>Write '1' to |

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 | 2 1 0 |
| ------------------ | ------------------ | ---------- | ------------------------------ | ------------------------------ |
| ID |  |  |  | V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| P RW | CH4LIMITL |  |  | Write '1' to disable interrupt for event CH4LIMITL |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| Q RW | CH5LIMITH |  |  | Write '1' to disable interrupt for event CH5LIMITH |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| R RW | CH5LIMITL |  |  | Write '1' to disable interrupt for event CH5LIMITL |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| S RW | CH6LIMITH |  |  | Write '1' to disable interrupt for event CH6LIMITH |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| T RW | CH6LIMITL |  |  | Write '1' to disable interrupt for event CH6LIMITL |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| U | RW CH7LIMITH |  |  | Write '1' to disable interrupt for event CH7LIMITH |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| V | RW CH7LIMITL |  |  | Write '1' to disable interrupt for event CH7LIMITL |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |

## 8.18.11.27 STATUS

Address offset: 0x400

Status

![]({{img:images/c384d909cfcac2a5711799518496825e27e1084124b6a4adfd0e32dd8a762e7b.jpg}})

## 8.18.11.28 TRIM.LINCALCOEFF[n] (n=0..5)

Address offset: 0x440 + (n × 0x4)

Linearity calibration coefficient

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/ed3ea34bb513f4ea7042012a8ca83ca0781ab8c715e84e4cfb0ef615bd90cd5e.jpg}})

## 8.18.11.29 ENABLE

Address offset: 0x500

Enable or disable ADC

![]({{img:images/0dc0796b2eb930cf76df2019549eed2a64db769d97bee3a3a0c885b3a0f9ad57.jpg}})

When enabled, the ADC will acquire access to the GPIO pins specified in the CH[n].PSELP and CH[n].PSELN registers.

## 8.18.11.30 CH[n].PSELP (n=0..7)

Address offset: 0x510 + (n × 0x10)

Input positive pin selection for CH[n]

![]({{img:images/cdee2d1703d60c0b2fea9b3471921ed57421713009639cd74004d85ad9c57296.jpg}})

| Bit number | Bit number | Bit number | Bit number | Bit number |
| -------------- | -------------- | -------------- | -------------- | -------------- |

## 8.18.11.31 CH[n].PSELN (n=0..7)

Address offset: 0x514 + (n × 0x10)

Input negative pin selection for CH[n]

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/3dcf4f1037a096c74f7420d7d16ac165ccc1616dcecac2109d65145ca1c64217.jpg}})

## 8.18.11.32 CH[n].CONFIG (n=0..7)

Address offset: 0x518 + (n × 0x10)

Input configuration for CH[n]

| Bit number |  |  | 31 30 29 28 27 26 25 24 |  |  |  | 23 22 21 20 19 18 | 17 16 15 14 13 | 6 5 4 3 | 2 1 0 |
| ------------------ | ------------------ | ---------- | --------------------------- | ----- | ---- | ----- | ------------------------- | --------------------------- | ------------------ | ---------------- |
| ID |  |  |  | F F |  |  | E E E E E E E | E D |  |  |
| Reset 0x00020000 | Reset 0x00020000 |  | 0 | 0 0 | 0 | 0 0 | 0 0 0 0 0 0 0 | 0 0 0 | 0 0 | 0 0 0 0 |
| ID | R/W Field | ID | Value |  |  |  | Description |  |  | 0 |
| A | RW GAIN | Value<br>Gain2<br>Gain1<br>Gain2_3<br>Gain2_4<br>Gain2_5<br>Gain2_6<br>Gain2_8 | 0<br>1<br>2<br>3<br>4<br>5<br>7 |  |  |  | Gain control<br>2<br>1<br>2/3<br>2/4<br>2/5<br>2/6<br>2/8 |  |  |  |
| B RW | BURST | Disabled | 0 |  |  |  | Enable burst mode<br>Burst mode is disabled | (normal operation) |  |  |
|  |  | Enabled | 1 |  |  |  | Burst mode is enabled.<br>fast as it can, | SAADC takes<br>sends the average | number | of samples as |
| C- RW |  | REFSEL<br>Internal<br>External | 0<br>1 |  |  |  | Reference control<br>Internal reference (0.9<br>External reference | V)<br>given at PADC_EXT_REF_1V2 |  |  |
| D | RW | MODE |  |  |  |  | Enable differential | mode |  |  |
|  |  | SE<br>Diff | 0 |  |  |  | Single ended, PSELN<br>Differential | will be ignored, | to ADC | shorted to GND |
| E | RW | TACQ | [1..319] |  |  |  | Acquisition time, the<br>Resulting acquistion | time the ADC is<br>time ((TACQ+1) | the input | voltage. |
| F | RW | TCONV | [1..7] |  |  |  | Conversion time. | Resulting conversion | ((TCONV+1) x 250 | ns) |

## 8.18.11.33 CH[n].LIMIT (n=0..7)

Address offset: 0x51C + (n × 0x10)

High/low limits for event monitoring a channel

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/c9f8f7d2c8f1be3b6d0bf9523c5102ad3c73ab56a7ad55fd6a638f420d4a5854.jpg}})

## 8.18.11.34 RESOLUTION

Address offset: 0x5F0

Resolution configuration

![]({{img:images/91218af6414b4462b36f56ee3dbfafa3b793657f7f449cebf376e2ff28366b17.jpg}})

## 8.18.11.35 OVERSAMPLE

Address offset: 0x5F4

Oversampling configuration. OVERSAMPLE should not be combined with SCAN unless burst is enabled. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.

![]({{img:images/1fb21e1ca9299234cd6d6172536547a1fe9aefd109c10f96657c65f921d85be1.jpg}})

## 8.18.11.36 SAMPLERATE

Address offset: 0x5F8

Configures the sampling rate for either task-triggered or continuous operation using a local timer

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/29569ff90f723073012ba7efd24f52f4888280fb8595b03bc15ad04991d86083.jpg}})

## 8.18.11.37 RESULT

RESULT EasyDMA channel

## 8.18.11.37.1 RESULT.PTR

Address offset: 0x62C

Data pointer

![]({{img:images/54faf383e8e332e94a1cee70656568854cc6fab0c6ca01f1b89649e1ed829902.jpg}})

## 8.18.11.37.2 RESULT.MAXCNT

Address offset: 0x630

Maximum number of buffer bytes to transfer. Note that one sample is two bytes.

![]({{img:images/b01de5e1bf236e892fa6e9c9f464dc901678e512aeefad77002256d1f52c3f2e.jpg}})

## 8.18.11.37.3 RESULT.AMOUNT

Address offset: 0x634

Number of buffer bytes transferred since last START, updated after the END or STOPPED events

![]({{img:images/5c531db18cab0cdc30e78f0e90170e3f3aa4c2b3871d04d2a29c1c1e9eb2f20e.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.18.11.37.4 RESULT.CURRENTAMOUNT

## Address offset: 0x638

Number of buffer bytes transferred since last START, continuously updated

![]({{img:images/0368886e46a46a33b0c8b8d7d7493c02691a700eee4b571b6cdb4671cf9362ef.jpg}})

A

R

AMOUNT

## 8.18.11.38 NOISESHAPE

## Address offset: 0x654

SAADC provides two operational noise shaping modes (one that prioritizes higher bandwith, while the other prioritizes higher accuracy) that allow trade-offs between ADC resolution, power consumption, and signal bandwidth.

Note: When using noise shaping, the first RESULTREADY event will take longer to arrive as the filters need to be filled with valid data.

![]({{img:images/20c9319a7236c9df1927692fa85c681c6d87ba2a02f131ce8cccda56eaed8804.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | Bit number | Bit number |
| -------------- | ------------------------------ | -------------- | -------------- |

## 8.19 SPIM - Serial peripheral interface controller with EasyDMA

The SPI controller peripheral (SPIM) with EasyDMA provides a full duplex, 4-wire synchronous serial communication interface.

The main features of SPIM are the following:

- EasyDMA direct transfer to and from RAM
- SPI mode [0..3]
- Individual selection of I/O pins
- Optional D/CX output line for distinguishing between command and data bytes

Number of buffer bytes transferred since last START, continuously updated.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## · Optional hardware controlled chip select (CSN)

Figure 135: SPIM with EasyDMA

![]({{img:images/594dfb526c47175dd5c6cda14f2fbeb0e105560a9ee6cf9ea0e718c12bf35e04.jpg}})

## 8.19.1 SPIM transaction sequence

An SPIM transaction is started by triggering the START task. This initiates a number of bytes to be transmitted/received on SDO/SDI.

The following figure illustrates an SPIM transaction.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Figure 136: SPIM transaction

![]({{img:images/8fcfd5f43e5203387ca5129ee83ce14a2902be5f1348fa9f2a3fa1ad6e5dce59.jpg}})

The ENDTX event is generated when all bytes in buffer DMA.TX.PTR on page 589 are transmitted. The number of bytes in the transmit buffer is specified in register DMA.TX.MAXCNT on page 590. The ENDRX event is generated when buffer DMA.RX.PTR on page 587 is full; that is when the number of bytes specified in register DMA.RX.MAXCNT on page 587 have been received. The transaction stops automatically after all bytes are transmitted or received. When the maximum number of bytes in the receive buffer is larger than the number of bytes in the transmit buffer, the contents of register ORC on page 585 will be transmitted after the last byte in the transmit buffer has been transmitted.

The END event is generated after both the ENDRX and ENDTX events have been generated.

SPIM is stopped by triggering the STOP task. A STOPPED event is generated when the SPIM has stopped. If the STOP task is triggered in the middle of a transaction, SPIM completes the process for the current byte before stopping. The STOPPED event is generated even if the STOP task is triggered while there is no ongoing transaction.

If the ENDTX event has not been generated when the SPIM peripheral stops, the ENDTX event will be generated, even if all bytes in the buffer  have not been transmitted.

If the ENDRX event has not been generated when the SPIM stops, the ENDRX event will be generated even if the buffer DMA.RX.PTR on page 587 is not full.

A transaction can be suspended and resumed using the SUSPEND and RESUME tasks, respectively. When the SUSPEND task is triggered, SPIM completes transmitting and receiving the current byte before it is suspended.

## 8.19.2 D/CX functionality

Some SPI targets, such as display drivers, require an additional signal from the SPIM to distinguish between command and data bytes. This line is called D/CX.

SPIM supports additional signals such as a D/CX output line. The D/CX line is set low for transmitting command bytes and high for transmitting data bytes.

The D/CX pin number is selected using . The number of command bytes that precede the data bytes is configured using DCXCNT on page 585. Writing to DCXCNT on page 585 during an ongoing transmission is not allowed.

The following figure shows D/CX in use, where SPIM.DCXCNT= 1 .

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 137: D/CX example

![]({{img:images/97bfcd6f609846fcb134ad4aa24e96999d9a646b7bbff4c688f025f925eb51cd.jpg}})

## 8.19.3 Chip select hardware control

To use CSN hardware control, set register PSEL.CSN on page 587 according to the Pin configuration on page 567.

When enabled, CSN is asserted automatically after TASKS\_START on page 571 is triggered, and deasserted after EVENTS\_END on page 575. The value in register IFTIMING.CSNDUR on page 584 sets the time between the falling edge of CSN and the first SCK edge. The same delay is used between the last SCK edge and the rising edge of CSN at the end of a transfer. It is also used between two transfers as the minimum CSN inactive time when the END\_START short is enabled. The IFTIMING.CSNDUR is expressed in number of SPIM core clock periods.

The following figure shows a timing diagram with two SPI transmissions where the delay is controlled by IFTIMING.CSNDUR and is represented by tCSNDUR.

Figure 138: CSNDUR example

![]({{img:images/ece33341df9fa0bad6414574536c53acf341f79212e5fb386865f024ae72e90d.jpg}})

The following figure shows the timing delay for the combinations of polarity and phase settings. The register CSNPOL on page 585 determines the active polarity of the signal.

**Figure 138: CSNDUR example**

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 139: Polarity settings timing delay

![]({{img:images/753d38538487fe9f69e0adf39a3a372a6bfac3fdc150e96062c334c8ba7e31b3.jpg}})

## 8.19.4 Pin configuration

To configure pins for SPIM use, see the corresponding PSEL.n registers.

The contents of registers PSEL.SCK,  PSEL.CSN,  PSEL.DCX, PSEL.MOSI, and PSEL.MISO are only used when SPIM is enabled, and retained while the device is in System ON mode. The PSEL.n registers can be configured only when SPIM is disabled in register ENABLE on page 583.

To ensure correct behavior, the pins used by SPIM must be configured in the GPIO peripheral as described in GPIO configuration on page 567 before SPIM is enabled.

Only one peripheral can be assigned to drive a GPIO pin at a time. If more than one peripheral is assigned to a GPIO pin, it could result in unpredictable behavior.

Table 57: GPIO configuration

| SPIM signal | SPIM pin | Direction | Output value |
| --------------- | ------------------------------ | ------------- | --------------------- |
| SCK | As specified in PSEL.SCK on page 586 | Output | Same as CONFIG.CPOL |
| CSN | As specified in PSEL.CSN on page 587 | Output | Same as CONFIG.CPOL |
| DCX | As specified in PSEL.DCX on page 586 | Output | 1 |
| SDO | As specified in PSEL.MOSI on page 586 | Output | 0 |
| SDI | As specified in PSEL.MISO on page 586 | Input | Not applicable |

SPIM supports SPI modes [0..3]. The clock polarity (CPOL) and the clock phase (CPHA) are configured in register CONFIG on page 584.

**Table 57: GPIO configuration**

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Table 58: SPI modes

| Mode | Clock polarity (CPOL) | Clock phase (CPHA) |
| ----------- | ------------------------- | ---------------------- |
| SPI_MODE0 | 0 (Active High ) | 0 (Leading) |
| SPI_MODE1 | 0 (Active High ) | 1 (Trailing) |
| SPI_MODE2 | 1 (Active Low ) | 0 (Leading) |
| SPI_MODE3 | 1 (Active Low ) | 1 (Trailing) |

## 8.19.5 Shared resources

The SPIM peripheral shares registers and other resources with peripherals that have the same ID as SPIM. Before SPIM can be configured and used, all peripherals that have the same ID as SPIM must be disabled.

Disabling a peripheral with the same ID as SPIM will not reset any shared SPIM registers. Configure all SPIM registers to ensure they operate correctly.

See the Instantiation table in Instantiation on page 214 for details on peripherals and their IDs.

## 8.19.6 EasyDMA

SPIM uses EasyDMA to fetch data to transmit from RAM or store received data in RAM.

SPIM implements the following EasyDMA channels.

Table 59: SPIM EasyDMA channels

| Channel | Type | Register Cluster |
| ----------- | -------- | ------------------------ |
| TXD | READER | DMA.TX.PTR on page 589 |
| RXD | WRITER | DMA.RX.PTR on page 587 |

The .PTR and .MAXCNT registers are double-buffered. After receiving the STARTED event, the registers can be written to before the next transmission.

SPIM automatically stops transmitting after TXD.MAXCNT bytes have been transmitted and RXD.MAXCNT bytes have been received. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined in the ORC register. If TXD.MAXCNT is larger than RXD.MAXCNT, the additional received bytes will be discarded.

The RX.END and TX.END events indicate that EasyDMA has finished accessing buffers in RAM. Both RX and TX must be finished before the END event is generated.

If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion can occur. In this case, the EasyDMA channel behavior will depend on the SPIM instance. Refer to Instances on page 569 for information about what behavior is expected in each instance.

See EasyDMA for more detailed information.

## 8.19.7 Low power

When the peripheral is not needed, stop and disable SPIM to ensure lowest possible power consumption.

When the STOP task is sent, the software must wait until the STOPPED event is received before disabling the peripheral through the ENABLE register. If the peripheral is already stopped, the STOP task is not needed to ensure data is not lost.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.19.8 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| ------------------------ | ---------- | ----------------------- | ------------- | ------------- | ------------- | --------- | ----------------------- |
|  |  |  | Map | Att | DMA | access |  |
| SPIM00 : S SPIM00 : NS | GLOBAL | 0x5004A000 0x4004A000 | US | S | SA | No | SPI controller SPIM00 |
| SPIM20 : S SPIM20 : NS | GLOBAL | 0x500C6000 0x400C6000 | US | S | SA | No | SPI controller SPIM20 |
| SPIM21 : S SPIM21 : NS | GLOBAL | 0x500C7000 0x400C7000 | US | S | SA | No | SPI controller SPIM21 |
| SPIM22 : S SPIM22 : NS | GLOBAL | 0x500C8000 0x400C8000 | US | S | SA | No | SPI controller SPIM22 |
| SPIM30 : S SPIM30 : NS | GLOBAL | 0x50104000 0x40104000 | US | S | SA | No | SPI controller SPIM30 |


| Instance | Domain | Configuration |
| ------------------------ | ---------- | ------------------------------ |
| SPIM00 : S SPIM00 : NS | GLOBAL | Use dedicated pins on GPIO port P2 CSN functionality is supported. DCX functionality is supported. Peripheral core frequency is 128 MHz. Prescaler divisor range is 4..126 |
| SPIM20 : S SPIM20 : NS | GLOBAL | DCX functionality is supported. Peripheral core frequency is 16 MHz. |
| SPIM21 : S SPIM21 : NS | GLOBAL | DCX functionality is supported. Peripheral core frequency is 16 MHz. Prescaler divisor range is 2..126 |
| SPIM22 : S SPIM22 : NS | GLOBAL | Use GPIO port P1 CSN functionality is supported. DCX functionality is supported. |
| SPIM30 : S | GLOBAL | Prescaler divisor range is 2..126 Use GPIO port P0 CSN functionality is supported. DCX functionality is supported. |
| SPIM30 : NS |  | Peripheral core frequency is 16 MHz. |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})


| Register | Offset | TZ | Description |
| ------------------------------ | ------------- | ------ | ------------------------------ |
| TASKS_START | 0x000 |  | Start SPI transaction |
| TASKS_STOP | 0x004 |  | Stop SPI transaction |
| TASKS_SUSPEND | 0x00C |  | Suspend SPI transaction |
| TASKS_RESUME | 0x010 |  | Resume SPI transaction |
| TASKS_DMA.RX.ENABLEMATCH[n] | 0x030 |  | Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. |
| TASKS_DMA.RX.DISABLEMATCH[n] | 0x040 |  | Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. |
| SUBSCRIBE_START | 0x080 |  | Subscribe configuration for task START |
| SUBSCRIBE_STOP | 0x084 |  | Subscribe configuration for task STOP |
| SUBSCRIBE_SUSPEND | 0x08C |  | Subscribe configuration for task SUSPEND |
| SUBSCRIBE_RESUME | 0x090 |  | Subscribe configuration for task RESUME |
| SUBSCRIBE_DMA.RX.ENABLEMATCH[n] | 0x0B0 |  | Subscribe configuration for task ENABLEMATCH[n] |
| SUBSCRIBE_DMA.RX.DISABLEMATCH[n] | 0x0C0 |  | Subscribe configuration for task DISABLEMATCH[n] |
| EVENTS_STARTED | 0x100 |  | SPI transaction has started |
| EVENTS_STOPPED | 0x104 |  | SPI transaction has stopped |
| EVENTS_END | 0x108 |  | End of RXD buffer and TXD buffer reached |
| EVENTS_DMA.RX.END | 0x14C |  | Generated after all MAXCNT bytes have been transferred |
| EVENTS_DMA.RX.READY | 0x150 |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.RX.BUSERROR | 0x154 |  | An error occured during the bus transfer. |
| EVENTS_DMA.RX.MATCH[n] | 0x158 |  | Pattern match is detected on the DMA data bus. |
| EVENTS_DMA.TX.END | 0x168 |  | Generated after all MAXCNT bytes have been transferred |
| EVENTS_DMA.TX.READY | 0x16C |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.TX.BUSERROR | 0x170 |  | An error occured during the bus transfer. |
| PUBLISH_STARTED | 0x180 |  | Publish configuration for event STARTED |
| PUBLISH_STOPPED | 0x184 |  | Publish configuration for event STOPPED |
| PUBLISH_END | 0x188 |  | Publish configuration for event END |
| PUBLISH_DMA.RX.END | 0x1CC |  | Publish configuration for event END |
| PUBLISH_DMA.RX.READY | 0x1D0 |  | Publish configuration for event READY |
| PUBLISH_DMA.RX.BUSERROR | 0x1D4 |  | Publish configuration for event BUSERROR |
| PUBLISH_DMA.RX.MATCH[n] | 0x1D8 |  | Publish configuration for event MATCH[n] |
| PUBLISH_DMA.TX.END | 0x1E8 |  | Publish configuration for event END |
| PUBLISH_DMA.TX.READY | 0x1EC |  | Publish configuration for event READY |
| PUBLISH_DMA.TX.BUSERROR | 0x1F0 |  | Publish configuration for event BUSERROR |
| SHORTS | 0x200 |  | Shortcuts between local events and tasks |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| ENABLE | 0x500 |  | Enable SPIM |
| PRESCALER | 0x52C |  | The prescaler is used to set the SPI frequency. |
| CONFIG | 0x554 |  | Configuration register |
| IFTIMING.RXDELAY | 0x5AC |  | Sample delay for input serial data on SDI |
| IFTIMING.CSNDUR | 0x5B0 |  | Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. |
| DCXCNT | 0x5B4 |  | DCX configuration |
| CSNPOL | 0x5B8 |  | Polarity of CSN output |
| ORC | 0x5C0 |  | Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT |
| PSEL.SCK | 0x600 |  | Pin select for SCK |
| PSEL.MOSI | 0x604 |  | Pin select for SDO signal |
| PSEL.MISO PSEL.DCX | 0x608 0x60C |  | Pin select for SDI signal Pin select for DCX signal |
| Register | Offset | TZ | Description |
| PSEL.CSN | 0x610 |  | Pin select for CSN |
| DMA.RX.PTR | 0x704 |  | RAM buffer start address |
| DMA.RX.MAXCNT | 0x708 |  | Maximum number of bytes in channel buffer |
| DMA.RX.AMOUNT | 0x70C |  | Number of bytes transferred in the last transaction, updated after the END event.<br>Also updated after each MATCH event. |
| DMA.RX.LIST | 0x714 |  | EasyDMA list type |
| DMA.RX.TERMINATEONBUSERROR | 0x71C |  | Terminate the transaction if a BUSERROR event is detected. |
| DMA.RX.BUSERRORADDRESS | 0x720 |  | Address of transaction that generated the last BUSERROR event. |
| DMA.RX.MATCH.CONFIG | 0x724 |  | Configure individual match events |
| DMA.RX.MATCH.CANDIDATE[n] | 0x728 |  | The data to look for - any match will trigger the MATCH[n] event, if enabled. |
| DMA.TX.PTR | 0x73C |  | RAM buffer start address |
| DMA.TX.MAXCNT | 0x740 |  | Maximum number of bytes in channel buffer |
| DMA.TX.AMOUNT | 0x744 |  | Number of bytes transferred in the last transaction, updated after the END event.<br>Also updated after each MATCH event. |
| DMA.TX.LIST | 0x74C |  | EasyDMA list type |
| DMA.TX.TERMINATEONBUSERROR | 0x754 |  | Terminate the transaction if a BUSERROR event is detected. |
| DMA.TX.BUSERRORADDRESS | 0x758 |  | Address of transaction that generated the last BUSERROR event. |

## 8.19.8.1 TASKS\_START

Address offset: 0x000

Start SPI transaction

![]({{img:images/bb057d1398071e8df04c13473c341056b96bfe6b8312dc6220351296e7e818a2.jpg}})

## 8.19.8.2 TASKS\_STOP

Address offset: 0x004

Stop SPI transaction

![]({{img:images/f1cccc148956254525ef37529187f2bac925346d5ebcc110d883c9d1ef14fa66.jpg}})

## 8.19.8.3 TASKS\_SUSPEND

Address offset: 0x00C

Suspend SPI transaction

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/ba0f02f9798bef6e50ee5150e81dd288227d7c5244d8845c29271cd4502e6e69.jpg}})

## 8.19.8.4 TASKS\_RESUME

Address offset: 0x010

Resume SPI transaction

![]({{img:images/153e1bf503601b98428e07a4a70b5e7a77ef0c172735091f01f5448aebbf79e7.jpg}})

## 8.19.8.5 TASKS\_DMA

Peripheral tasks.

## 8.19.8.5.1 TASKS\_DMA.RX

Peripheral tasks.

## 8.19.8.5.1.1 TASKS\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x030 + (n × 0x4)

Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.

![]({{img:images/d3bad9c22802d10bd157629bc9dd48693c04bc6e247f7555b27afd3a33fd9e92.jpg}})

## 8.19.8.5.1.2 TASKS\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x040 + (n × 0x4)

Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.

![]({{img:images/1896e658a16df902081d0c9edf3018fce356eede6a27d0daf660f800002d2b01.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.19.8.6 SUBSCRIBE\_START

Address offset: 0x080

Subscribe configuration for task START

![]({{img:images/078341e855775c2a7fd0d4175405f31d33e780ffac3d6ae1cd3c1d151084e567.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task START will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.19.8.7 SUBSCRIBE\_STOP

Address offset: 0x084

Subscribe configuration for task STOP

![]({{img:images/008e26b71808dcf6e3374c65d11078e86d0d703a5c23672dc1c6d5e013873692.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task STOP will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

## 8.19.8.8 SUBSCRIBE\_SUSPEND

Address offset: 0x08C

Subscribe configuration for task SUSPEND

![]({{img:images/3f37241c323fb4a6c6e543a99a40965c9e655f35b17dbc95e245d06c60b13097.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task SUSPEND will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.19.8.9 SUBSCRIBE\_RESUME

Address offset: 0x090

Subscribe configuration for task RESUME

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/e043ceb195763823b9a483e33faaac4cae64b6a33bc421c4f9d8a6e52971cbd7.jpg}})

## 8.19.8.10 SUBSCRIBE\_DMA

Subscribe configuration for tasks

## 8.19.8.10.1 SUBSCRIBE\_DMA.RX

Subscribe configuration for tasks

## 8.19.8.10.1.1 SUBSCRIBE\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x0B0 + (n × 0x4)

Subscribe configuration for task ENABLEMATCH[n]

![]({{img:images/9a03b382ffce12b331ece1224f38d735fa8a2dd99a2f51b74a44c88a5bfdd2a6.jpg}})

## 8.19.8.10.1.2 SUBSCRIBE\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task DISABLEMATCH[n]

![]({{img:images/854f2e6fa6c00f6506bf761ed6a3a2c5fe2c2f1883c6b212e3b10eae01bfb70e.jpg}})

## 8.19.8.11 EVENTS\_STARTED

Address offset: 0x100

SPI transaction has started

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/1b409d951282f0610a652d5198ccb59eab1fd184ca57bb52841c97337cff3a57.jpg}})

## 8.19.8.12 EVENTS\_STOPPED

Address offset: 0x104

SPI transaction has stopped

![]({{img:images/8d3370923875fced36b1d16645d42acfebfe9a6cba99293966981150e3b10909.jpg}})

## 8.19.8.13 EVENTS\_END

Address offset: 0x108

End of RXD buffer and TXD buffer reached

![]({{img:images/d2171b1e88e860d7b2057914cd6b794c0b4851ae7963ba151295d240d0e1cd3c.jpg}})

## 8.19.8.14 EVENTS\_DMA

Peripheral events.

## 8.19.8.14.1 EVENTS\_DMA.RX

Peripheral events.

## 8.19.8.14.1.1 EVENTS\_DMA.RX.END

Address offset: 0x14C

Generated after all MAXCNT bytes have been transferred

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/080c83017c2bb57f42f923aab6bc781c77da11f4dcd2fefc7d22caa5e06ddc72.jpg}})

## 8.19.8.14.1.2 EVENTS\_DMA.RX.READY

Address offset: 0x150

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/501a7d47d348f84bc4934e1f3252add89294f80a895a4c296e7a39978df8f17b.jpg}})

## 8.19.8.14.1.3 EVENTS\_DMA.RX.BUSERROR

Address offset: 0x154

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/92e6119d90aa2f938b3433d5b791a8315a5c17c641520e5fcec01c2468d77207.jpg}})

## 8.19.8.14.1.4 EVENTS\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x158 + (n × 0x4)

Pattern match is detected on the DMA data bus.

![]({{img:images/2a8fdd6afc44fa4f9f6759c855993d7505508b039da103fa0413ddd7dffcd30e.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.19.8.14.2 EVENTS\_DMA.TX

Peripheral events.

## 8.19.8.14.2.1 EVENTS\_DMA.TX.END

Address offset: 0x168

Generated after all MAXCNT bytes have been transferred

![]({{img:images/ab9527f927eaf3bedafcc9f3e5d487cdc434d707abcd45690c4e30af142f6da6.jpg}})

## 8.19.8.14.2.2 EVENTS\_DMA.TX.READY

Address offset: 0x16C

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/eddb455b8e38d5553d72a24ba9558d7616a3467ea815e90e9609cebe003c6dee.jpg}})

## 8.19.8.14.2.3 EVENTS\_DMA.TX.BUSERROR

Address offset: 0x170

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/96bca0576ee061dc04c5e6ceaffd51ef610636a0cc709d04d98f833f69be639a.jpg}})

## 8.19.8.15 PUBLISH\_STARTED

Address offset: 0x180

Publish configuration for event STARTED

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/71da6472b90894f69ecd3f76789c0c8c0306dbf774208674f481a51df94aa1fc.jpg}})

## 8.19.8.16 PUBLISH\_STOPPED

Address offset: 0x184

Publish configuration for event STOPPED

![]({{img:images/adf35f89bb7fc625223219a12045f55fcabfa49607eceb30b61204aaf64c5197.jpg}})

## 8.19.8.17 PUBLISH\_END

Address offset: 0x188

Publish configuration for event END

![]({{img:images/c1369b6fe46f23b77b4274348ebc80832ea13c182e5888e048dc48eff1b3b102.jpg}})

## 8.19.8.18 PUBLISH\_DMA

Publish configuration for events

## 8.19.8.18.1 PUBLISH\_DMA.RX

Publish configuration for events

## 8.19.8.18.1.1 PUBLISH\_DMA.RX.END

Address offset: 0x1CC

Publish configuration for event END

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/d88d337cdd1694759b65df7b721a6c843b57f59cac355f79f4ef505c5057a953.jpg}})

## 8.19.8.18.1.2 PUBLISH\_DMA.RX.READY

Address offset: 0x1D0

Publish configuration for event READY

![]({{img:images/ed7b69333175ce5dff685b62a572b4c3f63fa1ef5cb2445ecc9c305fcb76c154.jpg}})

## 8.19.8.18.1.3 PUBLISH\_DMA.RX.BUSERROR

Address offset: 0x1D4

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/f2c8fddff7aacfe38869d5ded1e93260657a82aae34676ea9656512206304975.jpg}})

## 8.19.8.18.1.4 PUBLISH\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x1D8 + (n × 0x4)

Publish configuration for event MATCH[n]

![]({{img:images/e0d26d0a788e25ff30291e5c7ffbef21793399270f8684981c834ca855fae7bb.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that event MATCH[n] will publish to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable publishing<br>1 Enable publishing |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## 8.19.8.18.2 PUBLISH\_DMA.TX

Publish configuration for events

## 8.19.8.18.2.1 PUBLISH\_DMA.TX.END

Address offset: 0x1E8

Publish configuration for event END

![]({{img:images/27bfb39a432ffb1010e7548a26e480a1fed412b0e1706db9e9b702ab3f17a94d.jpg}})

## 8.19.8.18.2.2 PUBLISH\_DMA.TX.READY

Address offset: 0x1EC

Publish configuration for event READY

![]({{img:images/f8abe1f946882d5e464423ff05db7fa16c37ef75bb2f6b9305cfc5941eb48fed.jpg}})

## 8.19.8.18.2.3 PUBLISH\_DMA.TX.BUSERROR

Address offset: 0x1F0

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/ca2d63ac80353d48ddab50270f9664f8b6ef4184defdd7c004c5cd5fba859e9c.jpg}})

## 8.19.8.19 SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/3a37edb5cd43f826b1db0eb6193611d0470683e0fdd0e3424cb28a94632bc6df.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | Bit number | Bit number |
| -------------- | ------------------------------ | -------------- | -------------- |

## 8.19.8.20 INTENSET


Enable interrupt

| Bit number |  |  |  | 31 30 | 29 28 | 22 21 | 23 20 | 3 2 1 | 0 |
| ------------------ | ----- | --------------- | ---------- | --------- | --------- | --------------- | ---------------------- | --------- | ----- |
| ID |  |  |  |  | M | G | H |  |  |
| Reset 0x00000000 |  |  |  | 0 0 0 | 0 | 0 0 | 0 0 | 0 0 0 | 0 |
| ID | R/W | Field | Value ID | Value |  |  | Description |  |  |
| A | RW | STARTED | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  | '1' | Write to<br>Enable<br>Read: Disabled<br>Read: Enabled |  |  |
| B | RW | STOPPED | Set<br>Disabled | 1<br>0 |  | Disabled | Write '1' to<br>Enable<br>Read: |  |  |
| C | RW | END | Set<br>Enabled | 1<br>1 |  | Write<br>Read: Enabled | Read: Enabled '1' to<br>Enable<br>Read: Disabled |  |  |
| D | RW | DMARXEND | Set<br>Disabled | 1<br>0 |  |  | Write '1' to<br>Enable<br>Read: Disabled |  |  |
| E | RW | DMARXREADY | Set<br>Disabled<br>Enabled | 1 |  |  | Read:<br>Write '1' to<br>Enable<br>Read: Disabled |  |  |
|  |  | DMARXBUSERROR |  | 0 |  | '1' | Write |  |  |

G-J

RW

DMARXMATCH[i] (i=0..3)

Write '1' to enable interrupt for event DMARXMATCH[i]

![]({{img:images/dc844bae687360ad3dc0ccea308269ecb6d640c2fc7aad4f347b50660a643b91.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | Bit number |
| -------------- | ------------------------------ | -------------- |

## 8.19.8.21 INTENCLR

Address offset: 0x308

Disable interrupt

| Bit number | Bit number | Bit number | Bit number |
| -------------- | -------------- | -------------- | -------------- |
| Bit number | 31 30 29 28 | Bit number | Bit number |

## 8.19.8.22 ENABLE

Address offset: 0x500

Enable SPIM

![]({{img:images/cdb3a7a92a55526dd37f4ce2bf103700f3d91a223d3377c4176fd3c158df1b24.jpg}})

## 8.19.8.23 PRESCALER

Address offset: 0x52C

The prescaler is used to set the SPI frequency.

The prescaler divides the core clock by the divisor to make the SPI clock. The resulting frequency is given by 'core clock' / DIVISOR. Different instances of the SPIM might have different core clocks. The SPIM core clock and divisor limits is given in the instance table in Instances on page 569.

Note that a low prescaler setting may require changing the default RXDELAY value to ensure correct sampling.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Only even numbers is allowed for the divisor.

![]({{img:images/320d83ea462430017fd20836dae6dc75d64d2d9fc3b981357be158f84bebb05e.jpg}})

## 8.19.8.24 CONFIG

Address offset: 0x554

Configuration register

![]({{img:images/935b7b7cffb1a65792f204864dc2a3ade0b264c0a314199dc1a49db0d53502e1.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID C B A | ID C B A | ID C B A | ID C B A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | Field | Value ID Value | Description |
| A | ORDER |  | Bit order |
|  |  | MsbFirst 0 | Most significant bit shifted out first |
|  |  | LsbFirst 1 | Least significant bit shifted out first |
| B | CPHA |  | Serial clock (SCK) phase |
|  |  | Leading 0 | Sample on leading edge of clock, shift serial data on trailing edge |
|  |  | Trailing 1 | Sample on trailing edge of clock, shift serial data on leading edge |
| C | CPOL |  | Serial clock (SCK) polarity |
|  |  | ActiveHigh | 0 Active high |
|  |  | ActiveLow | 1 Active low |

## 8.19.8.25 IFTIMING.RXDELAY

Address offset: 0x5AC

Sample delay for input serial data on SDI

If the value is written larger than the maximum value, the maximum value will be used.

![]({{img:images/00f648b74f4a6f7068835fba99814005b8887163a783a1d9cffd37ca44fd9377.jpg}})

## 8.19.8.26 IFTIMING.CSNDUR

## Address offset: 0x5B0

Minimum duration between edge of CSN and edge of SCK. When SHORTS.END\_START is used, this is also the minimum duration CSN must stay high between transactions.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/b3896c41c1549f1693bda254643696804758a7bafe68b3767b9d9373a0f580cd.jpg}})

## 8.19.8.27 DCXCNT

Address offset: 0x5B4

DCX configuration

![]({{img:images/cf15e0ed4a9aed713ca6d21453fdf3493b9499a78a42740bee3e93d7085093ca.jpg}})

## 8.19.8.28 CSNPOL

Address offset: 0x5B8

Polarity of CSN output

![]({{img:images/f881b505ae230e240b45900fe8651fae48b5bc5ed5e4fb8ce3fb98ffbae1e13e.jpg}})

## 8.19.8.29 ORC

Address offset: 0x5C0

Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT

![]({{img:images/e9db3f68003660be635bbd05499dd01617254619b6dd3189eaee607cff3bece3.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.19.8.30 PSEL.SCK

Address offset: 0x600

Pin select for SCK

![]({{img:images/f8583c735b8d4867479f2cf1a47731952475001d9e7a38e54f17c33abdf85cd3.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.19.8.31 PSEL.MOSI

Address offset: 0x604

Pin select for SDO signal

![]({{img:images/033efa47e27b67b3104159b3124a2fab5f1aa41d30077d0bd64c0b83bad4fc93.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.19.8.32 PSEL.MISO

Address offset: 0x608

Pin select for SDI signal

![]({{img:images/875d75c55047f3617e758b060d9365cc0478d16458f7f26f0b6583573ca14aff.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.19.8.33 PSEL.DCX

Address offset: 0x60C

Pin select for DCX signal

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/c83b371600abe13b221bd9a756e20cc072f4cb9f3e990e33e98a5d962719ab2e.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.19.8.34 PSEL.CSN

Address offset: 0x610

Pin select for CSN

![]({{img:images/ef4b8f76a9d4a5febbd20a50f5df3eee00878824fff40d23a8e5e2758cd99e07.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.19.8.35 DMA.RX.PTR

Address offset: 0x704

RAM buffer start address

![]({{img:images/aae0212bec92957b3fe50bdd2eb2ad881c3c492e1eb004be851525b39e2ccbfc.jpg}})

RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address.

Note: See the memory chapter for details about which memories are available for EasyDMA.

## 8.19.8.36 DMA.RX.MAXCNT

Address offset: 0x708

Maximum number of bytes in channel buffer

![]({{img:images/3ba4df655323a9306d4f0ee40bda02757dc1b5349b7c1f6d9286a00c042d1a5c.jpg}})

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.19.8.37 DMA.RX.AMOUNT

Address offset: 0x70C

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/200604e21d88ad45742e2fbb91077af00496ab42a6fb655178b5de4ac6c15867.jpg}})

## 8.19.8.38 DMA.RX.LIST

Address offset: 0x714

EasyDMA list type

![]({{img:images/cf76e8f700c733123e4daa56066af2260ed74a458175eab55e8815b05407e229.jpg}})

## 8.19.8.39 DMA.RX.TERMINATEONBUSERROR

Address offset: 0x71C

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/10882da1fdb012b05a8009846703df6b474f020bb586559815b3051d630c29cb.jpg}})

## 8.19.8.40 DMA.RX.BUSERRORADDRESS

Address offset: 0x720

Address of transaction that generated the last BUSERROR event.

![]({{img:images/624a81256566fbf29a7cfc66593d75866bb37ecc279ed52f3c129bf2477b1f73.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.19.8.41 DMA.RX.MATCH

Registers to control the behavior of the pattern matcher engine

## 8.19.8.41.1 DMA.RX.MATCH.CONFIG

Address offset: 0x724

Configure individual match events

![]({{img:images/027f71ba8f5c1bde97a3bf77d86b969b88f89003af01d86854cca76306b3101d.jpg}})

## 8.19.8.41.2 DMA.RX.MATCH.CANDIDATE[n] (n=0..3)

Address offset: 0x728 + (n × 0x4)

The data to look for - any match will trigger the MATCH[n] event, if enabled.

Note: This register can be updated while a transfer is in progress, but the new value will not take effect until a match has been found or the transfer is done. That makes it possible to write a new set of match words which will be searched for immediately after the event triggers.

![]({{img:images/1e20548e5764d8bdc910fd05448b655628bad114d63a229a52972ba0320fb17c.jpg}})

## 8.19.8.42 DMA.TX.PTR

Address offset: 0x73C

RAM buffer start address

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/aad1490162273c3f95ec76a1a2a63e660645574ccb1db6c2e35cea8a23e37db3.jpg}})

## 8.19.8.43 DMA.TX.MAXCNT

Address offset: 0x740

Maximum number of bytes in channel buffer

![]({{img:images/e07526b3c73412030c82e024c2a7c0f4af7389cf809425bc6321f10a767edf80.jpg}})

## 8.19.8.44 DMA.TX.AMOUNT

Address offset: 0x744

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/76198ee0bba0cc59beb162c09f4b602e88ff797c5c7d827128845454294503da.jpg}})

## 8.19.8.45 DMA.TX.LIST

Address offset: 0x74C

EasyDMA list type

![]({{img:images/47273ee9269c504c44d380625664999116c20fe5e490470e36be5c532344b437.jpg}})

## 8.19.8.46 DMA.TX.TERMINATEONBUSERROR

Address offset: 0x754

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/b24908062472b5558851dd6a9f77d4c80943e5376d9b7567b7100e8bfb292651.jpg}})

## 8.19.8.47 DMA.TX.BUSERRORADDRESS

Address offset: 0x758

Address of transaction that generated the last BUSERROR event.

![]({{img:images/b70c86008d110544d464f4a608d8b28d2def1962bfa9fb9110419dd393210c5d.jpg}})

## 8.20 SPIS - Serial peripheral interface target with EasyDMA

The SPI target peripheral (SPIS) with EasyDMA provides a full duplex, 4-wire synchronous serial communication interface.

The main features of SPIS are the following:

- EasyDMA direct transfer to and from RAM
- SPI mode [0..3]
- Individual selection of I/O pins
- Hardware-based semaphore mechanisms for synchronizing access to data buffers by SPIS and CPU

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 140: SPIS

![]({{img:images/97d739607c9c556865e0acc83f54f93b0f22bc41c8927e3a7168413f00e3c326.jpg}})

## 8.20.1 SPI modes

SPIS supports SPI modes [0..3]. Modes CPOL and CPHA are set in the CONFIG register.

Table 60: SPI modes

| Mode | Clock polarity (CPOL) | Clock phase (CPHA) |
| ----------- | ------------------------- | ------------------------ |
| SPI_MODE0 | 0 (Active High ) | 0 (Sample on Leading) |
| SPI_MODE1 | 0 (Active High ) | 1 (Sample on Trailing) |
| SPI_MODE2 | 1 (Active Low ) | 0 (Sample on Leading) |
| SPI_MODE3 | 1 (Active Low ) | 1 (Sample on Trailing) |

## 8.20.2 Shared resources

The SPIS peripheral shares registers and other resources with peripherals that have the same ID as SPIS. Before SPIS can be configured and used, all peripherals that have the same ID as SPIS must be disabled.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Disabling a peripheral with the same ID as SPIS will not reset any shared SPIS registers. Configure all SPIS registers to ensure they operate correctly.

See the Instantiation table in Instantiation on page 214 for details on peripherals and their IDs.

## 8.20.3 EasyDMA

SPIS implements EasyDMA for accessing RAM without CPU involvement. SPIS implements the EasyDMA channels found in the following table.

Table 61: SPIS EasyDMA Channels

| Channel | Type | Register Cluster |
| ----------- | -------- | -------------------- |
| TXD | READER | TXD |
| RXD | WRITER | RXD |

For detailed information regarding the use of EasyDMA, see EasyDMA on page 28.

If RXD.MAXCNT is greater than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined in the ORC register.

The END event indicates that EasyDMA is finished accessing the RAM buffer.

## 8.20.4 SPIS operation

SPIS uses two memory pointers. RXD.PTR points to the RXD buffer (receive buffer) and TXD.PTR points to the TXD buffer (transmit buffer). Because these buffers are located in RAM, which can be accessed by both SPIS and the CPU, a hardware based semaphore mechanism is implemented to enable safe sharing.

The CPU must acquire the SPI semaphore before it can safely update the RXD.PTR and TXD.PTR pointers. The ACQUIRE task must be triggered for the CPU to receive the ACQUIRED event and have access to the semaphore. When the CPU has updated the RXD.PTR and TXD.PTR pointers, the CPU must release the semaphore before SPIS can acquire it.

The CPU releases the semaphore by triggering the RELEASE task, as illustrated in the following figure. Triggering the RELEASE task when the CPU does not have access to the semaphore will have no effect. See Semaphore operation on page 595 for more information.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 141: SPI transaction when shortcut between END and ACQUIRE is enabled

![]({{img:images/6a59180a82109e03f8a7e4b628791e584db76925955f842904dab256dbc58d85.jpg}})

If the CPU is not able to reconfigure TXD.PTR and RXD.PTR between granted transactions, the same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening, the END\_ACQUIRE shortcut can be used. With this shortcut enabled, the semaphore will be handed over to the CPU automatically after the granted transaction has completed. This enables the CPU to update the TXPTR and RXPTR between every granted transaction.

The ENDRX event is generated when the RX buffer has been filled.

The RXD.MAXCNT register specifies the maximum number of bytes SPIS can receive in one granted transaction. If SPIS receives more than RXD.MAXCNT number of bytes, an OVERFLOW will be indicated in the STATUS register and the incoming bytes will be discarded.

The TXD.MAXCNT parameter specifies the maximum number of bytes SPIS can transmit in one granted transaction. If SPIS is forced to transmit more than TXD.MAXCNT number of bytes, an OVERREAD will be indicated in the STATUS register and the ORC character will be clocked out.

The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is complete. The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction. ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register indicates how many bytes were written into the RX buffer in the last transaction.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## 8.20.5 Semaphore operation

The semaphore is a mechanism implemented inside the SPIS peripheral that prevents SPIS and CPU from accessing data buffers simultaneously.

By default, the semaphore is assigned to the CPU after the SPIS peripheral is enabled. An ACQUIRED event will not be generated for this initial semaphore handover. If the ACQUIRE task is triggered while the semaphore is assigned to the CPU, an ACQUIRED event will be generated immediately. The following figure illustrates the transitions between states in the semaphore based on the relevant tasks and events.

Figure 142: SPI semaphore FSM

![]({{img:images/417075746f098d0163ec04f289a8af0dcdcc61895a1368df2b229200b3ac511a.jpg}})

Note: The semaphore mechanism does not prevent the CPU from performing read or write access to the RXD.PTR register, TXD.PTR registers, or RAM that these pointers are pointing to. The semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved.

SPIS will try to acquire the semaphore when the STARTED event is detected. If SPIS does not obtain the semaphore, the transaction will be ignored and the semaphore is retained by the CPU. All incoming data on SDI will be discarded and the DEF (default) character will be clocked out on the SDO line throughout the transaction. This is also true if the semaphore is released by the CPU during the transaction. If a race condition occurs where the CPU and SPIS try to acquire the semaphore at the same time, as illustrated in lifeline item 2 in figure SPI transaction when shortcut between END and ACQUIRE is enabled on page 594, the CPU is given the semaphore.

If SPIS acquires the semaphore, the transaction will be granted. The incoming data on SDI will be stored in the RXD buffer and the data in the TXD buffer will be clocked out on SDO.

When a transaction is complete and CSN goes HIGH , SPIS will automatically release the semaphore and generate the END event.

SPIS can be granted multiple transactions in a row as long as the semaphore is available.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

If the CPU tries to acquire the semaphore while it is assigned to SPIS, an immediate handover will not be granted. After the granted transaction is complete, SPIS releases the semaphore to the CPU. If the END\_ACQUIRE shortcut is enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE request will be served following the END event.

## 8.20.6 Pin configuration

The CSN, SCK, SDI, and SDO signals associated with SPIS are mapped to physical pins according to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers, respectively. If the CONNECT field is set to Disconnected , the associated SPIS signal will not be connected to any physical pins.

These registers and their configurations are only used when SPIS is enabled, and retained as long as the device is in System ON mode. See POWER - Power control on page 92 for more information about power modes. When the peripheral is disabled, the pins behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN\_CNF[n] register. Only configure PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO when SPIS is disabled.

Before enabling SPIS, the pins used by SPIS must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 596. This ensures that the pins are driven correctly if SPIS becomes temporarily disabled, or if the device enters System OFF mode. This configuration must be retained in the GPIO for the selected pins to be recognized by an external SPI controller.

The SDO line is set HIGH as long as SPIS is not selected with CSN.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.

| SPI signal | SPI pin | Direction | Output value | Comment |
| -------------- | --------------------------- | ------------- | ---------------- | ------------------------------ |
| CSN | As specified in PSEL.CSN | Input | Not applicable |  |
| SCK | As specified in PSEL.SCK | Input | Not applicable |  |
| SDI | As specified in PSEL.MOSI | Input | Not applicable |  |
| SDO | As specified in PSEL.MISO | Input | Not applicable | Emulates that SPIS is not selected. |

Table 62: GPIO configuration before enabling peripheral

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.20.7 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| ------------------------ | ---------- | ----------------------- | ------------- | ------------- | ------------- | --------- | ----------------------- |
|  |  |  | Map | Att | DMA | access |  |
| SPIS00 : S SPIS00 : NS | GLOBAL | 0x5004A000 0x4004A000 | US | S | SA | No | SPI peripheral SPIS00 |
| SPIS20 : S SPIS20 : NS | GLOBAL | 0x500C6000 0x400C6000 | US | S | SA | No | SPI peripheral SPIS20 |
| SPIS21 : S SPIS21 : NS | GLOBAL | 0x500C7000 0x400C7000 | US | S | SA | No | SPI peripheral SPIS21 |
| SPIS22 : S SPIS22 : NS | GLOBAL | 0x500C8000 0x400C8000 | US | S | SA | No | SPI peripheral SPIS22 |
| SPIS30 : S SPIS30 : NS | GLOBAL | 0x50104000 0x40104000 | US | S | SA | No | SPI peripheral SPIS30 |


| Instance | Domain | Configuration |
| ------------------------ | ---------- | ------------------------------ |
| SPIS00 : S SPIS00 : NS | GLOBAL | Use dedicated pins on GPIO port P2 |
| SPIS20 : S SPIS20 : NS | GLOBAL | Use GPIO port P1, or dedicated pins on P2 |
| SPIS21 : S SPIS21 : NS | GLOBAL | Use GPIO port P1, or dedicated pins on P2 |
| SPIS22 : S SPIS22 : NS | GLOBAL | Use GPIO port P1 |
| SPIS30 : S SPIS30 : NS | GLOBAL | Use GPIO port P0 |


| Register | Offset | TZ | Description |
| ------------------------------ | ---------- | ------ | ------------------------------ |
| TASKS_ACQUIRE | 0x014 |  | Acquire SPI semaphore |
| TASKS_RELEASE | 0x018 |  | Release SPI semaphore, enabling the SPI slave to acquire it |
| TASKS_DMA.RX.ENABLEMATCH[n] | 0x030 |  | Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. |
| TASKS_DMA.RX.DISABLEMATCH[n] | 0x040 |  | Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. |
| SUBSCRIBE_ACQUIRE | 0x094 |  | Subscribe configuration for task ACQUIRE |
| SUBSCRIBE_RELEASE | 0x098 |  | Subscribe configuration for task RELEASE |
| SUBSCRIBE_DMA.RX.ENABLEMATCH[n] | 0x0B0 |  | Subscribe configuration for task ENABLEMATCH[n] |
| SUBSCRIBE_DMA.RX.DISABLEMATCH[n] | 0x0C0 |  | Subscribe configuration for task DISABLEMATCH[n] |
| EVENTS_END | 0x104 |  | Granted transaction completed |
| EVENTS_ACQUIRED | 0x118 |  | Semaphore acquired |
| EVENTS_DMA.RX.END | 0x14C |  | Generated after all MAXCNT bytes have been transferred |
| EVENTS_DMA.RX.READY | 0x150 |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.RX.BUSERROR | 0x154 |  | An error occured during the bus transfer. |
| EVENTS_DMA.RX.MATCH[n] | 0x158 |  | Pattern match is detected on the DMA data bus. |
| EVENTS_DMA.TX.END | 0x168 |  | Generated after all MAXCNT bytes have been transferred |
| Register | Offset | TZ | Description |
| EVENTS_DMA.TX.READY | 0x16C |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.TX.BUSERROR | 0x170 |  | An error occured during the bus transfer. |
| PUBLISH_END | 0x184 |  | Publish configuration for event END |
| PUBLISH_ACQUIRED | 0x198 |  | Publish configuration for event ACQUIRED |
| PUBLISH_DMA.RX.END | 0x1CC |  | Publish configuration for event END |
| PUBLISH_DMA.RX.READY | 0x1D0 |  | Publish configuration for event READY |
| PUBLISH_DMA.RX.BUSERROR | 0x1D4 |  | Publish configuration for event BUSERROR |
| PUBLISH_DMA.RX.MATCH[n] | 0x1D8 |  | Publish configuration for event MATCH[n] |
| PUBLISH_DMA.TX.END | 0x1E8 |  | Publish configuration for event END |
| PUBLISH_DMA.TX.READY | 0x1EC |  | Publish configuration for event READY |
| PUBLISH_DMA.TX.BUSERROR | 0x1F0 |  | Publish configuration for event BUSERROR |
| SHORTS | 0x200 |  | Shortcuts between local events and tasks |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| SEMSTAT | 0x400 |  | Semaphore status register |
| STATUS | 0x440 |  | Status from last transaction |
| ENABLE | 0x500 |  | Enable SPI slave |
| CONFIG | 0x554 |  | Configuration register |
| DEF | 0x55C |  | Default character. Character clocked out in case of an ignored transaction. |
| ORC | 0x5C0 |  | Over-read character |
| PSEL.SCK | 0x600 |  | Pin select for SCK |
| PSEL.MISO | 0x604 |  | Pin select for SDO signal |
| PSEL.MOSI | 0x608 |  | Pin select for SDI signal |
| PSEL.CSN | 0x610 |  | Pin select for CSN signal |
| DMA.RX.PTR | 0x704 |  | RAM buffer start address |
| DMA.RX.MAXCNT | 0x708 |  | Maximum number of bytes in channel buffer |
| DMA.RX.AMOUNT | 0x70C |  | Number of bytes transferred in the last transaction, updated after the END event.<br>Also updated after each MATCH event. |
| DMA.RX.TERMINATEONBUSERROR | 0x71C |  | Terminate the transaction if a BUSERROR event is detected. |
| DMA.RX.BUSERRORADDRESS | 0x720 |  | Address of transaction that generated the last BUSERROR event. |
| DMA.RX.MATCH.CONFIG | 0x724 |  | Configure individual match events |
| DMA.RX.MATCH.CANDIDATE[n] | 0x728 |  | The data to look for - any match will trigger the MATCH[n] event, if enabled. |
| DMA.TX.PTR | 0x73C |  | RAM buffer start address |
| DMA.TX.MAXCNT | 0x740 |  | Maximum number of bytes in channel buffer |
| DMA.TX.AMOUNT | 0x744 |  | Number of bytes transferred in the last transaction, updated after the END event.<br>Also updated after each MATCH event. |
| DMA.TX.TERMINATEONBUSERROR | 0x754 |  | Terminate the transaction if a BUSERROR event is detected. |
| DMA.TX.BUSERRORADDRESS | 0x758 |  | Address of transaction that generated the last BUSERROR event. |

## 8.20.7.1 TASKS\_ACQUIRE

Address offset: 0x014

Acquire SPI semaphore

![]({{img:images/b8ad3d726f7357a3fa33f75f8f76940cb3351a1050bc8516dab340040fad8f02.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | W TASKS_ACQUIRE |  | Acquire SPI semaphore |
|  |  | Trigger | 1 Trigger task |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.20.7.2 TASKS\_RELEASE

Address offset: 0x018

Release SPI semaphore, enabling the SPI slave to acquire it

![]({{img:images/1162c7f46ad374120b697437c4517e8c2e1ecf995da76905f6171827446a7752.jpg}})

## 8.20.7.3 TASKS\_DMA

Peripheral tasks.

## 8.20.7.3.1 TASKS\_DMA.RX

Peripheral tasks.

## 8.20.7.3.1.1 TASKS\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x030 + (n × 0x4)

Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.

![]({{img:images/e222af13f0a891221e29dd47cce3c1b850abf3fbcdc1a7e22f00bdcf41c66652.jpg}})

## 8.20.7.3.1.2 TASKS\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x040 + (n × 0x4)

Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.

![]({{img:images/05d4a6c0ec3ada63242d274784fb870405dc726a026eacf993e027179b74ab23.jpg}})

## 8.20.7.4 SUBSCRIBE\_ACQUIRE

Address offset: 0x094

Subscribe configuration for task ACQUIRE

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/44e3306ee1e1b60bbdd71967883d7ae76b6e5b1903fa368fd097c1b47be64c96.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | R/W Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task ACQUIRE will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.20.7.5 SUBSCRIBE\_RELEASE

Address offset: 0x098

Subscribe configuration for task RELEASE

![]({{img:images/270d795bb368454dd64ab7454714c30c0fae9a3421665103665525413a8854ef.jpg}})

## 8.20.7.6 SUBSCRIBE\_DMA

Subscribe configuration for tasks

## 8.20.7.6.1 SUBSCRIBE\_DMA.RX

Subscribe configuration for tasks

## 8.20.7.6.1.1 SUBSCRIBE\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x0B0 + (n × 0x4)

Subscribe configuration for task ENABLEMATCH[n]

![]({{img:images/348eed46da9ae1ef03e98199effe9c5a84da0b7a107c81ba77f87f73f1fdf0a6.jpg}})

## 8.20.7.6.1.2 SUBSCRIBE\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task DISABLEMATCH[n]

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/b1a09243356a950b6d50fb13e345ab40e41efc0a95baaca4c44e5eb0b5d616dc.jpg}})

## 8.20.7.7 EVENTS\_END

Address offset: 0x104

Granted transaction completed

![]({{img:images/cb98834b0788d037e69a99336b555040abe4f22d9ce9798575082d1467376b16.jpg}})

## 8.20.7.8 EVENTS\_ACQUIRED

Address offset: 0x118

Semaphore acquired

![]({{img:images/cca45fcc0e84381b1be1b18c6dc7fa0baafdc9859d898db15e8efcd93c5c449d.jpg}})

## 8.20.7.9 EVENTS\_DMA

Peripheral events.

## 8.20.7.9.1 EVENTS\_DMA.RX

Peripheral events.

## 8.20.7.9.1.1 EVENTS\_DMA.RX.END

Address offset: 0x14C

Generated after all MAXCNT bytes have been transferred

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/f2a8b31301eaa631e3b8a8e6497f5edaa7391be04012665453ca1609202e8e7b.jpg}})

## 8.20.7.9.1.2 EVENTS\_DMA.RX.READY

Address offset: 0x150

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/501a7d47d348f84bc4934e1f3252add89294f80a895a4c296e7a39978df8f17b.jpg}})

## 8.20.7.9.1.3 EVENTS\_DMA.RX.BUSERROR

Address offset: 0x154

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/92e6119d90aa2f938b3433d5b791a8315a5c17c641520e5fcec01c2468d77207.jpg}})

## 8.20.7.9.1.4 EVENTS\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x158 + (n × 0x4)

Pattern match is detected on the DMA data bus.

![]({{img:images/2a8fdd6afc44fa4f9f6759c855993d7505508b039da103fa0413ddd7dffcd30e.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.20.7.9.2 EVENTS\_DMA.TX

Peripheral events.

## 8.20.7.9.2.1 EVENTS\_DMA.TX.END

Address offset: 0x168

Generated after all MAXCNT bytes have been transferred

![]({{img:images/ab9527f927eaf3bedafcc9f3e5d487cdc434d707abcd45690c4e30af142f6da6.jpg}})

## 8.20.7.9.2.2 EVENTS\_DMA.TX.READY

Address offset: 0x16C

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/eddb455b8e38d5553d72a24ba9558d7616a3467ea815e90e9609cebe003c6dee.jpg}})

## 8.20.7.9.2.3 EVENTS\_DMA.TX.BUSERROR

Address offset: 0x170

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/96bca0576ee061dc04c5e6ceaffd51ef610636a0cc709d04d98f833f69be639a.jpg}})

## 8.20.7.10 PUBLISH\_END

Address offset: 0x184

Publish configuration for event END

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/d67ee193a74a21def0cfd490d716bc75dd8f183cebca7601357a5992587b6314.jpg}})

## 8.20.7.11 PUBLISH\_ACQUIRED

Address offset: 0x198

Publish configuration for event ACQUIRED

![]({{img:images/d259998813703d28699e2fd76aa0911167acf053e0d7b4348f68e91b5cd610f9.jpg}})

## 8.20.7.12 PUBLISH\_DMA

Publish configuration for events

## 8.20.7.12.1 PUBLISH\_DMA.RX

Publish configuration for events

## 8.20.7.12.1.1 PUBLISH\_DMA.RX.END

Address offset: 0x1CC

Publish configuration for event END

![]({{img:images/3e25ddac1740a0281c2396dac3506ee7c546a1451b47120f9b7c9ad816ac4bcc.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event END will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.20.7.12.1.2 PUBLISH\_DMA.RX.READY

Address offset: 0x1D0

Publish configuration for event READY

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/e7b388849a6d60e23585f2e4a8487af186b4a98ef0f1b2e21362bab09d1e6021.jpg}})

## 8.20.7.12.1.3 PUBLISH\_DMA.RX.BUSERROR

Address offset: 0x1D4

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/84271ccf1154f28342abdf0974b50a348b0bb2ad48fc67a8579820a0623baf50.jpg}})

## 8.20.7.12.1.4 PUBLISH\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x1D8 + (n × 0x4)

Publish configuration for event MATCH[n]

![]({{img:images/21d6e192b68642c8cd70ede59e91890b8644a5e74be3bd3d2911fc277d7f0fcf.jpg}})

## 8.20.7.12.2 PUBLISH\_DMA.TX

Publish configuration for events

## 8.20.7.12.2.1 PUBLISH\_DMA.TX.END

Address offset: 0x1E8

Publish configuration for event END

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/cb1d1f26c08c51bc3437fc0b715ec46c347ea72786e8599b24cdf8cb3f472bb9.jpg}})

## 8.20.7.12.2.2 PUBLISH\_DMA.TX.READY

Address offset: 0x1EC

Publish configuration for event READY

![]({{img:images/ed7b69333175ce5dff685b62a572b4c3f63fa1ef5cb2445ecc9c305fcb76c154.jpg}})

## 8.20.7.12.2.3 PUBLISH\_DMA.TX.BUSERROR

Address offset: 0x1F0

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/cfa1a5ac355040312d1d4dc992985d5a1b71b15152c616765687462ff10b4572.jpg}})

## 8.20.7.13 SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/f6491dba432b8aadbbb054a4ced30e4d483eb2b4bf89c9778ee5dcec172aaa6f.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | Bit number | Bit number |
| -------------- | ------------------------------ | -------------- | -------------- |

## 8.20.7.14 INTENSET


Enable interrupt

| Bit number |  |  |  | 31 30 | 29 28 | 23 22 21 20 | 4 3 2 | 1 | 0 |
| -------------- | ------------ | --------------- | ---------- | --------- | --------- | ------------------------------ | --------- | ----- | ----- |
| ID Reset | 0x00000000 |  |  | 0 0 |  | G F E 0 0 0 0 | 0 | A | 0 |
| ID | R/W | Field | Value ID | Value |  | Description |  |  |  |
| A | RW | END | Set<br>Enabled | 1<br>1 |  | Write '1' to<br>Enable<br>Read: Enabled |  |  |  |
| B | RW | ACQUIRED | Set<br>Enabled | 1<br>1 |  | Write '1' to<br>Enable<br>Read: Enabled |  |  |  |
| C | RW | DMARXEND | Set | 1 |  | Write '1' to<br>Enable |  |  |  |
| D | RW | DMARXREADY | Set | 1 |  | Write '1' to enable<br>Enable |  |  |  |
| E | RW | DMARXBUSERROR | Disabled<br>Enabled | 0 1 |  | Write '1' to<br>Read: Disabled Read: Enabled |  |  |  |

J

RW

DMATXEND

Write '1' to enable interrupt for event DMATXEND

![]({{img:images/f150198843580c1049661ede9731390920f57a2bbfde0e8eeac36aa31407881b.jpg}})

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |  |  |  |  |  |  |  |  |  | 0 |
| ------------------ | ------------------ | ------------------------------ | ------- | ----- | ----- | ------------------------------ | ---------- | ----------------------------- | ------- | ----- | ----- | --------- |
| ID |  | L H |  | K | J I | G F E | D C |  |  | B |  | A |
| Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 |  | 0 0 | 0 | 0 0 0 | 0 0 0 | 0 0 0 | 0 0 | 0 | 0 0 | 0 0 0 0 |
| ID | R/W Field | Value ID<br>Set<br>Disabled<br>Enabled | Value<br>1<br>0<br>1 |  |  | Description<br>Enable<br>Read: Disabled<br>Read: Enabled |  |  |  |  |  |  |
| K RW | DMATXREADY | enable event<br>Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write '1'<br>Enable<br>Read: Disabled<br>Read: Enabled | to | interrupt for DMATXREADY |  |  |  |  |
| L RW | DMATXBUSERROR | enable event |  |  |  | Write '1' | to | interrupt for DMATXBUSERROR |  |  |  |  |
|  |  | Set<br>Disabled<br>Enabled | 1<br>0<br>1 | can |  | When this event read from the<br>Enable<br>Read:<br>Read: Enabled | caused<br>Disabled | address which register. | error | the | be |  |
## 8.20.7.15 INTENCLR

Address offset: 0x308

Disable interrupt

![]({{img:images/7461fdcf4a7de28e9a5ec316b7159bd2bbe4a5830270096d0d02ff1a5610b3d5.jpg}})

| Bit number |  |  | 31 | 30 29 28 27 |  | 26 | 25 24 23 | 22 21 20 19 | 4 3 2 | 1 |  | 6 5 | 0 |
| -------------- | ----- | --------------- | ---------- | --------------- | ----- | ------ | ------------ | ------------------------------ | --------- | ------- | ----- | --------------- | ----- |
| ID |  |  |  |  | L | K J | I | G F E D C |  |  |  | B | A |
| Reset |  | 0x00000000 |  | 0 0 | 0 0 | 0 | 0 0 | 0 0 0 0 0 | 0 | 0 0 0 |  | 0 0 | 0 |
| ID | R/W | Field | Value ID | Value |  |  |  | Description |  |  |  |  |  |
| A | RW | END | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  |  | Write '1' to disable interrupt for event<br>Disable<br>Read: Disabled<br>Read: Enabled |  |  |  |  |  |
| B | RW | ACQUIRED | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  |  | Write '1' to disable<br>Disable<br>Read: Disabled<br>Read: Enabled |  |  |  |  |  |
| C | RW | DMARXEND | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  |  | Write '1' to disable<br>Disable<br>Read: Disabled<br>Read: Enabled |  |  |  |  |  |
| D | RW | DMARXREADY | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  |  | Write '1' to disable<br>Disable<br>Read: Disabled<br>Read: Enabled |  |  |  |  |  |
| E | RW | DMARXBUSERROR | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  |  | Write '1' to disable<br>When<br>read from<br>Disable<br>Read: Disabled<br>Read: Enabled | error |  | can | DMARXBUSERROR | be |
| F-I | RW | DMARXMATCH[i] | (i=0..3)<br>Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  |  | Write '1' to disable<br>Disable<br>Read: Disabled<br>Read: Enabled |  |  |  | DMARXMATCH[i] |  |

![]({{img:images/bfe99ba41ee409c471fba67c07900d424876b05a1e16084deaabf809234d5fd1.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ---------------------- | ---------------------- | ---------------------- | ---------------------- | ------------------------------ |
| ID L K | ID L K | ID L K | ID L K | J I H G F E D C B A |
| Reset 0x00000000 0 0 | Reset 0x00000000 0 0 | Reset 0x00000000 0 0 | Reset 0x00000000 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value | Description |
| J RW | DMATXEND |  |  | Write '1' to disable interrupt for event DMATXEND |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| K RW | DMATXREADY |  |  | Write '1' to disable interrupt for event DMATXREADY |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |
| L RW | DMATXBUSERROR |  |  | Write '1' to disable interrupt for event DMATXBUSERROR<br>When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register. |
|  |  | Clear | 1 | Disable |
|  |  | Disabled | 0 | Read: Disabled |
|  |  | Enabled | 1 | Read: Enabled |

## 8.20.7.16 SEMSTAT

Address offset: 0x400

Semaphore status register

![]({{img:images/8b5dd36906a2d01085cbcb25fbd1f659397ae74e7229bc7785955840896b75fc.jpg}})

## 8.20.7.17 STATUS

Address offset: 0x440

Status from last transaction

Individual bits are cleared by writing a '1' to the bits that shall be cleared.

![]({{img:images/696f44a01437216e72ff7d550a438ed6393564839f992995b936e550a2b9f74f.jpg}})

| Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ | ------------------------------ |
| ID B A | ID B A | ID B A |
| Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Value ID | Value Description |
| A RW | OVERREAD TX buffer over-read detected, and prevented | OVERREAD TX buffer over-read detected, and prevented |
|  | NotPresent | 0 Read: error not present |
|  | Present | 1 Read: error present |
|  | Clear | 1 Write: clear error on writing '1' |
| B | RW OVERFLOW RX buffer overflow detected, and prevented | RW OVERFLOW RX buffer overflow detected, and prevented |
|  | NotPresent | 0 Read: error not present |
|  | Present | 1 Read: error present |
|  | Clear | 1 Write: clear error on writing '1' |

## 8.20.7.18 ENABLE

Address offset: 0x500

Enable SPI slave

![]({{img:images/ebf95ff279332ccebdb24d4211b8c10b9a42aa2b1afc3c7ea3e2efa4548ca5f7.jpg}})

## 8.20.7.19 CONFIG

Address offset: 0x554

Configuration register

![]({{img:images/31569c8c26c6563576133ab08c52ef5517f318013b9245833e0c7e379b869444.jpg}})

## 8.20.7.20 DEF

Address offset: 0x55C

Default character. Character clocked out in case of an ignored transaction.

![]({{img:images/5561073a07ecab394d4a3e39ce1f4d5896ffbe83dae46ff70cbbdc4017d350ae.jpg}})

## 8.20.7.21 ORC

Address offset: 0x5C0

Over-read character

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/db115d38a4c7400b835d29b005639eabd5c633a874f3e795d27f810aa3bccd8d.jpg}})

## 8.20.7.22 PSEL.SCK

Address offset: 0x600

Pin select for SCK

![]({{img:images/0877ecd1d5bcc770025104bab50ab08bce34d69dff0133d0405ec6aad01c4289.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.20.7.23 PSEL.MISO

Address offset: 0x604

Pin select for SDO signal

![]({{img:images/1b19236d17509639bca1452ccc30d7a6ad19215cc1226918cda53eed9ef61dcd.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.20.7.24 PSEL.MOSI

Address offset: 0x608

Pin select for SDI signal

![]({{img:images/379f35af638e70494b540b4fbeb4bf3077f860bbe38931e4c298d82c14fecde4.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.20.7.25 PSEL.CSN

Address offset: 0x610

Pin select for CSN signal

![]({{img:images/389070cfd7a1b621bd2a71d04a72948d2cf33f7e267ec67547a94d2b16449793.jpg}})

## 8.20.7.26 DMA.RX.PTR

Address offset: 0x704

RAM buffer start address

![]({{img:images/d8c67cb15f779fcd5a5509154d3fccf569559221d5cb883b8fbcacd2cee48d31.jpg}})

RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address.

Note: See the memory chapter for details about which memories are available for EasyDMA.

## 8.20.7.27 DMA.RX.MAXCNT

Address offset: 0x708

Maximum number of bytes in channel buffer

![]({{img:images/3c313a7ac172bb5797e0a68f308258c5c4e450c5fe724865678191d69dd15cfc.jpg}})

## 8.20.7.28 DMA.RX.AMOUNT

Address offset: 0x70C

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/b24e9722aa0e029ac7ea29c65f9e7bd60627f8ebebcb521bdfe1be1d1f207199.jpg}})

## 8.20.7.29 DMA.RX.TERMINATEONBUSERROR

Address offset: 0x71C

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/66f40d1a27fe08b7750e45fbe753d2ac390f2924acebc0e67455ea7c645bce3e.jpg}})

## 8.20.7.30 DMA.RX.BUSERRORADDRESS

Address offset: 0x720

Address of transaction that generated the last BUSERROR event.

![]({{img:images/2c172066d5b554c35e009f4198768052e0b1ab4eff841d4fb5bc1fe5343c624a.jpg}})

## 8.20.7.31 DMA.RX.MATCH

Registers to control the behavior of the pattern matcher engine

## 8.20.7.31.1 DMA.RX.MATCH.CONFIG

Address offset: 0x724

Configure individual match events

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/4ee35822fe55970ce8439d28818b7e04fc807c716ece0b831a095a157ef532aa.jpg}})

## 8.20.7.31.2 DMA.RX.MATCH.CANDIDATE[n] (n=0..3)

Address offset: 0x728 + (n × 0x4)

The data to look for - any match will trigger the MATCH[n] event, if enabled.

Note: This register can be updated while a transfer is in progress, but the new value will not take effect until a match has been found or the transfer is done. That makes it possible to write a new set of match words which will be searched for immediately after the event triggers.

![]({{img:images/c6e1825abdba4b9c117ece3fe15b569dbe282207202deafac204312cc4646481.jpg}})

## 8.20.7.32 DMA.TX.PTR

Address offset: 0x73C

RAM buffer start address

![]({{img:images/0bc1283105d783681662da6ae2753895af67a5530feb181fe6e00f6619536fdf.jpg}})

## 8.20.7.33 DMA.TX.MAXCNT

Address offset: 0x740

Maximum number of bytes in channel buffer

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/2d01963728d4a66343107266dbef6f7763b427ee5c6357f9bd2f229038f865bc.jpg}})

## 8.20.7.34 DMA.TX.AMOUNT

Address offset: 0x744

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/a02284aa98f006f1fb90fe4183eb81a0d6f28aad029630b5cb19430d823498a6.jpg}})

## 8.20.7.35 DMA.TX.TERMINATEONBUSERROR

Address offset: 0x754

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/414bf2fd89a2751ec11a7eacde98446fdf5ac7dcc7eac30941dac33e57cee890.jpg}})

## 8.20.7.36 DMA.TX.BUSERRORADDRESS

Address offset: 0x758

Address of transaction that generated the last BUSERROR event.

![]({{img:images/badc50993cf0787fa9f2fd8f2a4bf90d8fb9f7347bdafba000b97cfd0073de79.jpg}})

## 8.21 TEMP - Temperature sensor

The temperature sensor (TEMP) measures die temperature over the temperature range of the device. Linearity compensation can be implemented if required by the application.

The main features of TEMP are:

- Temperature range is greater than or equal to operating temperature of the device

![]({{img:images/33fe139d94bd9212e000108767e59c6833bd9c98cf4c9184a339967f71b45081.jpg}})

- Resolution is 0.25 degrees
- TEMP analog electronics power down after temperature measurement is completed

TEMP is started by triggering the START task.

When the temperature measurement is completed, a DATARDY event will be generated and the result of the measurement can be read from the TEMP register.

To achieve the measurement accuracy stated in the electrical specification, the crystal oscillator must be selected as the HFCLK source, see CLOCK - Clock control on page 71 for more information.

When the temperature measurement is completed, TEMP analog electronics power down to save power.

TEMP only supports one-shot operation, meaning that every TEMP measurement has to be explicitly started using the START task.

## 8.21.1 Registers


| Instance | Domain | Base address | TrustZone |  |  | Split | Description |
| -------------------- | ---------- | ----------------------- | ------------- | ----- | ----- | --------- | ------------------------- |
|  |  |  | Map | Att | DMA | access |  |
| TEMP : S TEMP : NS | GLOBAL | 0x500D7000 0x400D7000 | US | S | NA | No | Temperature sensor TEMP |


| Register | Offset | TZ | Description |
| ----------------- | ---------- | ------ | ------------------------------ |
| TASKS_START | 0x000 |  | Start temperature measurement |
| TASKS_STOP | 0x004 |  | Stop temperature measurement |
| SUBSCRIBE_START | 0x080 |  | Subscribe configuration for task START |
| SUBSCRIBE_STOP | 0x084 |  | Subscribe configuration for task STOP |
| EVENTS_DATARDY | 0x100 |  | Temperature measurement complete, data ready |
| PUBLISH_DATARDY | 0x180 |  | Publish configuration for event DATARDY |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| TEMP | 0x508 |  | Temperature in °C (0.25° steps) |
| A0 | 0x520 |  | Slope of 1st piece wise linear function |
| A1 | 0x524 |  | Slope of 2nd piece wise linear function |
| A2 | 0x528 |  | Slope of 3rd piece wise linear function |
| A3 | 0x52C |  | Slope of 4th piece wise linear function |
| A4 | 0x530 |  | Slope of 5th piece wise linear function |
| A5 | 0x534 |  | Slope of 6th piece wise linear function |
| A6 | 0x538 |  | Slope of 7th piece wise linear function |
| B0 | 0x540 |  | y-intercept of 1st piece wise linear function |
| B1 | 0x544 |  | y-intercept of 2nd piece wise linear function |
| B2 | 0x548 |  | y-intercept of 3rd piece wise linear function |
| B3 | 0x54C |  | y-intercept of 4th piece wise linear function |
| B4 | 0x550 |  | y-intercept of 5th piece wise linear function |
| B5 | 0x554 |  | y-intercept of 6th piece wise linear function |
| B6 | 0x558 |  | y-intercept of 7th piece wise linear function |
| T0 | 0x560 |  | End point of 1st piece wise linear function |
| T1 | 0x564 |  | End point of 2nd piece wise linear function |
| T2 | 0x568 |  | End point of 3rd piece wise linear function |
| Register | Offset | TZ | Description |
| T3 | 0x56C |  | End point of 4th piece wise linear function |
| T4 | 0x570 |  | End point of 5th piece wise linear function |
| T5 | 0x574 |  | End point of 6th piece wise linear function |

## 8.21.1.1 TASKS\_START

Address offset: 0x000

Start temperature measurement

![]({{img:images/b95eb4bdbf5f18ac70154e1f945d5bdd9ed7145c6e42ea98578f21024df7c96c.jpg}})

## 8.21.1.2 TASKS\_STOP

Address offset: 0x004

Stop temperature measurement

![]({{img:images/f314921e8b397eef0e3d4cc6c28156256177ee45f10ac43015cb50c4ded08c13.jpg}})

## 8.21.1.3 SUBSCRIBE\_START

Address offset: 0x080

Subscribe configuration for task START

![]({{img:images/e1a9e30e0af4c9028e2c7afa3555be8cb394c5036954bc9ed34f8353119967ac.jpg}})

## 8.21.1.4 SUBSCRIBE\_STOP

Address offset: 0x084

Subscribe configuration for task STOP

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/1e41696c22dda29fe6d5854511f9d7162f1cc7d1931dcd1e7d0232d760bfa81e.jpg}})

## 8.21.1.5 EVENTS\_DATARDY

Address offset: 0x100

Temperature measurement complete, data ready

![]({{img:images/dc7133bb07f7cd3cc5ad80a12405b9eed6f2b5c8850a0beca06ef6f5e3152a2a.jpg}})

## 8.21.1.6 PUBLISH\_DATARDY

Address offset: 0x180

Publish configuration for event DATARDY

![]({{img:images/74d17cae295828f529fdaf13d2fb4fc70d2c546271cc8022b2e78a671aafe711.jpg}})

## 8.21.1.7 INTENSET

Address offset: 0x304

Enable interrupt

![]({{img:images/9b244042aa39ca7e4876d5e1e288427662eac2f5af11a5b793d7c208e0eb7f4e.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.21.1.8 INTENCLR

Address offset: 0x308

Disable interrupt

![]({{img:images/cdb343008f89810b6cfd819b4d273960d1897fd88db5229e7acc015cb9af9558.jpg}})

## 8.21.1.9 TEMP

Address offset: 0x508

Temperature in °C (0.25° steps)

![]({{img:images/53a8d851a725e2534f9fcde2ca46d751611f840a3a6d898abe8dd611c5bcd4b9.jpg}})

## 8.21.1.10 A0

Address offset: 0x520

Slope of 1st piece wise linear function

![]({{img:images/32e44e5696e2e58aac1efa08aeceb3ec1055e9866a95a42b3b56aa47e1f25479.jpg}})

A

RW

A0

## 8.21.1.11 A1

Address offset: 0x524

Slope of 2nd piece wise linear function

![]({{img:images/45bc2da983138820ac5803aa48e26c4a075586faf088150e2d661c3cb02021d4.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Decision point: DATARDY

Slope of 1st piece wise linear function

## 8.21.1.12 A2

Address offset: 0x528

Slope of 3rd piece wise linear function

![]({{img:images/226e906c9e6e4e1be52c586c2aa7f7f026a19e1846e32dc8b69e1af17e51a985.jpg}})

A

RW

A2

## 8.21.1.13 A3

Address offset: 0x52C

Slope of 4th piece wise linear function

![]({{img:images/90ac55683adc5573f5ded9956748d9ef726127b25c512cd8a4e0cb5aa8b6bd7d.jpg}})

A

RW

A3

## 8.21.1.14 A4

Address offset: 0x530

Slope of 5th piece wise linear function

![]({{img:images/dcf9e7a34ceb3e1c8c24a6979bfddbcf880430bd0afc8b44d4e64a3f008fca80.jpg}})

A

RW

A4

## 8.21.1.15 A5

Address offset: 0x534

Slope of 6th piece wise linear function

![]({{img:images/bd36f4673789cc61c7662e622f264ae63fa99c0a0878d7544448e90caa63221b.jpg}})

A

RW

A5

## 8.21.1.16 A6

Address offset: 0x538

Slope of 7th piece wise linear function

Slope of 6th piece wise linear function

Slope of 3rd piece wise linear function

Slope of 4th piece wise linear function

Slope of 5th piece wise linear function

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/1f3b8c858a8f0e16f7f969d19c348a1ae46749fbb70ffcff0031fa62c6bbdbbe.jpg}})

A

RW

A6

## 8.21.1.17 B0

Address offset: 0x540

y-intercept of 1st piece wise linear function

![]({{img:images/9be85955829ebb919084707fb4bb2be9c50b1e3ebecba94c82025b83129daee7.jpg}})

A

RW

B0

## 8.21.1.18 B1

Address offset: 0x544

y-intercept of 2nd piece wise linear function

![]({{img:images/a56374f58e91ec8e44509205acd1a6fd343ebbeb8297cd827af12cfc6715927f.jpg}})

## 8.21.1.19 B2

Address offset: 0x548

y-intercept of 3rd piece wise linear function

![]({{img:images/c51c1ec5d9869191805fb62191159d74ab5303d6b396acd58e605b7770c895ab.jpg}})

A

RW

B2

## 8.21.1.20 B3

Address offset: 0x54C

y-intercept of 4th piece wise linear function

Slope of 7th piece wise linear function

![]({{img:images/17933d694d4006129522fc63d7cbe5add9ae069df34b9326e64dc501a4510144.jpg}})

![]({{img:images/4d8ce89d87e8b824def5d1b06432469feed7bc07aca299ff2b603ca898d3290d.jpg}})

y-intercept of 1st piece wise linear function

y-intercept of 3rd piece wise linear function

## 8.21.1.21 B4

Address offset: 0x550

y-intercept of 5th piece wise linear function

![]({{img:images/a713a697887012ab27afcd765f08390f78dec2c5c660b8cba877feb11fa48940.jpg}})

A

RW

B4

## 8.21.1.22 B5

Address offset: 0x554

y-intercept of 6th piece wise linear function

![]({{img:images/50a3c97a90fc4a0fe13ee973be08e57beadcb3e0c8df922719ad6e5d3470588d.jpg}})

A

RW

B5

## 8.21.1.23 B6

Address offset: 0x558

y-intercept of 7th piece wise linear function

![]({{img:images/1317297d49c64276748d0dbadfc556912aa5d978826ccc0aca06a4eff7557d7e.jpg}})

A

RW

B6

## 8.21.1.24 T0

Address offset: 0x560

End point of 1st piece wise linear function

![]({{img:images/838df11c15661128e9aa876becefb4dba7706de26a2429c05db8f2fb3ddc184e.jpg}})

A

RW

T0

## 8.21.1.25 T1

Address offset: 0x564

End point of 2nd piece wise linear function

End point of 1st piece wise linear function

y-intercept of 5th piece wise linear function

y-intercept of 6th piece wise linear function

y-intercept of 7th piece wise linear function

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/2d11bf9f45ab05852794f37ea6035575c94131f1df4a2b80600dd568c29ebefc.jpg}})

A

RW

T1

## 8.21.1.26 T2

Address offset: 0x568

End point of 3rd piece wise linear function

![]({{img:images/b08a9a3c32ff72b21c2a90e6e5e2dc6ff0bac4209f901d4ca458d84d4b5a8fba.jpg}})

A

RW

T2

## 8.21.1.27 T3

Address offset: 0x56C

End point of 4th piece wise linear function

![]({{img:images/c12939f431e51424862b7b3b640efde328004de060685ba7c9b1598c8540dfaa.jpg}})

## 8.21.1.28 T4

Address offset: 0x570

End point of 5th piece wise linear function

![]({{img:images/455cf984d15a4ecfd9b8a14d67f01918f371e023413cd9fb407555131a018256.jpg}})

A

RW

T4

## 8.21.1.29 T5

Address offset: 0x574

End point of 6th piece wise linear function

End point of 2nd piece wise linear function

![]({{img:images/24685d2eb1a443d76b966812a176d2b6aae94ef5bc162ee6cc41b6c872123d9e.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

End point of 3rd piece wise linear function

End point of 5th piece wise linear function

## 8.22 TIMER - Timer/counter

The TIMER peripheral is a general purpose timer allowing time intervals to be defined by user input.

The main features of TIMER are:

- Two modes of operation: Timer mode and Counter mode
- Multiple capture/compare registers
- Compare event for every capture/compare registers
- 4-bit (1/2X) prescaler
- Configurable number of bits used by the TIMER: 8, 16, 24 or 32 bits
- TIMER runs on the high-frequency clock source (HFCLK)

Figure 143: Block schematic for timer/counter

![]({{img:images/49485373f6dd8ac27799db2e9b85660f8fbfa0367104ed2536263cb97e5729f6.jpg}})

TIMER runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler that can divide the timer input clock (PCLK) from the HFCLK controller. The TIMER base frequency is always given as PCLK divided by the prescaler value.

The PPI system allows a TIMER event to trigger a task on another system peripheral on the device. The PPI system also enables the TIMER task/event feature to generate periodic output and PWM signals to any GPIO. The number of GPIO inputs or outputs used at the same time is limited by the number of GPIOTE channels.

TIMER can operate in two modes: Timer mode and Counter mode. In both modes, TIMER is started by triggering the START task, and stopped by triggering the STOP task. After TIMER stops, it can resume timing/counting by triggering the START task again. When timing/counting resumes, TIMER continues from the value it was on prior to stopping.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

In Timer mode, TIMER's internal Counter register is incremented by one for every tick of the timer frequency fTIMER, as illustrated in Block schematic for timer/counter on page 624. The timer frequency is derived from PCLK as shown in the following example, using the values specified in the PRESCALER register.

fTIMER = PCLK / (2 PRESCALER )


For timers using PCLK16M as PCLK, when fTIMER ≤ 1 MHz, TIMER uses PCLK1M instead of PCLK for reduced power consumption. Clock source selection between PCLK and PCLK1M is automatic according to the TIMER base frequency set by the prescaler.

In Counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task is triggered, meaning the timer frequency and the prescaler are not utilized in Counter mode. Similarly, the COUNT task has no effect in Timer mode.

TIMER's maximum value is configured by changing the bit-width of the timer in register BITMODE on page 632.

PRESCALER on page 632 and BITMODE on page 632 must only be updated when TIMER is stopped. If these registers are updated while TIMER is started, unpredictable behavior may occur.

When TIMER is incremented beyond its maximum value, the Counter register will overflow and TIMER will automatically start over from zero.

The Counter register can be cleared by triggering the CLEAR task. This will explicitly set the internal value to zero.

TIMER implements multiple capture/compare registers.

Independent of prescaler settings, the accuracy of TIMER is equivalent to one tick of the timer frequency fTIMER as illustrated in Block schematic for timer/counter on page 624.

## 8.22.1 Capture

TIMER implements one capture task for every available capture/compare register.

Every time the CAPTURE[n] task is triggered, the counter value is copied to the CC[n] register.

## 8.22.2 Compare

TIMER implements one COMPARE event for every available capture/compare register.

When the counter value becomes equal to the value specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is generated.

BITMODE on page 632 specifies how many Counter and capture/compare register bits are used when the comparison is performed. Other bits are ignored.

The COMPARE event can be configured to operate in one-shot mode by configuring the corresponding ONESHOTEN[n] register. After writing CC[n], a COMPARE[n] event is generated the first time the Counter matches CC[n].

## 8.22.3 Task delays

After TIMER is started, the CLEAR, COUNT, and STOP tasks are guaranteed to take effect within one clock cycle of the PCLK.

## 8.22.4 Task priority

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

If the START task and the STOP task are triggered at the same time, meaning within the same period of PCLK, the STOP task is prioritized.

If one or more of the CAPTURE tasks and the CLEAR task are triggered at the same time, that is, within the same period of PCLK, the  CAPTURE tasks are prioritized. This means that the CC registers will capture the counter value before the CLEAR tasks are triggered.

## 8.22.5 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| -------------------------- | ---------- | ----------------------- | ------------- | ------------- | ------------- | --------- | --------------- |
|  |  |  | Map | Att | DMA | access |  |
| TIMER00 : S TIMER00 : NS | GLOBAL | 0x50055000 0x40055000 | US | S | NA | No | Timer TIMER00 |
| TIMER10 : S TIMER10 : NS | GLOBAL | 0x50085000 0x40085000 | US | S | NA | No | Timer TIMER10 |
| TIMER20 : S TIMER20 : NS | GLOBAL | 0x500CA000 0x400CA000 | US | S | NA | No | Timer TIMER20 |
| TIMER21 : S TIMER21 : NS | GLOBAL | 0x500CB000 0x400CB000 | US | S | NA | No | Timer TIMER21 |
| TIMER22 : S TIMER22 : NS | GLOBAL | 0x500CC000 0x400CC000 | US | S | NA | No | Timer TIMER22 |
| TIMER23 : S TIMER23 : NS | GLOBAL | 0x500CD000 0x400CD000 | US | S | NA | No | Timer TIMER23 |
| TIMER24 : S TIMER24 : NS | GLOBAL | 0x500CE000 0x400CE000 | US | S | NA | No | Timer TIMER24 |


| Instance | Domain | Configuration |
| -------------------------- | ---------- | ------------------------------ |
| TIMER00 : S TIMER00 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 128 MHz The system is able to configure the TIMER peripheral input clock frequency (PCLK) before it reaches TIMER, and calculations of PRESCALER value must take the actual PCLK frequency into account |
| TIMER10 : S TIMER10 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 32 MHz 8 capture compare channels implemented |
| TIMER20 : S TIMER20 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented |
| TIMER21 : S TIMER21 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented |
| TIMER22 : S TIMER22 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented |
| TIMER23 : S TIMER23 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented |
| TIMER24 : S TIMER24 : NS | GLOBAL | Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})


| Register | Offset | TZ | Description |
| ---------------------- | ---------- | ------ | ------------------------------ |
| TASKS_START | 0x000 |  | Start Timer |
| TASKS_STOP | 0x004 |  | Stop Timer |
| TASKS_COUNT | 0x008 |  | Increment Timer (Counter mode only) |
| TASKS_CLEAR | 0x00C |  | Clear time |
| TASKS_CAPTURE[n] | 0x040 |  | Capture Timer value to CC[n] register |
| SUBSCRIBE_START | 0x080 |  | Subscribe configuration for task START |
| SUBSCRIBE_STOP | 0x084 |  | Subscribe configuration for task STOP |
| SUBSCRIBE_COUNT | 0x088 |  | Subscribe configuration for task COUNT |
| SUBSCRIBE_CLEAR | 0x08C |  | Subscribe configuration for task CLEAR |
| SUBSCRIBE_CAPTURE[n] | 0x0C0 |  | Subscribe configuration for task CAPTURE[n] |
| EVENTS_COMPARE[n] | 0x140 |  | Compare event on CC[n] match |
| PUBLISH_COMPARE[n] | 0x1C0 |  | Publish configuration for event COMPARE[n] |
| SHORTS | 0x200 |  | Shortcuts between local events and tasks |
| INTEN | 0x300 |  | Enable or disable interrupt |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| MODE | 0x504 |  | Timer mode selection |
| BITMODE | 0x508 |  | Configure the number of bits used by the TIMER |
| PRESCALER | 0x510 |  | Timer prescaler register |
| CC[n] | 0x540 |  | Capture/Compare register n |
| ONESHOTEN[n] | 0x580 |  | Enable one-shot operation for Capture/Compare channel |

## 8.22.5.1 TASKS\_START

Address offset: 0x000

## Start Timer

![]({{img:images/f53296a4a4db34bb3151ab6a58d3cb262732831090c17866a1597e51a9e7d600.jpg}})

## 8.22.5.2 TASKS\_STOP

Address offset: 0x004

## Stop Timer

![]({{img:images/299a442b2895f82523301ec6417267b49542fc1e98dbcc2ce17b7a5f02989c6c.jpg}})

## 8.22.5.3 TASKS\_COUNT

Address offset: 0x008

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## Increment Timer (Counter mode only)

![]({{img:images/2dda981d3f73178d3d0bb4f3cdefda3bc250f729167823e242db8454d5565fc3.jpg}})

## 8.22.5.4 TASKS\_CLEAR

Address offset: 0x00C

Clear time

![]({{img:images/a38c0751c58d5cb4c14a27fbb93d1c7154245acadb28b19289e40085ad336539.jpg}})

## 8.22.5.5 TASKS\_CAPTURE[n] (n=0..7)

Address offset: 0x040 + (n × 0x4)

Capture Timer value to CC[n] register

![]({{img:images/30d2885943c6ebd0a026f5f209d89eb87491a044ba30d4caa38417177a466847.jpg}})

## 8.22.5.6 SUBSCRIBE\_START

Address offset: 0x080

Subscribe configuration for task START

![]({{img:images/440e9d83b525682b0d86b3259e47c2fe49e8f5ab5207f1f8dcb023a64f077a0e.jpg}})

## 8.22.5.7 SUBSCRIBE\_STOP

Address offset: 0x084

Subscribe configuration for task STOP

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/1a14bab97edd1044cb0722f13c9a656b859b50a422c6d3750f96ca51d4a64326.jpg}})

## 8.22.5.8 SUBSCRIBE\_COUNT

Address offset: 0x088

Subscribe configuration for task COUNT

![]({{img:images/d613490a870341a929f09c70ae51a4401ae213f876c928511cdcf1c31642f232.jpg}})

## 8.22.5.9 SUBSCRIBE\_CLEAR

Address offset: 0x08C

Subscribe configuration for task CLEAR

![]({{img:images/7fe8bbfca19e0dcbc9177eabea1c9a69a94f19eaedb60d10bbfcc869d4ec1be0.jpg}})

## 8.22.5.10 SUBSCRIBE\_CAPTURE[n] (n=0..7)

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task CAPTURE[n]

![]({{img:images/95b414b4101cfa5a7ddc4731e797cf7a5052f04a3140ad438ee8c077118f17f4.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task CAPTURE[n] will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

## 8.22.5.11 EVENTS\_COMPARE[n] (n=0..7)

Address offset: 0x140 + (n × 0x4)

Compare event on CC[n] match

![]({{img:images/dcdf88eff613eae4c4e165b5443864b4e8ea290445b0742b9ec665c50d259c77.jpg}})

## 8.22.5.12 PUBLISH\_COMPARE[n] (n=0..7)

Address offset: 0x1C0 + (n × 0x4)

Publish configuration for event COMPARE[n]

![]({{img:images/e3a35ca1b626b0b3d334e341ced7fc5ecb50e1996726816980d75e491c105e07.jpg}})

## 8.22.5.13 SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

![]({{img:images/33973a60d7a1e5151fb88347080f2f7fd96c2c191e1e07e1f36766e487e44ab4.jpg}})

## 8.22.5.14 INTEN

Address offset: 0x300

Enable or disable interrupt

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/c7786778469a44f61a083de515d64468c5e601b7637f0c66d4dee9867873363f.jpg}})

## 8.22.5.15 INTENSET

Address offset: 0x304

Enable interrupt

![]({{img:images/caedbf613e663e35e62d4dcacce771b14af3c7e400a260e51fc33a795aab79f1.jpg}})

## 8.22.5.16 INTENCLR

Address offset: 0x308

Disable interrupt

![]({{img:images/f66221b1a44666f49b3a3ed624a9794bd36a34470879879bdd6599b37d41962f.jpg}})

## 8.22.5.17 MODE

Address offset: 0x504

Timer mode selection

![]({{img:images/71e06d888679b0c4ff80cf0b90f155cb309414e45136401e9486da7a9263cd7a.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.22.5.18 BITMODE

Address offset: 0x508

Configure the number of bits used by the TIMER

![]({{img:images/1bc57039c9728e1c13c3b7cebc8b83e0c3663e90bdc9b4ca6549edbd966ed695.jpg}})

## 8.22.5.19 PRESCALER

Address offset: 0x510

Timer prescaler register

![]({{img:images/2a7791de07182b276da32d882b5e5ade21e123a8eb3074bb44408b5ce891cf75.jpg}})

## 8.22.5.20 CC[n] (n=0..7)

Address offset: 0x540 + (n × 0x4)

Capture/Compare register n

![]({{img:images/978ba1f1b6c9e65e2ef448b80193f4627032684a4e2fad77e0e74e09ae772962.jpg}})

Only the number of bits indicated by BITMODE will be used by the TIMER.

## 8.22.5.21 ONESHOTEN[n] (n=0..7)

Address offset: 0x580 + (n × 0x4)

Enable one-shot operation for Capture/Compare channel n

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/233afd9b4b7efa7bfda4ef4a90cdfa55a9b5eda24ef66ec1461d0ddf9dc89155.jpg}})

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------------------------------ |
| ID |  | A |
| Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW ONESHOTEN |  | Enable one-shot operation<br>Configures the corresponding compare-channel for one-shot operation |
|  | Disable | 0 Disable one-shot operation<br>Compare event is generated every time the Counter matches CC[n] |
|  | Enable | 1 Enable one-shot operation<br>Compare event is generated the first time the Counter matches CC[n] after<br>CC[n] has been written |

## 8.23 TWIM - I 2 C compatible two-wire interface controller with EasyDMA

The TWI controller peripheral (TWIM) with EasyDMA provides a half duplex, two-wire synchronous serial communication interface which supports multiple targets in the same bus.

## The main features of TWIM are the following:

- I 2 C compatible for 100 kbps and 400 kbps
- 1000 kbps bit rate support for selected pull-up resistor/bus capacitance combinations
- Supported baud rates:
- 100 kbps
- 400 kbps
- 1000 kbps
- EasyDMA direct transfer to and from RAM
- Individual selection of I/O pins
- Support for clock stretching
- Transmissions can be suspended and resumed

The two-wire interface can communicate with a bidirectional wired-AND bus with two lines (SCL, SDA). The interface enables interconnecting up to 127 individually addressable devices. TWIM is not compatible with CBUS.

Selecting GPIO pins individually ensures flexibility in device pinout and efficient use of board space and signal routing.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 144: TWIM with EasyDMA

![]({{img:images/1f37f0481ba985fe01c3dc5f3c87547a7f1bb0630e06554fd120894d6f1cc465.jpg}})

A typical TWIM setup consists of one controller and one or more targets, as illustrated in the following figure. TWIM can only operate as a single controller on the TWI bus. A bus configuration with multiple controllers is not supported.

Figure 145: A typical TWIM setup with one controller and three targets

**Figure 144: TWIM with EasyDMA**

![]({{img:images/a7eb244eb683d313676708755b661e09e4659022f58aac5f22532a090f01402a.jpg}})

TWIM supports clock stretching performed by the targets.

## 8.23.1 TWIM operation

TWIM is started by triggering the DMA.TX.START or DMA.RX.START tasks, and stopped by triggering the STOP task. After a STOP task, TWIM generates a STOPPED event when it has stopped.

After TWIM starts, the DMA.TX.START and DMA.RX.START tasks must not be triggered again until TWIM has issued a LASTRX, LASTTX, or STOPPED event.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

TWIM can be suspended using the SUSPEND task, which is useful when using TWIM in a low priority interrupt context. When TWIM enters the SUSPEND state, it will automatically issue a SUSPENDED event while performing a continuous clock stretching. This continues until a RESUME task is received. TWIM cannot be stopped while it is suspended. The STOP task must be issued after TWIM resumes operation.

Note: Any ongoing byte transfer is allowed to complete before suspend is enforced. A SUSPEND task has no effect unless TWIM is actively involved in a transfer.

If a NACK is clocked in from the target, TWIM generates an ERROR event.

## 8.23.2 Shared resources

The TWIM peripheral shares registers and other resources with peripherals that have the same ID as TWIM. Therefore, all peripherals that have the same ID as TWIM must be disabled before TWIM can be configured and used.

Disabling shared peripherals will not reset any of the registers that are shared with TWIM. Configure all relevant TWIM registers to ensure they operate correctly.

See the Instantiation table in Instantiation on page 214 for details on peripherals and their IDs.

## 8.23.3 EasyDMA

EasyDMA is implemented by TWIM in order to access RAM without the CPU.

TWIM implements the following EasyDMA channels.

Table 63: TWIM EasyDMA channels

| Channel | Type | Register Cluster |
| ----------- | -------- | -------------------- |
| TXD | READER | TXD |
| RXD | WRITER | RXD |

The RXD.PTR, TXD.PTR, RXD.MAXCNT, and TXD.MAXCNT registers are double-buffered. They are ready for the next transmission immediately after receiving the EVENTS\_DMA.RX.READY or EVENTS\_DMA.TX.READY event.

The STOPPED event indicates that EasyDMA is finished accessing the buffer in RAM.

See EasyDMA on page 28 for more detailed information.

## 8.23.4 TWIM write sequence

A TWIM write sequence is started by triggering the DMA.TX.START task. After the DMA.TX.START task has been triggered, TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE = 0 , READ = 1 ).

The target device address the controller wants to write to must match the clocked address. The READ/ WRITE bit is followed by an ACK/NACK bit (ACK = 0 or NACK = 1 ) generated by the target.

After receiving the ACK bit, TWIM clocks out the data bytes found in the transmit buffer located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from TWIM is followed by an ACK/ NACK bit clocked in from the target.

A typical TWIM write sequence including clock stretching performed by TWIM following a SUSPEND task is shown in the following figure.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 146: TWIM writing data to a target

![]({{img:images/33521a8f01e0a5bd5d94c58d18fd11631cc29890a2889886ccb5d3365043d9e4.jpg}})

A SUSPENDED event indicates that the SUSPEND task has taken effect.

TWIM will generate a LASTTX event when it starts to transmit the last byte.

TWIM is stopped by triggering the STOP task. To stop TWIM as fast as possible, trigger the task during the transmission of the last byte. The shortcut between LASTTX and STOP can also be used to accomplish this.

TWIM does not stop on its own when the entire RAM buffer has been sent or when an error occurs. The STOP task must be issued, either through the local or PPI shortcut, or in software as part of the error handler.

## 8.23.5 TWIM read sequence

A TWIM read sequence is started by triggering the DMA.RX.START task. After the DMA.RX.START task has been triggered, TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE = 0 , READ = 1 ). The address must match the address of the target device that the controller wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit (ACK = 0 or NACK = 1) generated by the target.

After sending the ACK bit, the TWI target sends data to the controller using the clock generated by TWIM.

Data received will be stored in RAM at the address specified in the RXD.PTR register. TWIM will generate an ACK before the last byte is received from the target. TWIM generates a NACK after the last byte received to indicate that the read sequence will stop.

A typical TWIM read sequence is illustrated in the following figure, including clock stretching performed by TWIM following a SUSPEND task.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 147: TWIM reading data from a target

![]({{img:images/6f2db58e4394c8c6d7541cc91169da9e5ce3779ca449d78d8a265cd439ab09fb.jpg}})

A SUSPENDED event indicates that the SUSPEND task has taken effect. This event can be used to synchronize the software.

TWIM generates a LASTRX event when it is ready to receive the last byte. If RXD.MAXCNT > 1, the LASTRX event is generated after sending the ACK of the previously received byte. If RXD.MAXCNT = 1, the LASTRX event is generated after receiving the ACK following the address and READ bit.

TWIM is stopped by triggering the STOP task. This task must be triggered before the NACK bit begins transmission. The STOP task can be triggered at any time during the reception of the last byte. It is recommended to use the shortcut between LASTRX and STOP.

TWIM does not stop on its own when the RAM buffer is full or when an error occurs. The STOP task must be issued, either through a local or PPI shortcut, or in software as part of the error handler.

TWIM cannot be stopped while suspended. The STOP task must be issued after TWIM has been resumed.

## 8.23.6 TWIM repeated start sequence

A typical repeated start sequence is when TWIM writes two bytes to the target followed by reading four bytes from the target. This example uses shortcuts to perform a simple repeated start sequence, with one write followed by one read. The same approach can be used to perform a repeated start sequence where the sequence is read followed by a write.

The following figure shows an example of a repeated start sequence where TWIM writes two bytes followed by reading four bytes from the target.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 148: Controller repeated start sequence

![]({{img:images/4b9ad825576d26f7ce3e4433cf890f60e775fa448a1cf220e6bd337da8c1a7e4.jpg}})

If a more complex repeated start sequence is needed, and the TWI firmware drive is serviced in a low priority interrupt, use the SUSPEND task and SUSPENDED event to ensure that the correct tasks are generated at the correct time. A double repeated start sequence using the SUSPEND task to secure safe operation in low priority interrupts is shown in the following figure.

Figure 149: Double repeated start sequence

**Figure 148: Controller repeated start sequence**

![]({{img:images/a9a84e18b007cd87206bae4fa1fa273cacd6e7ea0c6772ec42beb792e1feb4ac.jpg}})

## 8.23.7 Low power

When the peripheral is not needed, stop and disable TWIM for lowest possible power consumption.

When the STOP task is sent, the software must wait until the STOPPED event is received before disabling the peripheral through the ENABLE register. If the peripheral is already stopped, the STOP task is not needed.

## 8.23.8 TWIM pin configuration

The SCL and SDA signals are mapped to physical pins using the PSEL.SCL and PSEL.SDA registers.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

These registers and their configurations are only used when TWIM is enabled, and retained while the device is in System ON mode. When the peripheral is disabled, the pins behave as regular GPIOs and are configured according to their respective OUT bit field and PIN\_CNF[n] register. Configure registers PSEL.SCL and PSEL.SDA when TWIM is disabled.

Only one peripheral can be assigned to drive a GPIO pin at a time. If more than one peripheral is assigned to a GPIO pin, it could result in unpredictable behavior.

When TWIM is in System OFF mode or disabled, the pins using TWIM must be configured by the GPIO peripheral according to the following table to ensure correct pin behavior.

Table 64: GPIO configuration before enabling peripheral

| TWIM signal | TWIM pin | Drive strength | Direction | Output value |
| --------------- | -------------------------- | ------------------ | ------------- | ---------------- |
| SCL | As specified in PSEL.SCL | S0D1 | Input | Not applicable |
| SDA | As specified in PSEL.SDA | S0D1 | Input | Not applicable |

## 8.23.9 Pull-up resistor

1000 kbps bit rate is supported when using H0D1 drive strength, 1 kΩ pull-up resistor, and maximum 50 pF bus capacitance. For other bit rates, see the following figure.

**Figure 150: Recommended TWIM pull-up value vs. line capacitance**

![]({{img:images/3cbbeefc344c5d93d55ecac59872ce70c9f9d2809e5322b429dde946c37eca4f.jpg}})

Figure 150: Recommended TWIM pull-up value vs. line capacitance

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

- The I 2 C bus specification allows a maximum line capacitance of 400 pF.
- The value of internal pull-up resistor (RPU) for nRF54L15/10/05 can be found in GPIO - General purpose input/output on page 272.

## 8.23.10 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| ------------------------ | ---------- | ----------------------- | ------------- | ------------- | ------------- | --------- | ------------------------------ |
|  |  |  | Map | Att | DMA | access |  |
| TWIM20 : S TWIM20 : NS | GLOBAL | 0x500C6000 0x400C6000 | US | S | SA | No | Two-wire interface controller TWIM20 |
| TWIM21 : S TWIM21 : NS | GLOBAL | 0x500C7000 0x400C7000 | US | S | SA | No | Two-wire interface controller TWIM21 |
| TWIM22 : S TWIM22 : NS | GLOBAL | 0x500C8000 0x400C8000 | US | S | SA | No | Two-wire interface controller TWIM22 |
| TWIM30 : S TWIM30 : NS | GLOBAL | 0x50104000 0x40104000 | US | S | SA | No | Two-wire interface controller TWIM30 |


| Instance | Domain | Configuration |
| ------------------------ | ---------- | ------------------ |
| TWIM20 : S TWIM20 : NS | GLOBAL | Use GPIO port P1 |
| TWIM21 : S TWIM21 : NS | GLOBAL | Use GPIO port P1 |
| TWIM22 : S TWIM22 : NS | GLOBAL | Use GPIO port P1 |
| TWIM30 : S TWIM30 : NS | GLOBAL | Use GPIO port P0 |


| Register | Offset | TZ | Description |
| ------------------------------ | ---------- | ------ | ------------------------------ |
| TASKS_STOP | 0x004 |  | Stop TWI transaction. Must be issued while the TWI master is not suspended. |
| TASKS_SUSPEND | 0x00C |  | Suspend TWI transaction |
| TASKS_RESUME | 0x010 |  | Resume TWI transaction |
| TASKS_DMA.RX.START | 0x028 |  | Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. |
| TASKS_DMA.RX.STOP | 0x02C |  | Stops operation using easyDMA. This does not trigger an END event. |
| TASKS_DMA.RX.ENABLEMATCH[n] | 0x030 |  | Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. |
| TASKS_DMA.RX.DISABLEMATCH[n] | 0x040 |  | Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. |
| TASKS_DMA.TX.START | 0x050 |  | Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. |
| TASKS_DMA.TX.STOP | 0x054 |  | Stops operation using easyDMA. This does not trigger an END event. |
| SUBSCRIBE_STOP | 0x084 |  | Subscribe configuration for task STOP |
| SUBSCRIBE_SUSPEND | 0x08C |  | Subscribe configuration for task SUSPEND |
| SUBSCRIBE_RESUME | 0x090 |  | Subscribe configuration for task RESUME |
| SUBSCRIBE_DMA.RX.START | 0x0A8 |  | Subscribe configuration for task START |
| SUBSCRIBE_DMA.RX.STOP | 0x0AC |  | Subscribe configuration for task STOP |
| SUBSCRIBE_DMA.RX.ENABLEMATCH[n] | 0x0B0 |  | Subscribe configuration for task ENABLEMATCH[n] |
| Register | Offset | TZ | Description |
| SUBSCRIBE_DMA.RX.DISABLEMATCH[n] | 0x0C0 |  | Subscribe configuration for task DISABLEMATCH[n] |
| SUBSCRIBE_DMA.TX.START | 0x0D0 |  | Subscribe configuration for task START |
| SUBSCRIBE_DMA.TX.STOP | 0x0D4 |  | Subscribe configuration for task STOP |
| EVENTS_STOPPED | 0x104 |  | TWI stopped |
| EVENTS_ERROR | 0x114 |  | TWI error |
| EVENTS_SUSPENDED | 0x128 |  | SUSPEND task has been issued, TWI traffic is now suspended. |
| EVENTS_LASTRX | 0x134 |  | Byte boundary, starting to receive the last byte |
| EVENTS_LASTTX | 0x138 |  | Byte boundary, starting to transmit the last byte |
| EVENTS_DMA.RX.END | 0x14C |  | Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. |
| EVENTS_DMA.RX.READY | 0x150 |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.RX.BUSERROR | 0x154 |  | An error occured during the bus transfer. |
| EVENTS_DMA.RX.MATCH[n] | 0x158 |  | Pattern match is detected on the DMA data bus. |
| EVENTS_DMA.TX.END | 0x168 |  | Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. |
| EVENTS_DMA.TX.READY | 0x16C |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.TX.BUSERROR | 0x170 |  | An error occured during the bus transfer. |
| PUBLISH_STOPPED | 0x184 |  | Publish configuration for event STOPPED |
| PUBLISH_ERROR | 0x194 |  | Publish configuration for event ERROR |
| PUBLISH_SUSPENDED | 0x1A8 |  | Publish configuration for event SUSPENDED |
| PUBLISH_LASTRX | 0x1B4 |  | Publish configuration for event LASTRX |
| PUBLISH_LASTTX | 0x1B8 |  | Publish configuration for event LASTTX |
| PUBLISH_DMA.RX.END | 0x1CC |  | Publish configuration for event END |
| PUBLISH_DMA.RX.READY | 0x1D0 |  | Publish configuration for event READY |
| PUBLISH_DMA.RX.BUSERROR | 0x1D4 |  | Publish configuration for event BUSERROR |
| PUBLISH_DMA.RX.MATCH[n] | 0x1D8 |  | Publish configuration for event MATCH[n] |
| PUBLISH_DMA.TX.END | 0x1E8 |  | Publish configuration for event END |
| PUBLISH_DMA.TX.READY | 0x1EC |  | Publish configuration for event READY |
| PUBLISH_DMA.TX.BUSERROR | 0x1F0 |  | Publish configuration for event BUSERROR |
| SHORTS | 0x200 |  | Shortcuts between local events and tasks |
| INTEN | 0x300 |  | Enable or disable interrupt |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| ERRORSRC | 0x4C4 |  | Error source |
| ENABLE | 0x500 |  | Enable TWIM |
| FREQUENCY | 0x524 |  | TWI frequency. Accuracy depends on the HFCLK source selected. |
| ADDRESS | 0x588 |  | Address used in the TWI transfer |
| PSEL.SCL | 0x600 |  | Pin select for SCL signal |
| PSEL.SDA | 0x604 |  | Pin select for SDA signal |
| DMA.RX.PTR | 0x704 |  | RAM buffer start address |
| DMA.RX.MAXCNT | 0x708 |  | Maximum number of bytes in channel buffer |
|  | 0x70C |  | Number of bytes transferred in the last transaction, updated after the END event. |
| DMA.RX.AMOUNT |  |  |  |
| Also updated DMA.RX.TERMINATEONBUSERROR | 0x71C |  | after each MATCH event. Terminate the transaction if a BUSERROR event is detected. |
| DMA.RX.MATCH.CONFIG | 0x724 |  | Configure individual match events |
| DMA.RX.MATCH.CANDIDATE[n] | 0x728 |  | The data to look for - any match will trigger the MATCH[n] event, if enabled. |
| DMA.TX.PTR RAM buffer | 0x73C |  | start address |
| Maximum | 0x740 0x744 |  | number of bytes in channel buffer Number of bytes transferred in the last transaction, updated after the END |
| DMA.TX.MAXCNT DMA.TX.AMOUNT |  |  |  |
| Also updated after each MATCH |  |  | event. |
| event. | event. | event. | event. |
| Register | Offset | TZ | Description |
| DMA.TX.TERMINATEONBUSERROR | 0x754 |  | Terminate the transaction if a BUSERROR event is detected. |
| DMA.TX.BUSERRORADDRESS | 0x758 |  | Address of transaction that generated the last BUSERROR event. |

## 8.23.10.1 TASKS\_STOP

Address offset: 0x004

Stop TWI transaction. Must be issued while the TWI master is not suspended.

![]({{img:images/d47473ad1f21827e62e033d1094363d693c6636efea6146ff6ae4a9d2a6c828a.jpg}})

## 8.23.10.2 TASKS\_SUSPEND

Address offset: 0x00C

Suspend TWI transaction

![]({{img:images/ca1006a6ac7e271de25844c4f05c7ff729cff84cbdbbdfc7daf3543140b6f666.jpg}})

## 8.23.10.3 TASKS\_RESUME

Address offset: 0x010

Resume TWI transaction

![]({{img:images/75ff409b6a065514498ca52f7ae99d3d1bdd3851cfe9a89525d9c921adb039ce.jpg}})

## 8.23.10.4 TASKS\_DMA

Peripheral tasks.

## 8.23.10.4.1 TASKS\_DMA.RX

Peripheral tasks.

## 8.23.10.4.1.1 TASKS\_DMA.RX.START

Address offset: 0x028

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.

![]({{img:images/2005b577fab3491462ee43d32f6ed6d8438974901dd164565b1f7129c8ac3115.jpg}})

## 8.23.10.4.1.2 TASKS\_DMA.RX.STOP

Address offset: 0x02C

Stops operation using easyDMA. This does not trigger an END event.

![]({{img:images/fa841804383cd9de316a2ac7caa7199e3a61f9795f1bcf90ac3b4e4ce72d5359.jpg}})

## 8.23.10.4.1.3 TASKS\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x030 + (n × 0x4)

Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.

![]({{img:images/ab903c0589221305f7f87b722a794b5d37a0dd8b320506b505980b94b7acd5dd.jpg}})

## 8.23.10.4.1.4 TASKS\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x040 + (n × 0x4)

Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.

![]({{img:images/e8078d3707b1367adfbf193fb73c2482c6cf4a928cc6ca2a69d6ed5bcc5e4702.jpg}})

## 8.23.10.4.2 TASKS\_DMA.TX

Peripheral tasks.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.23.10.4.2.1 TASKS\_DMA.TX.START

Address offset: 0x050

Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.

![]({{img:images/f05e5f842254460442826abb77326df029e3702100dfb63fe0c8b095915c3274.jpg}})

## 8.23.10.4.2.2 TASKS\_DMA.TX.STOP

Address offset: 0x054

Stops operation using easyDMA. This does not trigger an END event.

![]({{img:images/29c3df92c9476f5fee689328bebe8a847678142d51bd9ef3f42d688f8a22c11c.jpg}})

## 8.23.10.5 SUBSCRIBE\_STOP

Address offset: 0x084

Subscribe configuration for task STOP

![]({{img:images/a83f841af56ac7452958fe8e678bcdd05914cf3021241805045e790ea094ad14.jpg}})

## 8.23.10.6 SUBSCRIBE\_SUSPEND

Address offset: 0x08C

Subscribe configuration for task SUSPEND

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/bdc6fd84ec2b09c555d7db478d61bea238ae5733ffff38a9d1e4f122e3cf0b8c.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task SUSPEND will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.23.10.7 SUBSCRIBE\_RESUME

Address offset: 0x090

Subscribe configuration for task RESUME

![]({{img:images/109aba4b491e8715dbf7ec36b72bed1506c20ff1952dc2e8775c9b1b2fb3983d.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task RESUME will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.23.10.8 SUBSCRIBE\_DMA

Subscribe configuration for tasks

## 8.23.10.8.1 SUBSCRIBE\_DMA.RX

Subscribe configuration for tasks

## 8.23.10.8.1.1 SUBSCRIBE\_DMA.RX.START

Address offset: 0x0A8

Subscribe configuration for task START

![]({{img:images/90ee711f428e6af8c7d1e1f2a1fb15747b6139e6342dce137e1f2d04f702e9ee.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that task START will subscribe to |
| B | RW | EN |  |  |
|  |  | Disabled | 0 | Disable subscription |
|  |  | Enabled | 1 | Enable subscription |

## 8.23.10.8.1.2 SUBSCRIBE\_DMA.RX.STOP

Address offset: 0x0AC

Subscribe configuration for task STOP

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

8.23.10.8.1.3 SUBSCRIBE\_DMA.RX.ENABLEMATCH[n] (n=0..3)

**8.23.10.8.1.3 SUBSCRIBE_DMA.RX.ENABLEMATCH[n] (n=0..3)**

![]({{img:images/686617f9a9147736105fb059e6e9a629f33466ca2e26f1e9360bb41b1bd291b2.jpg}})

Address offset: 0x0B0 + (n × 0x4)

Subscribe configuration for task ENABLEMATCH[n]

8.23.10.8.1.4 SUBSCRIBE\_DMA.RX.DISABLEMATCH[n] (n=0..3)

**8.23.10.8.1.4 SUBSCRIBE_DMA.RX.DISABLEMATCH[n] (n=0..3)**

![]({{img:images/2b7a6bd0b26ec7038489f28c66146849bd92137b46ea0cacb493ceed9f839887.jpg}})

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task DISABLEMATCH[n]

![]({{img:images/831747efdb0a0872021ad186cda6b3c94dbcb81c651ca63b37ddfacb322cc0f3.jpg}})

## 8.23.10.8.2 SUBSCRIBE\_DMA.TX

Subscribe configuration for tasks

## 8.23.10.8.2.1 SUBSCRIBE\_DMA.TX.START

Address offset: 0x0D0

Subscribe configuration for task START

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/4171ba16bd0e16cc34c99b962020a9e358eaef64f95fab6cbb47c887e30f8ecb.jpg}})

## 8.23.10.8.2.2 SUBSCRIBE\_DMA.TX.STOP

Address offset: 0x0D4

Subscribe configuration for task STOP

![]({{img:images/85b791b9aa54ba531731bc31b114d706e1c6a8b6cf081579425ffbcc87ccf3ff.jpg}})

## 8.23.10.9 EVENTS\_STOPPED

Address offset: 0x104

TWI stopped

![]({{img:images/bd78199eb0d9130079d016d8f716dab3308ce594a8cc1b31f70655e94462be29.jpg}})

## 8.23.10.10 EVENTS\_ERROR

Address offset: 0x114

TWI error

![]({{img:images/5441197caa251105a8801b1818bfeaa448119a01a44776c382bb08038a67538c.jpg}})

## 8.23.10.11 EVENTS\_SUSPENDED

Address offset: 0x128

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

SUSPEND task has been issued, TWI traffic is now suspended.

![]({{img:images/7bd32daaf8ff89fed679116c3371b6462def096c345593ac38963cbfd35f203a.jpg}})

## 8.23.10.12 EVENTS\_LASTRX

Address offset: 0x134

Byte boundary, starting to receive the last byte

![]({{img:images/ced11703c64b25c93263e3fa304fc13af10e7f53e383eb621c2b9e3efa2ca7e7.jpg}})

## 8.23.10.13 EVENTS\_LASTTX

Address offset: 0x138

Byte boundary, starting to transmit the last byte

![]({{img:images/4120a40e6a1158f46dcdc8bbafa1426c54b7f7a2400e21ce83127f66a0839b73.jpg}})

## 8.23.10.14 EVENTS\_DMA

Peripheral events.

## 8.23.10.14.1 EVENTS\_DMA.RX

Peripheral events.

## 8.23.10.14.1.1 EVENTS\_DMA.RX.END

Address offset: 0x14C

Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/63c86c00a8f1cdc48ff1d4fa17ecbb022a47b0b2f40e48d92b642052041afdbb.jpg}})

## 8.23.10.14.1.2 EVENTS\_DMA.RX.READY

Address offset: 0x150

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/f068b9538d24e1f9cd83353b7bb5361af952303cae61ff4a70b9790e3b4c61c9.jpg}})

## 8.23.10.14.1.3 EVENTS\_DMA.RX.BUSERROR

Address offset: 0x154

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/c32e710e7f77c71573ea42a9f53cc756205a56a79d99914568b67428fa26eb80.jpg}})

## 8.23.10.14.1.4 EVENTS\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x158 + (n × 0x4)

Pattern match is detected on the DMA data bus.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/c48363b388c9cbea47b0f6828b5bee7a3c11442999c2a75a680f92414384455d.jpg}})

## 8.23.10.14.2 EVENTS\_DMA.TX

Peripheral events.

## 8.23.10.14.2.1 EVENTS\_DMA.TX.END

Address offset: 0x168

Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed.

![]({{img:images/1655752d34eea6c95d1ed4494ae117b4e0cd8b343772e18203b0b10814027114.jpg}})

## 8.23.10.14.2.2 EVENTS\_DMA.TX.READY

Address offset: 0x16C

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/4dd243b0d6441b91df76ebb9002626949c341e647b464cc7c6ed557ef45a12ed.jpg}})

## 8.23.10.14.2.3 EVENTS\_DMA.TX.BUSERROR

Address offset: 0x170

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/c4481a5d018a7b4c7ca91726d0d9e703938db7c75361fa65a4966ad7b7971703.jpg}})

## 8.23.10.15 PUBLISH\_STOPPED

Address offset: 0x184

Publish configuration for event STOPPED

![]({{img:images/35ef0f4b966877bab9c43a48cc55ca82065b119c18cf13380be579adf8b39b98.jpg}})

## 8.23.10.16 PUBLISH\_ERROR

Address offset: 0x194

Publish configuration for event ERROR

![]({{img:images/97ab5c43e52dbaf63e9302dc8dee06ea213f1f557d81478a600d3c7510efb6e7.jpg}})

## 8.23.10.17 PUBLISH\_SUSPENDED

Address offset: 0x1A8

Publish configuration for event SUSPENDED

![]({{img:images/b535312c44b62a64760f3de8642bba3f4c2ba9896e883ebdcd7ebe52300535ab.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that event SUSPENDED will publish to |
| B | RW | EN |  |  |
|  |  | Disabled | 0 | Disable publishing |
|  |  | Enabled | 1 | Enable publishing |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## 8.23.10.18 PUBLISH\_LASTRX

Address offset: 0x1B4

Publish configuration for event LASTRX

![]({{img:images/456501a096cb1f7995bc8bc56d8a8715aef85c858c923192d5c7851e447e8200.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that event LASTRX will publish to |
| B | RW | EN |  |  |
|  |  | Disabled | 0<br>Enabled 1 | Disable publishing<br>Enable publishing |

## 8.23.10.19 PUBLISH\_LASTTX

Address offset: 0x1B8

Publish configuration for event LASTTX

![]({{img:images/210a015ba0f57234a8b858fccdf183a522c06006e2436ce06131ad31e28490e8.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that event LASTTX will publish to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable publishing |
|  |  | Enabled | 1 Enable publishing |

## 8.23.10.20 PUBLISH\_DMA

Publish configuration for events

## 8.23.10.20.1 PUBLISH\_DMA.RX

Publish configuration for events

## 8.23.10.20.1.1 PUBLISH\_DMA.RX.END

Address offset: 0x1CC

Publish configuration for event END

![]({{img:images/4c2de11601169b71ddab8d2549cf02ca63223c1ead501e97988453fbf6acc73d.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that event END will publish to |
| B | RW | EN |  |  |
|  |  | Disabled | 0<br>Enabled 1 | Disable publishing<br>Enable publishing |

## 8.23.10.20.1.2 PUBLISH\_DMA.RX.READY

Address offset: 0x1D0

Publish configuration for event READY

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/0ed46d8e478fc025b0d6762e0ab69dc379f5bd065f3fd0274b7528ed2d974a71.jpg}})

## 8.23.10.20.1.3 PUBLISH\_DMA.RX.BUSERROR

Address offset: 0x1D4

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/541570df73ba1806a8f9513f22e430fda9261f0a766f90f588ade9052ed6a878.jpg}})

## 8.23.10.20.1.4 PUBLISH\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x1D8 + (n × 0x4)

Publish configuration for event MATCH[n]

![]({{img:images/21d6e192b68642c8cd70ede59e91890b8644a5e74be3bd3d2911fc277d7f0fcf.jpg}})

## 8.23.10.20.2 PUBLISH\_DMA.TX

Publish configuration for events

## 8.23.10.20.2.1 PUBLISH\_DMA.TX.END

Address offset: 0x1E8

Publish configuration for event END

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

8.23.10.20.2.2 PUBLISH\_DMA.TX.READY

**8.23.10.20.2.2 PUBLISH_DMA.TX.READY**

![]({{img:images/b41fc205cf408c325e7ae9d07bcaa16ca8cf0a307ed3a1940cc11011370e7e7b.jpg}})

Address offset: 0x1EC

Publish configuration for event READY

![]({{img:images/ed7b69333175ce5dff685b62a572b4c3f63fa1ef5cb2445ecc9c305fcb76c154.jpg}})

## 8.23.10.20.2.3 PUBLISH\_DMA.TX.BUSERROR

Address offset: 0x1F0

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/f2c8fddff7aacfe38869d5ded1e93260657a82aae34676ea9656512206304975.jpg}})

## 8.23.10.21 SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

![]({{img:images/c355e339c21e5a25a6cf657727c7aab1988fc03ab0a3e27f7a429c56c4134b63.jpg}})

![]({{img:images/cd342c6f2f4f0aed7d107b1812560b475663f9eff053cd8e267437b8cee82165.jpg}})

| Bit |  |  | number 31 30 29 28 27 26 25 24 |  |  |  | 23 22 21 20 | 8 7 | 4 3 2 |  | 9 |  | 6 5 1 0 |  |  | 19 18 17 16 |
| ------------------ | ----- | ------------------------------ | ------------------------------ | ------- | ---- | ----- | ------------------------ | -------------- | --------- | ----- | ------ | ---- | ----------- | ----- | ---------- | --------------- |
| ID |  |  |  |  |  | M L | I H G | B A |  |  | C |  |  |  | F |  |
| Reset 0x00000000 |  |  |  | 0 0 | 0 | 0 0 | 0 0 | 0 | 0 | 0 0 | 0 | 0 | 0 0 | 0 0 | 0 0 | 0 0 0 0 |
| ID | R/W | Field | Value ID<br>Disabled | Value<br>0 |  |  | Description<br>Disable |  |  |  |  |  |  |  | shortcut |  |
| C | RW | LASTTX_STOP | Disabled | 0 |  |  | Shortcut<br>Disable |  |  |  | STOP |  |  |  | between | event |
| D | RW | LASTRX_DMA_TX_START | Enabled | 1 |  |  | Shortcut<br>Enable | DMA.TX.START |  |  |  |  |  |  | between | event |
| E | RW | LASTRX_STOP | Disabled | 0 |  |  | Shortcut<br>Disable |  |  |  | STOP |  |  |  |  |  |
| F-I |  |  | Enabled<br>Disabled<br>Enabled | 1<br>1 |  |  | Enable<br>daisy-chaining<br>Allows<br>Disable<br>Enable |  |  |  |  |  |  |  | shortcut |  |
| J-M | RW | DMA_RX_MATCH[i]_DMA_RX_DISABLEMATCH[i]<br>(i=0..3) | Disabled | 0 |  |  | DMA.RX.DISABLEMATCH[n]<br>Disable |  |  |  |  |  |  |  | shortcut | between event |

## 8.23.10.22 INTEN

Address offset: 0x300

Enable or disable interrupt

| Bit number | Bit number | Bit number |
| -------------- | -------------- | -------------- |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/155eec417f73a7f295f5e447cc5f079ff5934fe527f2870b25c98a9e28d6ebf6.jpg}})

| Bit number |  |  |  | 31 30 29 28 27 26 |  |  | 25 24 | 23 22 21 20 | 15 14 | 13 | 12 11 | 10 9 8 7 6 5 4 3 | 2 1 |  | 0 |
| ------------------ | ------------------ | ------------------------ | ---------- | --------------------- | ----- | ---- | --------- | ------------------- | --------------------- | ------------------------------ | --------------------- | -------------------- | ------- | ----------- | ------- |
| ID |  |  |  |  | O | M | L K | J I H | E | D |  | C B |  |  | A |
| Reset 0x00000000 | Reset 0x00000000 |  |  | 0 0 | 0 0 | 0 | 0 0 | 0 0 0 | 0 0 |  | 0 0 | 0 0 0 0 | 0 0 0 | 0 0 | 0 0 0 |
| ID | R/W Field | Value<br>Disabled<br>Enabled | ID<br>1 | Value<br>0 |  |  |  | Description<br>Disable<br>Enable |  |  |  |  |  |  |  |
| H | RW | DMARXBUSERROR<br>Disabled<br>Enabled | 0<br>1 |  |  |  |  | Enable or<br>When<br>this<br>read from<br>the<br>Disable<br>Enable | interrupt for<br>generated,<br>BUSERRORADDRESS | event<br>the | DMARXBUSERROR<br>address register. | the error | be | can |  |
| I-L | RW | DMARXMATCH[i] (i=0..3) | Disabled<br>Enabled | 0<br>1 |  |  |  | Enable or<br>Disable<br>Enable | interrupt for |  | event DMARXMATCH[i] |  |  |  |  |
| M | RW | DMATXEND | Disabled<br>Enabled | 0<br>1 |  |  |  | Enable or disable<br>Disable<br>Enable | interrupt for | event | DMATXEND |  |  |  |  |
| N | RW | DMATXREADY<br>DMATXBUSERROR<br>Disabled | Disabled<br>Enabled<br>Enabled | 0<br>1<br>1 |  |  |  | Enable or Disable<br>Enable<br>Enable or<br>Enable | interrupt for event<br>interrupt for event | generated, the address BUSERRORADDRESS | DMATXREADY<br>register. |  | be | error can |  |
## 8.23.10.23 INTENSET

Address offset: 0x304

Enable interrupt

| Bit number |
| -------------- |

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Set

1

Enable

| Bit number ID |  |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 O N M L K J I H G F E C |  |  | D | B | 1 0 A |
| ------------------ | ------------------ | --------------------------- | ------------------------------ | ------- | ------------------ | ------------------------- | ------------------ | --------- |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 |  |  |  |  |  |
| ID R/W | Field | Value ID<br>Disabled<br>Enabled | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description<br>Read: Disabled<br>Read: Enabled | Value<br>0<br>1 | 0 0 0 | 0 0 | 0 0 0 | 0 |
| F RW | DMARXEND | Set<br>Disabled<br>Enabled | Write '1' to<br>1 Enable<br>Read: Disabled<br>1 Read: Enabled | 0 | enable interrupt | for event DMARXEND |  |  |
| G | RW | DMARXREADY<br>Set<br>Disabled<br>Enabled | Write '1' to<br>1 Enable<br>0 Read: Disabled<br>1 Read: Enabled |  | enable interrupt | for event DMARXREADY |  |  |
| H | RW |  | Write '1' to |  | enable interrupt | for event DMARXBUSERROR |  |  |
|  | DMARXBUSERROR |  |  |  | is generated,<br>BUSERRORADDRESS | the address<br>register. | caused the error | can be |
| I-L | RW DMARXMATCH[i] | Disabled Enabled (i=0..3)<br>Set<br>Disabled<br>Enabled | 0 Read: Disabled Read: Enabled Write '1' to<br>1 Enable<br>0 Read: Disabled<br>1 Read: Enabled | 1 | enable interrupt | for event DMARXMATCH[i] |  |  |
| M | RW DMATXEND | Set<br>Disabled<br>Enabled | Write '1' to<br>1 Enable<br>0 Read: Disabled<br>1 Read: Enabled |  | enable interrupt<br>enable interrupt | for event DMATXEND |  |  |
| N | RW DMATXREADY |  | Write '1' to for DMATXREADY |  |  | event |  |  |
## 8.23.10.24 INTENCLR

Address offset: 0x308

Disable interrupt

![]({{img:images/fb970df0b18765721af9993eeee76871dec01c8eaed2da8156d1dcf9577bc820.jpg}})

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------------------------------ |
| ID |  | O N M L K J I H G F E D C B A |
| Reset 0x00000000 |  | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW STOPPED |  | Write '1' to disable interrupt for event STOPPED |
|  | Clear | 1 Disable |
|  | Disabled | 0 Read: Disabled |
|  | Enabled | 1 Read: Enabled |
| B RW ERROR |  | Write '1' to disable interrupt for event ERROR |

![]({{img:images/62a0c62ea0856973d4c4d6d53cb391b984f0e46c6744364b73d1167255867de4.jpg}})

| Bit | number |  | 31 30 29 | 28 27 26 25 24 23 16 15 14 13 12 11 10 9 8 7 6 5 |  | 22 21 20 19 18 17 |  |  | 4 | 3 | 2 1 0 | 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ | ------------- | ------------------------------ | ----------------- | ----------------------- | ------- | -------- | --------- | --------- |
| ID |  |  |  | F | O N M L K J | I H G | E | D C |  | B | A | A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000<br>Clear<br>Disabled | 0<br>1<br>0 | 0 0 0 0 0 0 | 0 0 0<br>Disable<br>Read: Disabled | 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 | 0 0 | 0 0 | 0 0 |
| C | RW | SUSPENDED<br>LASTRX | Enabled<br>Clear<br>Disabled<br>Enabled<br>Disabled | 1<br>1<br>0<br>1<br>1 | Read:<br>Read: | Enabled Write '1' to disable<br>Disable<br>Read: Disabled<br>Enabled Write '1' to disable<br>Disable | interrupt for<br>interrupt<br>for | event SUSPENDED<br>LASTRX |  |  |  |  |
| D | RW |  | Clear Disabled | 1 0<br>1 |  | Read: Disabled<br>Read: Enabled |  | event |  |  |  |  |
| E | RW | LASTTX | Enabled<br>Clear | disable 1<br>0 |  | Write '1' to<br>Disable<br>Read: Disabled | interrupt for | event LASTTX |  |  |  |  |
| F | RW | DMARXEND | Enabled<br>Clear<br>Disabled | 1<br>0 |  | Read: Enabled<br>Write '1' to disable Disable<br>Read: Disabled Read:<br>Write '1' | interrupt for | event DMARXEND<br>event |  |  |  |  |
| G | RW | DMARXREADY | Enabled<br>Disabled<br>Clear<br>Enabled | disable<br>1<br>0<br>1<br>1 | Read: | Enabled<br>to Disabled<br>Disable<br>Read: Enabled | interrupt<br>for | DMARXREADY |  |  |  |  |
| H | RW | DMARXBUSERROR | Clear<br>Disabled | 1<br>0 |  | Write '1' to<br>When<br>disable<br>this event<br>Disable<br>Read: Disabled | interrupt<br>BUSERRORADDRESS<br>for<br>generated, | event DMARXBUSERROR<br>register.<br>the address | error | can<br>be |  |  |
| I-L | RW | DMARXMATCH[i] | (i=0..3)<br>Clear<br>Disabled | 1<br>0 |  | Write '1' to disable<br>Disable<br>Read: Disabled | interrupt for | event DMARXMATCH[i] |  |  |  |  |
| M | RW | DMATXEND | Clear<br>Disabled | 1<br>0 |  | Write '1' to disable Disable<br>Read: Disabled | interrupt for | event DMATXEND |  |  |  |  |
| N | RW | DMATXREADY | Clear<br>Disabled | disable<br>1<br>0 |  | Read: Enabled<br>Write '1'<br>to<br>Disable<br>Read: Disabled | interrupt for | event DMATXREADY |  |  |  |  |
| O | RW | DMATXBUSERROR | Clear<br>Disabled<br>Enabled | disable<br>1<br>0<br>1 |  | When this<br>read<br>Write '1' to<br>from<br>Disable<br>Read: Disabled<br>Read: Enabled | BUSERRORADDRESS<br>interrupt for<br>generated, | address register.<br>event DMATXBUSERROR | error | can be |  |  |

## 8.23.10.25 ERRORSRC

Address offset: 0x4C4

Error source

![]({{img:images/a2b0701885a6bdf68cc5a6d0295e85db44359381e2b8f06bd8a5fe3afa2406a3.jpg}})

| Bit number | 31 30 29 | Bit number | Bit number |
| -------------- | ------------ | -------------- | -------------- |

## 8.23.10.26 ENABLE

Address offset: 0x500

## Enable TWIM

![]({{img:images/4c19b34ec221f0d8dc63e1cba4e3f3015f40b4d7b180e3cf44776060acc2c424.jpg}})

## 8.23.10.27 FREQUENCY

Address offset: 0x524

TWI frequency. Accuracy depends on the HFCLK source selected.

![]({{img:images/ea9e394c6b940dfcdafe310ee251085fca2f70563a567fd17375c85b1c4eed1b.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.23.10.28 ADDRESS

Address offset: 0x588

Address used in the TWI transfer

![]({{img:images/f6a7744f3fbafe680768ca6697b9be7b8cc1d2d89ecc4a411b10be493dddd46f.jpg}})

## 8.23.10.29 PSEL.SCL

Address offset: 0x600

Pin select for SCL signal

![]({{img:images/93f65f6d3e18b037536852c6b8fdf49ea85ce7d9acfb38e3591bf9d7d948730c.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | PIN |  | [0..31] Pin number |
| B | RW | PORT |  | [0..7] Port number |
| C | RW | CONNECT | Disconnected<br>Connected | Connection<br>1 Disconnect<br>0 Connect |

## 8.23.10.30 PSEL.SDA

Address offset: 0x604

Pin select for SDA signal

![]({{img:images/7bb98ce67e7db860825cda369a2657766136bb38c18623eaca5df18f1856ad93.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | C B B B A A A A A |
| Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | Reset 0xFFFFFFFF | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
| ID | R/W | Field Value ID | Value | Description |
| A | RW | PIN | [0..31] | Pin number |
| B | RW | PORT | [0..7] | Port number |
| C | RW | CONNECT |  | Connection |
|  |  | Disconnected | 1 | Disconnect |
|  |  | Connected | 0 | Connect |

## 8.23.10.31 DMA.RX.PTR

Address offset: 0x704

RAM buffer start address

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/3dd97f175ff03a44d6d81252faa36c8474a0433949870d0441589bdc4189775b.jpg}})

## 8.23.10.32 DMA.RX.MAXCNT

Address offset: 0x708

Maximum number of bytes in channel buffer

![]({{img:images/441757a71a228bfa49796d961ebbee1f7673658dd84274ecfe879c89358c9833.jpg}})

## 8.23.10.33 DMA.RX.AMOUNT

Address offset: 0x70C

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/671ac653824627742599952e92e61a70e066cd228f716d59a66d8f254ab906b9.jpg}})

## 8.23.10.34 DMA.RX.TERMINATEONBUSERROR

Address offset: 0x71C

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/f3aab590ef964f035f26c7b937d9285a797c4faf18639b27b98a221dae404c54.jpg}})

## 8.23.10.35 DMA.RX.BUSERRORADDRESS

Address offset: 0x720

Address of transaction that generated the last BUSERROR event.

![]({{img:images/33fe139d94bd9212e000108767e59c6833bd9c98cf4c9184a339967f71b45081.jpg}})

![]({{img:images/ce419e238ca6d6da9bfd952e1f731cbeab50a1ea44125f3b49a024778a495cd5.jpg}})

## 8.23.10.36 DMA.RX.MATCH

Registers to control the behavior of the pattern matcher engine

## 8.23.10.36.1 DMA.RX.MATCH.CONFIG

Address offset: 0x724

Configure individual match events

![]({{img:images/b3baacc0ad7c9a79c08c05cffee3fd2b303d292d109ec190f5ef331b76457bc8.jpg}})

## 8.23.10.36.2 DMA.RX.MATCH.CANDIDATE[n] (n=0..3)

Address offset: 0x728 + (n × 0x4)

The data to look for - any match will trigger the MATCH[n] event, if enabled.

Note: This register can be updated while a transfer is in progress, but the new value will not take effect until either the DMA is restarted or the match event is generated. That makes it possible to write a new set of match words which will be searched for immediately after the event triggers.

![]({{img:images/a3e0d87528ad72d93bf85e9c46ac59a059aa96f20bddfbefbeb9f1ae6a3dc69f.jpg}})

## 8.23.10.37 DMA.TX.PTR

Address offset: 0x73C

RAM buffer start address

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/9201e77d79359e896227c4170e9f366118cf069189eff86a90241e04367a2afa.jpg}})

## 8.23.10.38 DMA.TX.MAXCNT

Address offset: 0x740

Maximum number of bytes in channel buffer

![]({{img:images/441757a71a228bfa49796d961ebbee1f7673658dd84274ecfe879c89358c9833.jpg}})

## 8.23.10.39 DMA.TX.AMOUNT

Address offset: 0x744

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/0170c1485c4ff2973530cddfb7300fa5e2b6147c6c62529af015421bd4d979e2.jpg}})

## 8.23.10.40 DMA.TX.TERMINATEONBUSERROR

Address offset: 0x754

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/f3aab590ef964f035f26c7b937d9285a797c4faf18639b27b98a221dae404c54.jpg}})

## 8.23.10.41 DMA.TX.BUSERRORADDRESS

Address offset: 0x758

Address of transaction that generated the last BUSERROR event.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/65172586f4de153219042b32474502c9e9b1b56fb176ecb202cdaefcee7948ff.jpg}})

## 8.24 TWIS - I 2 C compatible two-wire interface target with EasyDMA

The TWI target peripheral (TWIS) with EasyDMA provides a half duplex, two-wire synchronous serial communication interface.

The main features of TWIS are the following:

- I 2 C compatible
- Supports 100 kbps and 400 kbps bit rate
- EasyDMA direct transfer to and from RAM
- Individual selection of I/O pins
- Support for clock stretching

Figure 151: TWIS with EasyDMA

![]({{img:images/25b48f9cab84ce752c2611efa28b39b6d49d4360e219108fdbd5ce676d82068f.jpg}})

A typical TWI setup consists of one controller and one or more targets, as seen in the following figure. Only a single controller can be used on the TWI bus.

Figure 152: Typical TWI setup with one controller and three targets

**Figure 151: TWIS with EasyDMA**

![]({{img:images/59c2af23bf22f8aac8c60c36f83f57ebe4a8cf3574107d5b334fb2b26e0a9675.jpg}})

## 8.24.1 State machine

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

The following figure shows the TWIS state machine.

Figure 153: TWIS state machine

![]({{img:images/ec7803e0fff976800dd7a8840fb326419973047ee00b9cdfbc11fdf112d2ca18.jpg}})

The following table contains descriptions of the symbols used in the state machine.

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

Table 65: TWI slave state machine symbols

| Symbol | Type | Description |
| ------------------- | -------------- | ------------------------------ |
| ENABLE | Register | TWIS enabled via the ENABLE register. |
| PREPARETX | Task | The TASKS_PREPARETX task was triggered. |
| STOP | Task | The TASKS_STOP task was triggered. |
| PREPARERX | Task | The TASKS_PREPARERX task was triggered. |
| STOPPED | Event | The EVENTS_STOPPED event was generated. |
| DMA.RX.READY | Event | The EVENTS_DMA.RX.READY event was generated. |
| DMA.TX.READY | Event | The EVENTS_DMA.TX.READY event was generated. |
| TX prepared | Internal | Internal flag indicating that a TASKS_PREPARETX task was triggered. |
| RX prepared | Internal | Internal flag indicating that a TASKS_PREPARERX task was triggered. |
| Unprepare TX | Internal | Clears the TX prepared flag until the next TASKS_PREPARETX task. |
| Unprepare RX | Internal | Clears the RX prepared flag until the next TASKS_PREPARERX task. |
| Stop condition | TWI protocol | A TWI stop condition was detected. |
| Restart condition | TWI protocol | A TWI restart condition was detected. |

TWIS supports clock stretching. In order to use this feature, the controller must also support clock stretching for the feature to execute properly. TWIS operates in a low-power mode while waiting for the TWI controller to initiate a transfer. As long as TWIS is not addressed, it will remain in this mode.

For TWIS to run correctly, PSEL.SCL, PSEL.SDA, CONFIG, and the ADDRESS[n] registers must be configured, the SCL and SDA lines must both be high, before enabling TWIS through the ENABLE register. Similarly, changing these settings must be performed while TWIS is disabled. Failing to do so may result in unpredictable behavior.

## 8.24.2 Shared resources

The TWIS peripheral shares registers and other resources with peripherals that have the same ID as TWIS. Before TWIS can be configured and used, all peripherals that have the same ID as TWIS must be disabled.

Disabling a peripheral with the same ID as TWIS will not reset any shared TWIS registers. Configure all TWIS registers to ensure they operate correctly.

See the Instantiation table in Instantiation on page 214 for details on peripherals and their IDs.

## 8.24.3 EasyDMA

TWIS implements EasyDMA for accessing RAM without CPU involvement.

TWIS implements the EasyDMA channels found in the following table.

| Channel | Type | Register Cluster |
| ----------- | -------- | -------------------- |
| TXD | READER | TXD |
| RXD | WRITER | RXD |

Table 66: TWIS EasyDMA Channels

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

For detailed information regarding the use of EasyDMA, see EasyDMA on page 28.

The STOPPED event indicates that EasyDMA is finished accessing the buffer in RAM.

## 8.24.4 Read command response

Before TWIS can respond to a read command, it must be configured and enabled in the ENABLE register. When enabled, TWIS is in the IDLE state.

A read command is started when TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and setting the READ/WRITE bit to 1 (READ=1, WRITE=0). The READ/WRITE bit is followed by an ACK/NACK bit (ACK = 0, NACK = 1) response from the TWIS.

TWIS can listen for two addresses at a time. This is configured in the ADDRESS registers and the CONFIG register.

TWIS only acknowledges (ACK) the read command if the address presented by the controller matches one of the addresses the target is configured to listen for. TWIS will generate a READ event when it acknowledges the read command.

TWIS only detects a read command from the IDLE state.

TWIS will set an internal TX prepared flag when the PREPARETX task is triggered.

When the read command is received, TWIS will enter the TX state if the internal TX prepared flag is set.

If the internal TX prepared flag is not set when the read command is received, TWIS will stretch the controller's clock until the PREPARETX task is triggered and the internal TX prepared flag is set.

TWIS will generate the EVENTS\_DMA.TX.READY event and clear the TX prepared flag when it enters the TX state. In this state, TWIS will send the data bytes found in the transmit buffer to the controller using the controller's clock.

TWIS returns to the IDLE state if the TWIS receives a restart command when it is in the TX state.

TWIS is stopped when it receives the stop condition from TWIM. A STOPPED event will be generated when the transaction has stopped. TWIS will clear the TX prepared flag and go back to the IDLE state when it has stopped.

The transmit buffer is located in RAM at the address specified in the TXD.PTR register. TWIS will only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If TWIM forces TWIS to send more than TXD.MAXCNT bytes, the target will send the byte specified in the ORC register to the controller instead. If this happens, an ERROR event will be generated.

The EasyDMA configuration registers RXD.PTR, TXD.PTR, RXD.AMOUNT, and TXD.AMOUNT, are latched when the EVENTS\_DMA.TX.READY event is generated.

TWIS can be forced to stop by triggering the STOP task. A STOPPED event will be generated when TWIS has stopped. TWIS will clear the TX prepared flag and return to the IDLE state when it has stopped, see Terminate an ongoing TWI transaction on page 670.

Each byte sent from TWIS will be followed by an ACK/NACK bit sent from the controller. TWIM will generate a NACK following the last byte that it wants to receive to tell the target to release the bus allowing TWIM to generate the stop condition. The TXD.AMOUNT register can be queried after a transaction to see how many bytes were sent.

A typical TWIS read command response is illustrated in the following figure, including clock stretching following a SUSPEND task.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 154: TWIS responding to a read command

![]({{img:images/d4254f0aa86cc2f007148f8130741f2fe29f4d6998073cbb38ad1718fdbbc43a.jpg}})

## 8.24.5 Write command response

Before TWIS can respond to a write command, TWIS must be configured and enabled in the ENABLE register. When enabled, TWIS is in the IDLE state.

A write command is started when TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and setting the READ/WRITE bit to 0 (READ = 1, WRITE = 0). The READ/WRITE bit is followed by an ACK/NACK bit (ACK = 0, NACK = 1) response from the TWIS.

TWIS can listen for two addresses at a time. This is configured in the ADDRESS registers and the CONFIG register.

TWIS only acknowledges (ACK) the write command if the address presented by the controller matches one of the addresses the target is configured to listen for. TWIS will generate a WRITE event when it acknowledges the write command.

TWIS only detects a write command from the IDLE state.

TWIS will set an internal RX prepared flag when the PREPARERX task is triggered.

When the write command is received, TWIS will enter the RX state if the internal RX prepared flag is set.

If the internal RX prepared flag is not set when the write command is received, TWIS will start stretching the master's clock after the first data byte, not allowing the master to send the stop condition. Clock is stretched until the PREPARERX task is triggered and the internal RX prepared flag is set.

TWIS will generate the EVENTS\_DMA.RX.READY event and clear the internal RX prepared flag when it enters the RX state. In this state, TWIS will be able to receive the bytes sent by the TWIM.

TWIS returns to the IDLE state if TWIS receives a restart command when it is in the RX state.

TWIS is stopped when it receives the stop condition from TWIM. A STOPPED event will be generated when the transaction has stopped. TWIS will clear the internal RX prepared flag and go back to the IDLE state when it has stopped.

The receive buffer is located in RAM at the address specified in the RXD.PTR register. TWIS can only receive as many bytes as specified in the RXD.MAXCNT register. If TWIM tries to send more bytes to TWIS than it

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

can receive, the extra bytes are discarded and NACKed by the target. If this happens, an ERROR event will be generated.

The EasyDMA configuration registers, RXD.PTR, TXD.PTR, RXD.AMOUNT, and TXD.AMOUNT, are latched when the EVENTS\_DMA.RX.READY event is generated.

TWIS can be forced to stop by triggering the STOP task. A STOPPED event will be generated when TWIS has stopped. TWIS will clear the internal RX prepared flag and return to the IDLE state when it has stopped, see Terminate an ongoing TWI transaction on page 670.

TWIS will generate an ACK after every byte received from the controller. The RXD.AMOUNT register can be queried after a transaction to see how many bytes were received.

A typical TWIS write command response is illustrated in the following figure, including clock stretching following a SUSPEND task.

Figure 155: TWIS responding to a write command

![]({{img:images/6ed2c1691ab60a4db4e6a0d73c7a8438af98c9be5b8078843cbc5d2e45bb26e9.jpg}})

## 8.24.6 TWI controller repeated start sequence

A repeated start sequence is where the TWI controller writes two bytes to TWIS, followed by reading four bytes from the target. This is shown in the following figure.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 156: Repeated start sequence

![]({{img:images/ebe2c51319a23a2a4287306a8e92c9853b43a9ce2fe3dbbd2d7cd65fefc247e0.jpg}})

In this example, the receiver does not know in advance what the controller wants to read. This information is in the first two received bytes of the write in the repeated start sequence. For the CPU to process the received data before TWIS replies to the read command, the SUSPEND task is triggered. This is enabled through a shortcut from the READ event generated when the read command is received. When the CPU has processed the incoming data and prepared the correct data response, the CPU will resume the transaction by triggering the RESUME task.

## 8.24.7 Terminate an ongoing TWI transaction

In some situations, an ongoing transaction must be terminated. This can happen when the external TWI controller is not responding correctly, for example.

To stop an ongoing transaction, trigger the STOP task. A STOPPED event will be generated when TWIS stops. It is not dependent on the STOP condition being generated on the TWI bus. TWIS will release the bus when it has stopped and returns to its IDLE state.

## 8.24.8 Low power

When the peripheral is not needed, stop and disable TWIS for lowest possible power consumption.

When the STOP task is sent, the software must wait until the STOPPED event is received before disabling the peripheral through the ENABLE register. If the peripheral is already stopped, the STOP task is not needed.

## 8.24.9 Target mode pin configuration

The SCL and SDA signals are mapped to physical pins using the PSEL.SCL and PSEL.SDA registers.

The PSEL.SCL and PSEL.SDA registers and their configurations are only used when TWIS is enabled, and retained while the device is in System ON mode. When the peripheral is disabled, the pins function as regular GPIOs, and use the configuration in their respective OUT bit field and PIN\_CNF[n] register. Only configure PSEL.SCL and PSEL.SDA when TWIS is disabled.

When in System OFF mode or when TWIS is disabled, the TWIS pins must be configured in the GPIO peripheral as described in the following table to secure correct signal levels.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Only one peripheral can be assigned to drive a GPIO pin at a time. Failing to do so may result in unpredictable behavior.

Table 67: GPIO configuration before enabling peripheral

| TWIS signal | TWIS pin | Direction | Output value | Drive strength |
| --------------- | -------------------------- | ------------- | ---------------- | ------------------ |
| SCL | As specified in PSEL.SCL | Input | Not applicable | S0D1 |
| SDA | As specified in PSEL.SDA | Input | Not applicable | S0D1 |

## 8.24.10 Registers


| Instance | Domain | Base address | TrustZone | TrustZone | TrustZone | Split | Description |
| ------------------------ | ---------- | ----------------------- | ------------- | ------------- | ------------- | --------- | ------------------------------ |
|  |  |  | Map | Att | DMA | access |  |
| TWIS20 : S TWIS20 : NS | GLOBAL | 0x500C6000 0x400C6000 | US | S | SA | No | Two-wire interface target TWIS20 |
| TWIS21 : S TWIS21 : NS | GLOBAL | 0x500C7000 0x400C7000 | US | S | SA | No | Two-wire interface target TWIS21 |
| TWIS22 : S TWIS22 : NS | GLOBAL | 0x500C8000 0x400C8000 | US | S | SA | No | Two-wire interface target TWIS22 |
| TWIS30 : S TWIS30 : NS | GLOBAL | 0x50104000 0x40104000 | US | S | SA | No | Two-wire interface target TWIS30 |


| Instance | Domain | Configuration |
| ------------------------ | ---------- | ------------------ |
| TWIS20 : S TWIS20 : NS | GLOBAL | Use GPIO port P1 |
| TWIS21 : S TWIS21 : NS | GLOBAL | Use GPIO port P1 |
| TWIS22 : S TWIS22 : NS | GLOBAL | Use GPIO port P1 |
| TWIS30 : S TWIS30 : NS | GLOBAL | Use GPIO port P0 |


| Register | Offset | TZ | Description |
| ------------------------------ | ---------- | ------ | ------------------------------ |
| TASKS_STOP | 0x004 |  | Stop TWI transaction |
| TASKS_SUSPEND | 0x00C |  | Suspend TWI transaction |
| TASKS_RESUME | 0x010 |  | Resume TWI transaction |
| TASKS_PREPARERX | 0x020 |  | Prepare the TWI slave to respond to a write command |
| TASKS_PREPARETX | 0x024 |  | Prepare the TWI slave to respond to a read command |
| TASKS_DMA.RX.ENABLEMATCH[n] | 0x030 |  | Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. |
| TASKS_DMA.RX.DISABLEMATCH[n] | 0x040 |  | Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. |
| SUBSCRIBE_STOP | 0x084 |  | Subscribe configuration for task STOP |
| Register | Offset | TZ | Description |
| SUBSCRIBE_SUSPEND | 0x08C |  | Subscribe configuration for task SUSPEND |
| SUBSCRIBE_RESUME | 0x090 |  | Subscribe configuration for task RESUME |
| SUBSCRIBE_PREPARERX | 0x0A0 |  | Subscribe configuration for task PREPARERX |
| SUBSCRIBE_PREPARETX | 0x0A4 |  | Subscribe configuration for task PREPARETX |
| SUBSCRIBE_DMA.RX.ENABLEMATCH[n] | 0x0B0 |  | Subscribe configuration for task ENABLEMATCH[n] |
| SUBSCRIBE_DMA.RX.DISABLEMATCH[n] | 0x0C0 |  | Subscribe configuration for task DISABLEMATCH[n] |
| EVENTS_STOPPED | 0x104 |  | TWI stopped |
| EVENTS_ERROR | 0x114 |  | TWI error |
| EVENTS_WRITE | 0x13C |  | Write command received |
| EVENTS_READ | 0x140 |  | Read command received |
| EVENTS_DMA.RX.END | 0x14C |  | Generated after all MAXCNT bytes have been transferred |
| EVENTS_DMA.RX.READY | 0x150 |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.RX.BUSERROR | 0x154 |  | An error occured during the bus transfer. |
| EVENTS_DMA.RX.MATCH[n] | 0x158 |  | Pattern match is detected on the DMA data bus. |
| EVENTS_DMA.TX.END | 0x168 |  | Generated after all MAXCNT bytes have been transferred |
| EVENTS_DMA.TX.READY | 0x16C |  | Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. |
| EVENTS_DMA.TX.BUSERROR | 0x170 |  | An error occured during the bus transfer. |
| PUBLISH_STOPPED | 0x184 |  | Publish configuration for event STOPPED |
| PUBLISH_ERROR | 0x194 |  | Publish configuration for event ERROR |
| PUBLISH_WRITE | 0x1BC |  | Publish configuration for event WRITE |
| PUBLISH_READ | 0x1C0 |  | Publish configuration for event READ |
| PUBLISH_DMA.RX.END | 0x1CC |  | Publish configuration for event END |
| PUBLISH_DMA.RX.READY | 0x1D0 |  | Publish configuration for event READY |
| PUBLISH_DMA.RX.BUSERROR | 0x1D4 |  | Publish configuration for event BUSERROR |
| PUBLISH_DMA.RX.MATCH[n] | 0x1D8 |  | Publish configuration for event MATCH[n] |
| PUBLISH_DMA.TX.END | 0x1E8 |  | Publish configuration for event END |
| PUBLISH_DMA.TX.READY | 0x1EC |  | Publish configuration for event READY |
| PUBLISH_DMA.TX.BUSERROR | 0x1F0 |  | Publish configuration for event BUSERROR |
| SHORTS | 0x200 |  | Shortcuts between local events and tasks |
| INTEN | 0x300 |  | Enable or disable interrupt |
| INTENSET | 0x304 |  | Enable interrupt |
| INTENCLR | 0x308 |  | Disable interrupt |
| ERRORSRC | 0x4D0 |  | Error source |
| MATCH | 0x4D4 |  | Status register indicating which address had a match |
| ENABLE | 0x500 |  | Enable TWIS |
| ADDRESS[n] | 0x588 |  | TWI slave address n |
| CONFIG | 0x594 |  | Configuration register for the address match mechanism |
| ORC | 0x5C0 |  | Over-read character. Character sent out in case of an over-read of the transmit buffer. |
| PSEL.SCL | 0x600 |  | Pin select for SCL signal |
| PSEL.SDA | 0x604 |  | Pin select for SDA signal |
| DMA.RX.PTR | 0x704 |  | RAM buffer start address |
| DMA.RX.MAXCNT | 0x708 |  | Maximum number of bytes in channel buffer |
| DMA.RX.AMOUNT | 0x70C |  | Number of bytes transferred in the last transaction, updated after the END event.<br>Also updated after each MATCH event. |
| DMA.RX.TERMINATEONBUSERROR | 0x71C |  | Terminate the transaction if a BUSERROR event is detected. |
| DMA.RX.BUSERRORADDRESS | 0x720 |  | Address of transaction that generated the last BUSERROR event. |
| DMA.RX.MATCH.CONFIG | 0x724 |  | Configure individual match events |
| DMA.RX.MATCH.CANDIDATE[n] | 0x728 |  | The data to look for - any match will trigger the MATCH[n] event, if enabled. |
| DMA.TX.PTR | 0x73C |  | RAM buffer start address |
| DMA.TX.MAXCNT | 0x740 |  | Maximum number of bytes in channel buffer |

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/c03a72582d577f7b10dcefc243cff35d819aa77cceb05bde0a476d3e460a8350.jpg}})

## 8.24.10.1 TASKS\_STOP

Address offset: 0x004

Stop TWI transaction

![]({{img:images/ee197c107f4ef0b6ff70484e81a6ea6dde27a01e93c929cde01514474bd594b4.jpg}})

## 8.24.10.2 TASKS\_SUSPEND

Address offset: 0x00C

Suspend TWI transaction

![]({{img:images/666f76dab1214ef8a0bb1ba9ee1057587da854aa6ef0153e0614fb2ff0f740eb.jpg}})

## 8.24.10.3 TASKS\_RESUME

Address offset: 0x010

Resume TWI transaction

![]({{img:images/a83b880e83f5f0573827f374e110f8b0bdcbcc67c6725bc915f986dd3a1ec72e.jpg}})

## 8.24.10.4 TASKS\_PREPARERX

Address offset: 0x020

Prepare the TWI slave to respond to a write command

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/7f13211e7e56d2fa9471d5db5a89f1c559da570b61167124c11c96f301ef75c4.jpg}})

## 8.24.10.5 TASKS\_PREPARETX

Address offset: 0x024

Prepare the TWI slave to respond to a read command

![]({{img:images/fbdb2f4dcc9e045413a1250fc57bb36e8847eb0f17b7468017751dc21ec4bd06.jpg}})

## 8.24.10.6 TASKS\_DMA

Peripheral tasks.

## 8.24.10.6.1 TASKS\_DMA.RX

Peripheral tasks.

## 8.24.10.6.1.1 TASKS\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x030 + (n × 0x4)

Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.

![]({{img:images/d3bad9c22802d10bd157629bc9dd48693c04bc6e247f7555b27afd3a33fd9e92.jpg}})

## 8.24.10.6.1.2 TASKS\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x040 + (n × 0x4)

Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.

![]({{img:images/1896e658a16df902081d0c9edf3018fce356eede6a27d0daf660f800002d2b01.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.24.10.7 SUBSCRIBE\_STOP

Address offset: 0x084

Subscribe configuration for task STOP

![]({{img:images/6978e873109cd5284423fbe9d794644fe00c8d54269ede6e275165f5ef8972f3.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task STOP will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.24.10.8 SUBSCRIBE\_SUSPEND

Address offset: 0x08C

Subscribe configuration for task SUSPEND

![]({{img:images/55810da11e52c73d6cff51def772d9f14592527dad333c547d6986ecceec6d69.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task SUSPEND will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

## 8.24.10.9 SUBSCRIBE\_RESUME

Address offset: 0x090

Subscribe configuration for task RESUME

![]({{img:images/ccc2c89bfe42900eecb35be6a79ae8789fea33b3ba077b6fa3afb1b59dce7739.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task RESUME will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.24.10.10 SUBSCRIBE\_PREPARERX

Address offset: 0x0A0

Subscribe configuration for task PREPARERX

![]({{img:images/daea0475c0285f1ae174bca41ace609e5e3283de79a48b6c5ff36867afca8646.jpg}})

![]({{img:images/7fbaf2f52044f60882b6c054dfe42c5fbc2609393ce67cdbc948a254f532f508.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | R/W Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that task PREPARERX will subscribe to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable subscription<br>1 Enable subscription |

## 8.24.10.11 SUBSCRIBE\_PREPARETX

Address offset: 0x0A4

Subscribe configuration for task PREPARETX

![]({{img:images/03d66dcda459bc421a716fbe401de5c9cb56a8844531ac768c1188489a3b19dc.jpg}})

## 8.24.10.12 SUBSCRIBE\_DMA

Subscribe configuration for tasks

## 8.24.10.12.1 SUBSCRIBE\_DMA.RX

Subscribe configuration for tasks

## 8.24.10.12.1.1 SUBSCRIBE\_DMA.RX.ENABLEMATCH[n] (n=0..3)

Address offset: 0x0B0 + (n × 0x4)

Subscribe configuration for task ENABLEMATCH[n]

![]({{img:images/348eed46da9ae1ef03e98199effe9c5a84da0b7a107c81ba77f87f73f1fdf0a6.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW CHIDX |  | [0..255] DPPI channel that task ENABLEMATCH[n] will subscribe to |
| B | RW EN |  |  |
|  |  | Disabled | 0 Disable subscription |
|  |  | Enabled | 1 Enable subscription |

## 8.24.10.12.1.2 SUBSCRIBE\_DMA.RX.DISABLEMATCH[n] (n=0..3)

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task DISABLEMATCH[n]

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/40b9ef029b9042e666044057f3357bef1a2976e870ad6f175ca90ad92c03650d.jpg}})

## 8.24.10.13 EVENTS\_STOPPED

Address offset: 0x104

## TWI stopped

![]({{img:images/84c3f2b0ce90d3e1ca1f438ecae7bdc87be0ad8e07615c160457a127d4e01b0b.jpg}})

## 8.24.10.14 EVENTS\_ERROR

Address offset: 0x114

TWI error

![]({{img:images/094c83eac24d7c73057d2a7f0149c25f92a2e6e6c621e8dd063d1c78ac0498f9.jpg}})

## 8.24.10.15 EVENTS\_WRITE

Address offset: 0x13C

Write command received

![]({{img:images/2987d47856e4055c378631396779fd61c17a1bc9ffa7945e687a8286b8775bb0.jpg}})

## 8.24.10.16 EVENTS\_READ

Address offset: 0x140

Read command received

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/992f341249bf1a3cb5b4e42b9751ca7398dcec619636e2abff748cef552dc4c4.jpg}})

## 8.24.10.17 EVENTS\_DMA

Peripheral events.

## 8.24.10.17.1 EVENTS\_DMA.RX

Peripheral events.

## 8.24.10.17.1.1 EVENTS\_DMA.RX.END

Address offset: 0x14C

Generated after all MAXCNT bytes have been transferred

![]({{img:images/9f73ca7739a51e4035800947f40e67156cb703d8e8f35a6ba79270e5ab958131.jpg}})

## 8.24.10.17.1.2 EVENTS\_DMA.RX.READY

Address offset: 0x150

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/6d9b69725635341a9f7ec8d5f0055bc76c21e0975dbf527695c75364b613ed3f.jpg}})

## 8.24.10.17.1.3 EVENTS\_DMA.RX.BUSERROR

Address offset: 0x154

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/efca6b46956d995c28bfd68f3618166319950e6a3b41ed8891cd32e35ad63976.jpg}})

## 8.24.10.17.1.4 EVENTS\_DMA.RX.MATCH[n] (n=0..3)

Address offset: 0x158 + (n × 0x4)

Pattern match is detected on the DMA data bus.

![]({{img:images/15ab1576595fd63ddca60211e432ab3df5345cf5d1581d61c1bb157ea4aff37e.jpg}})

## 8.24.10.17.2 EVENTS\_DMA.TX

Peripheral events.

## 8.24.10.17.2.1 EVENTS\_DMA.TX.END

Address offset: 0x168

Generated after all MAXCNT bytes have been transferred

![]({{img:images/3a440f89c4bea965de15ead57e12e12060c3ec82f9fa48a62c1506e0d399ca0e.jpg}})

## 8.24.10.17.2.2 EVENTS\_DMA.TX.READY

Address offset: 0x16C

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

![]({{img:images/2a3457633830b6431ded0e98c1cbf57b8a748e274b834032ad2614bc41df66ac.jpg}})

## 8.24.10.17.2.3 EVENTS\_DMA.TX.BUSERROR

Address offset: 0x170

An error occured during the bus transfer.

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/b9546ae5264ab5c209958a76187d8ea13fc031ab8df1e207f370758c360952ae.jpg}})

## 8.24.10.18 PUBLISH\_STOPPED

Address offset: 0x184

Publish configuration for event STOPPED

![]({{img:images/b91e7bfd3f4b8b3d4e2be05a3fceec57e568f8df38f4320310c9c09346e2fbd2.jpg}})

## 8.24.10.19 PUBLISH\_ERROR

Address offset: 0x194

Publish configuration for event ERROR

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/143ef2530bea1239896a55acbe2ed5a9c6ec2338a52a61ea1d9729c4e04da53a.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that event ERROR will publish to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable publishing<br>1 Enable publishing |

## 8.24.10.20 PUBLISH\_WRITE

Address offset: 0x1BC

Publish configuration for event WRITE

![]({{img:images/e6fd504a3015d25759ff4a0d8c7bef5924039412fe2f264993a1fe735863f3e3.jpg}})

| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W | Field | Value ID | Value Description |
| A | RW | CHIDX |  | [0..255] DPPI channel that event WRITE will publish to |
| B | RW | EN | Disabled<br>Enabled | 0 Disable publishing<br>1 Enable publishing |

## 8.24.10.21 PUBLISH\_READ

Address offset: 0x1C0

Publish configuration for event READ

![]({{img:images/8290018a25bb619959751eb0ee3419fe853d1411cbbb40cf9194767d76965f0f.jpg}})

| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ------------------ | ------------------------------ | ------------------------------ |
| ID | ID | ID | B A A A A A A A A | B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description |
| A | RW CHIDX |  | [0..255] | DPPI channel that event READ will publish to |
| B | RW | EN |  |  |
|  |  | Disabled | 0 | Disable publishing |
|  |  | Enabled | 1 | Enable publishing |

## 8.24.10.22 PUBLISH\_DMA

Publish configuration for events

## 8.24.10.22.1 PUBLISH\_DMA.RX

Publish configuration for events

## 8.24.10.22.1.1 PUBLISH\_DMA.RX.END

Address offset: 0x1CC

Publish configuration for event END

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

8.24.10.22.1.2 PUBLISH\_DMA.RX.READY

**8.24.10.22.1.2 PUBLISH_DMA.RX.READY**

![]({{img:images/2ff241809a0400f82a42fee2b174d60014895eafb185b00130977d4d8048959c.jpg}})

Address offset: 0x1D0

Publish configuration for event READY

8.24.10.22.1.3 PUBLISH\_DMA.RX.BUSERROR

**8.24.10.22.1.3 PUBLISH_DMA.RX.BUSERROR**

![]({{img:images/ed7b69333175ce5dff685b62a572b4c3f63fa1ef5cb2445ecc9c305fcb76c154.jpg}})

Address offset: 0x1D4

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

8.24.10.22.1.4 PUBLISH\_DMA.RX.MATCH[n] (n=0..3)

**8.24.10.22.1.4 PUBLISH_DMA.RX.MATCH[n] (n=0..3)**

![]({{img:images/f2c8fddff7aacfe38869d5ded1e93260657a82aae34676ea9656512206304975.jpg}})

Address offset: 0x1D8 + (n × 0x4)

Publish configuration for event MATCH[n]

![]({{img:images/e0d26d0a788e25ff30291e5c7ffbef21793399270f8684981c834ca855fae7bb.jpg}})

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

## 8.24.10.22.2 PUBLISH\_DMA.TX

Publish configuration for events

## 8.24.10.22.2.1 PUBLISH\_DMA.TX.END

Address offset: 0x1E8

Publish configuration for event END

![]({{img:images/27bfb39a432ffb1010e7548a26e480a1fed412b0e1706db9e9b702ab3f17a94d.jpg}})

## 8.24.10.22.2.2 PUBLISH\_DMA.TX.READY

Address offset: 0x1EC

Publish configuration for event READY

![]({{img:images/9bb692e0cc8e3dfea47c617c0a87244614521e2c6d04f3d5ef21fdf7653ef2a0.jpg}})

## 8.24.10.22.2.3 PUBLISH\_DMA.TX.BUSERROR

Address offset: 0x1F0

Publish configuration for event BUSERROR

When this event is generated, the address which caused the error can be read from the BUSERRORADDRESS register.

![]({{img:images/ca2d63ac80353d48ddab50270f9664f8b6ef4184defdd7c004c5cd5fba859e9c.jpg}})

## 8.24.10.23 SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 | Bit number | Bit number |
| -------------- | ------------------------------ | -------------- | -------------- |

## 8.24.10.24 INTEN

Address offset: 0x300

Enable or disable interrupt

| Bit |  |  | number | 31 30 29 | 28 27 26 | 23 22 21 20 19 18 17 |  | 16 15 14 | 4 3 2 1 | 11 10 9 | 7 6 5 | 0 |
| ------- | ------- | --------------- | ---------- | ------------ | ------------ | ------------------------ | ------------ | ------------------------------ | ----------- | --------------- | --------- | ----- |
| ID |  |  |  |  | N M | I H G | F E | D C |  |  | B | A |
| Reset | Reset | 0x00000000 |  | 0 0 | 0 0 | 0 0 | 0 0 0 | 0 0 0 0 0 | 0 0 0 | 0 0 0 | 0 0 0 | 0 0 |
| ID | R/W | Field | Value ID | Value |  | Description |  |  |  |  |  |  |
| A | RW | STOPPED | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable | interrupt for event |  | STOPPED |  |  |
| B | RW | ERROR | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable | interrupt for event |  | ERROR |  |  |
| C | RW | WRITE | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable | interrupt for event |  | WRITE |  |  |
| D | RW | READ | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable | interrupt for event |  | READ |  |  |
| E | RW | DMARXEND | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable | interrupt for event |  | DMARXEND |  |  |
| F | RW | DMARXREADY | Disabled<br>Enabled | 0<br>1 |  | Enable or<br>Disable<br>Enable | disable | interrupt for event |  | DMARXREADY |  |  |
| G | RW | DMARXBUSERROR | Disabled<br>Enabled | 0<br>1 |  | Enable<br>When this<br>read from<br>Disable<br>Enable | or disable<br>event<br>the | interrupt for event<br>is generated, BUSERRORADDRESS | error can | DMARXBUSERROR<br>be | the |  |
| H-K | RW | DMARXMATCH[i] | (i=0..3) |  |  | Enable | or disable | interrupt for event |  | DMARXMATCH[i] |  |  |

![]({{img:images/b57659b59a54e54824bea968a3fee586c839ffdfd0132035f6f8cdf8c013835b.jpg}})

| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 | Bit number | Bit number |
| -------------- | ------------------------------ | -------------- | -------------- |

## 8.24.10.25 INTENSET

Address offset: 0x304

Enable interrupt

| Bit number |  | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 |  |  |  | 4 3 2 | 7 6 1 |  | 8 | 5 | 0 |
| ------------------ | ------------------ | ------------------------------ | ------- | ----- | ----------------------- | ------------------------------ | --------- | ----- | ------- | ------- | ----- |
| ID |  |  |  | N M | I H G F | E D C | B | A |  |  |  |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 0 | 0 0 | 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 | 0 0 | 0 0 0 | 0 0 0 | 0 0 |
| ID | R/W Field | Value ID | Value |  | Description |  |  |  |  |  |  |
| A | RW STOPPED | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | enable interrupt for event STOPPED |  |  |  |  |  |
| B RW | ERROR | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | enable interrupt for event ERROR |  |  |  |  |  |
| C RW | WRITE | Set<br>Disabled | 1<br>0 |  | Write '1' to<br>Enable Read: Disabled<br>Read: Enabled | enable interrupt for event WRITE |  |  |  |  |  |
| D RW | READ | Enabled<br>Set<br>Disabled<br>Enabled | 1<br>1<br>0<br>1 |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | enable interrupt for event READ |  |  |  |  |  |
| E RW | DMARXEND | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | enable interrupt for event DMARXEND |  |  |  |  |  |
| F RW | DMARXREADY | Set<br>Disabled | 1<br>0 |  | Write '1' to<br>Enable<br>Read: Disabled | enable interrupt for event DMARXREADY |  |  |  |  |  |

![]({{img:images/e3b0c83d26c9aa9fac04717307c43594ceddd4314e14a8299100177344972eb1.jpg}})

| Bit number |  |  | 31 30 29 28 27 26 25 24 23 | 22 |  |  | 21 20 19 18 | 16 15 14 | 13 12 | 11 10 9 | 8 7 6 5 4 3 2 |  | 1 | 0 |
| ------------------ | ------------------ | ------------------------ | ------------------------------ | ------- | ---- | ----- | ------------------------------ | ---------------------------- | ----------------------- | --------------- | ----------------- | ----------- | -------- | ----- |
| ID |  |  |  |  | M | L K | J I H G F | D C |  |  | B |  | A |  |
| Reset 0x00000000 | Reset 0x00000000 |  | 0 | 0 | 0 | 0 0 | 0 0 0 0 0 | 0 0 0 | 0 0 | 0 0 0 | 0 0 0 | 0 0 0 | 0 | 0 0 |
| ID | R/W | Field Value | ID | Value |  |  | Description |  |  |  |  |  |  |  |
| G | RW | DMARXBUSERROR | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write '1' to<br>When this event read from the<br>Enable<br>Read: Disabled<br>Read: Enabled | interrupt for<br>generated, BUSERRORADDRESS | event<br>the address register. | DMARXBUSERROR<br>which | the | error can | be |  |
| H-K | RW | DMARXMATCH[i] (i=0..3) | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | interrupt for | event | DMARXMATCH[i] |  |  |  |  |
| L | RW | DMATXEND | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | interrupt for | event | DMATXEND |  |  |  |  |
| M | RW | DMATXREADY | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | interrupt | for event | DMATXREADY |  |  |  |  |
| N | RW | DMATXBUSERROR | Set<br>Disabled<br>Enabled | 1<br>0<br>1 |  |  | Write '1' to<br>When this<br>read from the<br>Enable<br>Read: Disabled<br>Read: Enabled | interrupt<br>generated,<br>BUSERRORADDRESS | for event<br>the address | DMATXBUSERROR<br>which<br>register. | the | error | can be |  |
## 8.24.10.26 INTENCLR

Address offset: 0x308

Disable interrupt

![]({{img:images/a6e5567febda3b0942c9d065c153d724a390971003e18aaa9a209407be1d2c89.jpg}})

| Bit number |
| -------------- |

![]({{img:images/62a0c62ea0856973d4c4d6d53cb391b984f0e46c6744364b73d1167255867de4.jpg}})

| Bit ID |  |  | number | 31 30 29 28 N | 24 23 22 21 | 20 19 18 17 16 15 14 13 C | 5 4 B | 2 1 A | 0 |
| ---------- | ------------------ | ---------- | ---------- | ----------------- | --------------- | ------------------------------ | ----------- | --------- | ----- |
|  |  |  |  | 0 0 | J I | H G F E D |  |  |  |
| ID | R/W Field | Enabled | Value ID<br>1 | Value | Description<br>Read: | Enabled |  |  |  |
| E | RW DMARXEND | Clear<br>Disabled<br>Enabled | 1<br>1 | 0 | Write<br>Disable<br>Read:<br>Read: | '1' to disable interrupt for event<br>Disabled<br>Enabled |  |  |  |
| F | RW DMARXREADY | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable interrupt for event<br>Disabled<br>Enabled |  |  |  |
| G | RW DMARXBUSERROR | Clear<br>Disabled | 1 | 0 | Write<br>When<br>read<br>Disable<br>Read: | '1' to disable interrupt for event<br>generated, the<br>BUSERRORADDRESS<br>Disabled | the error | can be |  |
| H-K | RW DMARXMATCH[i] | (i=0..3)<br>Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable interrupt for event<br>Disabled<br>Enabled |  |  |  |
| L | RW DMATXEND | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable interrupt for event<br>Disabled<br>Enabled |  |  |  |
| M | RW DMATXREADY | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 |  | Write<br>Disable<br>Read:<br>Read: | '1' to disable interrupt for event<br>Disabled<br>Enabled |  |  |  |
| N | RW DMATXBUSERROR | Clear<br>Disabled<br>Enabled | 1<br>1 | 0 | Write<br>When read<br>Disable<br>Read:<br>Read: | '1' to disable interrupt for event<br>generated,<br>the BUSERRORADDRESS<br>Disabled<br>Enabled | the error | can be |  |
## 8.24.10.27 ERRORSRC

Address offset: 0x4D0

Error source

![]({{img:images/7aa5319a9c39b1f3771744a681c9cc5e89d3490144955abc2cc72e7944fd05f4.jpg}})

![]({{img:images/f317bbd0fd414e8a9b8fa15b9c901348422a488376a2894df5740d95fa3ea5f0.jpg}})

## 8.24.10.28 MATCH

Address offset: 0x4D4

Status register indicating which address had a match

![]({{img:images/0bf1de2b07e4e6d2a419026c29a28f12f5c65135ef91754300eda78874d50a2a.jpg}})

## 8.24.10.29 ENABLE

Address offset: 0x500

Enable TWIS

![]({{img:images/dce113327901e10f39dd7633e5168f2f527b52a2c79477faeac2d3c476c03c36.jpg}})

## 8.24.10.30 ADDRESS[n] (n=0..1)

Address offset: 0x588 + (n × 0x4)

TWI slave address n

![]({{img:images/8c688ef068dde79fa79d8e83253f2a63bd510221b7ec1aecc931fbf2277611ef.jpg}})

![]({{img:images/6b3e0a250ae5b9304ef3a134429e8ec2625b4911ff88d3b696f0285f1868e08d.jpg}})

## 8.24.10.31 CONFIG

Address offset: 0x594

Configuration register for the address match mechanism

![]({{img:images/f16b4868e3ed401241d2d007041a648a8ba3498fea6a81793b4fc03b9c7cbfa5.jpg}})

## 8.24.10.32 ORC

Address offset: 0x5C0

Over-read character. Character sent out in case of an over-read of the transmit buffer.

![]({{img:images/15c48c91238a98d48d0f65b9d17ac56a025edf9471355b46109fd9be73aee76e.jpg}})

## 8.24.10.33 PSEL.SCL

Address offset: 0x600

Pin select for SCL signal

![]({{img:images/afcba123f9e090ecf27cfbfe56d56cc98ec0c6b42818c206ec84e8bfb4fcc63e.jpg}})

## 8.24.10.34 PSEL.SDA

Address offset: 0x604

Pin select for SDA signal

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/d7252deee96148d00ee6ffbbec9076612be7f3c4a8f35e2801c046ff5fc2d23c.jpg}})

## 8.24.10.35 DMA.RX.PTR

Address offset: 0x704

RAM buffer start address

![]({{img:images/b2926c1bb01b6835c64a84ac1c67118d11955d792164562aac49892b36bc2729.jpg}})

## 8.24.10.36 DMA.RX.MAXCNT

Address offset: 0x708

Maximum number of bytes in channel buffer

![]({{img:images/2a02156244a47f1af91860fa2192c7dd51b09f01c3ab0f6a5782b8f4bdac65a3.jpg}})

## 8.24.10.37 DMA.RX.AMOUNT

Address offset: 0x70C

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/44a1d14d12ec3124e62376cd835e8a44caee8e80ca77bb13e9a5af48b86ad271.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.24.10.38 DMA.RX.TERMINATEONBUSERROR

Address offset: 0x71C

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/ce3a6b7c02384e6d26b8b1199d9781e19d106c02e2ba353785f10a57b59ce470.jpg}})

## 8.24.10.39 DMA.RX.BUSERRORADDRESS

Address offset: 0x720

Address of transaction that generated the last BUSERROR event.

![]({{img:images/4d9d490b4a3844b476ee635ed3aafe93637b0488255c9ebeb0cc719ffe61da52.jpg}})

## 8.24.10.40 DMA.RX.MATCH

Registers to control the behavior of the pattern matcher engine

## 8.24.10.40.1 DMA.RX.MATCH.CONFIG

Address offset: 0x724

Configure individual match events

![]({{img:images/fed34b455ef536368a47808579e815fe4d2e345b1f77f27a14c815e84ec0672e.jpg}})

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.24.10.40.2 DMA.RX.MATCH.CANDIDATE[n] (n=0..3)

Address offset: 0x728 + (n × 0x4)

The data to look for - any match will trigger the MATCH[n] event, if enabled.

Note: This register can be updated while a transfer is in progress, but the new value will not take effect until a match has been found or the transfer is done. That makes it possible to write a new set of match words which will be searched for immediately after the event triggers.

![]({{img:images/0b4715e2bb9bbc396140e2cba930e7c9931472455a556beac525aa5c4f1b413b.jpg}})

## 8.24.10.41 DMA.TX.PTR

Address offset: 0x73C

RAM buffer start address

![]({{img:images/c91c987f130a732809ae40b6f012c092d41b61125f4c3222a8ed8eb81e213335.jpg}})

## 8.24.10.42 DMA.TX.MAXCNT

Address offset: 0x740

Maximum number of bytes in channel buffer

![]({{img:images/98db58c17b38b9094c4354b924ce42be846c6fad712a55f8dcf2c6e5d26e8d03.jpg}})

## 8.24.10.43 DMA.TX.AMOUNT

Address offset: 0x744

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

![]({{img:images/f8b05de56c6566930c4659c2d2563b4529192d28eb2194c2b4f4f11e9e49ff6c.jpg}})

## 8.24.10.44 DMA.TX.TERMINATEONBUSERROR

Address offset: 0x754

Terminate the transaction if a BUSERROR event is detected.

![]({{img:images/66f40d1a27fe08b7750e45fbe753d2ac390f2924acebc0e67455ea7c645bce3e.jpg}})

## 8.24.10.45 DMA.TX.BUSERRORADDRESS

Address offset: 0x758

Address of transaction that generated the last BUSERROR event.

![]({{img:images/2c172066d5b554c35e009f4198768052e0b1ab4eff841d4fb5bc1fe5343c624a.jpg}})

## 8.25 UARTE - Universal asynchronous receiver/ transmitter with EasyDMA

The Universal asynchronous receiver/transmitter with EasyDMA peripheral (UARTE) provides a full-duplex, asynchronous serial communication interface with hardware flow control.

The main features of UARTE are the following:

- Full-duplex operation
- EasyDMA direct transfer to and from RAM
- Individual selection of I/O pins
- Slow instances with up to 1 Mbps baud rate
- Optional even and odd parity bit checking and generation
- One or two stop bits
- Configurable data frame size: 4 bit to 9 bit
- 9-bit mode support with address matching in RX
- Automatic hardware flow control
- Supports return to the IDLE state between transactions (when using HW flow control)
- Interrupt generation after programmable timeout

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

- Compare match filter for generating events or interrupts

Figure 157: UARTE configuration

![]({{img:images/3ac9d69465dcfeabc07d4f4a8699ba381dadd2d44ef178f1576cfdfd5d676ffe.jpg}})

Note: The external crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication. See CLOCK - Clock control on page 71 for more information.

## 8.25.1 Baudrate

The UART baudrate defines the speed at which data is transmitted over the UART interface, measured in bits per second (bps).

The BAUDRATE register lists a set of precalculated values for the most common baudrates and 16 MHz PCLK. For the high speed instances (PCLK > 16 MHz), the baudrate is calculated as follows:

Figure 158: UARTE baudrate

- BAUDRATE is the value to be used in the UARTE BAUDRATE register.
- f\_PCLK is the peripheral clock frequency for the UARTE instance, as defined in Instances on page 701.
- desired\_baudrate is the desired baudrate in bits per second, such as 9600 or 115200.

## 8.25.2 EasyDMA

UARTE implements EasyDMA for reading and writing to and from RAM.

If the DMA.TX.PTR and the DMA.RX.PTR are not pointing to the RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 14 for more information about each memory region.

The DMA.RX.PTR, DMA.TX.PTR, DMA.RX.MAXCNT, and DMA.TX.MAXCNT registers are double-buffered. They can be updated and prepared for the next reception or transmission immediately after having received the DMA.RX.READY or DMA.TX.READY events.

The DMA.RX.END and DMA.TX.END events indicate that the EasyDMA is finished accessing the RX or TX buffer in RAM.

For detailed information regarding the use of EasyDMA, see EasyDMA on page 28.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.25.3 Transmission

The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This is achieved by writing the initial address pointer to DMA.TX.PTR, and the number of bytes to transmit from the RAM buffer to DMA.TX.MAXCNT. The UARTE transmission is started by triggering the DMA.TX.START task.

After each byte has been sent over the TXD line, a TXDRDY event is generated.

When then bytes have been transmitted, the DMA.TX.END event is generated.

A UARTE transmission sequence is stopped by triggering the DMA.TX.STOP task. A TXSTOPPED event will be generated when the UARTE transmitter has stopped.

If the DMA.TX.END event has not been generated when the UARTE transmitter stops, UARTE will generate the DMA.TX.END event explicitly even though all bytes specified in the DMA.TX.MAXCNT register have not been transmitted.

If flow control is enabled in the HWFC field in the CONFIG register, a transmission will be automatically suspended when CTS is deactivated, and resumed when CTS is activated again, as shown in the following figure. A byte that is in transmission when CTS is deactivated will finish transmitting before the transmission is suspended.

Figure 159: UARTE transmission

![]({{img:images/c1a44e10a01ba6250eba424cb6fec204fe163c5f70e11ec3d1a72253114d5635.jpg}})

The UARTE transmitter is least active when it is stopped, consuming the least amount of energy. This is before it is started via DMA.TX.START, or after it has been stopped via DMA.TX.STOP and the TXSTOPPED event has been generated. See POWER - Power control on page 92 for more information about power modes.

## 8.25.4 Reception

The UARTE receiver is started by triggering the DMA.RX.START task. The UARTE receiver uses EasyDMA to store incoming data in an RX buffer in RAM.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

The RX buffer is located at the address specified in the DMA.RX.PTR register. The DMA.RX.PTR register is double-buffered and can be updated and prepared for the next DMA.RX.START task immediately after the EVENTS\_DMA.RX.READY event is generated. The size of the RX buffer is specified in the DMA.RX.MAXCNT register. UARTE generates an DMA.RX.END event when it has filled up the RX buffer, as seen in the following figure.

For each byte received over the RXD line, an RXDRDY event is generated. This event is likely to occur before the corresponding data has been transferred to RAM.

The DMA.RX.AMOUNT register can be queried following an DMA.RX.END event to see how many new bytes have been transferred to the RX buffer in RAM since the previous DMA.RX.END event.

Figure 160: UARTE reception

![]({{img:images/0eacdfe6dbcb3d32ab434890eaabd9bf2948750e3cb66f1dd1cf2481a8ad2a39.jpg}})

The UARTE receiver is stopped by triggering the DMA.RX.STOP task. An RXTO event is generated when UARTE has stopped. UARTE makes sure that an impending DMA.RX.END event is generated before the RXTO event is generated. This means that UARTE guarantees that no DMA.RX.END event is generated after RXTO, unless UARTE is restarted or a FLUSHRX command is issued after the RXTO event is generated.

**Figure 160: UARTE reception**

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Note: If the DMA.RX.END event has not been generated when the UARTE receiver stops, indicating that all pending content in the RX FIFO has been moved to the RX buffer, UARTE generates the DMA.RX.END event explicitly even though the RX buffer is not full. In this scenario, the DMA.RX.END event is generated before the RXTO event is generated.

To determine the amount of bytes the RX buffer has received, the CPU can read the DMA.RX.AMOUNT register following the DMA.RX.END event or the RXTO event.

If sent in succession immediately after the RTS signal is deactivated, UARTE can receive up to four bytes after the DMA.RX.STOP task has been triggered.

After the RXTO event is generated, the internal RX FIFO can still contain data. To move this data to RAM, the FLUSHRX task must be triggered. The RX buffer must be emptied, or the DMA.RX.PTR register must be updated before the FLUSHRX task is triggered. This ensures the data in the RX buffer is not overwritten. To make sure that all data in the RX FIFO is moved to the RX buffer, the DMA.RX.MAXCNT register must be set to DMA.RX.MAXCNT > 4, as seen in the following figure. The UARTE will generate the EVENTS\_DMA.RX.END event after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not fill up. After the DMA.RX.END event, the DMA.RX.AMOUNT register holds the actual amount of bytes transferred to the RX buffer.

Figure 161: UARTE reception with forced stop through DMA.RX.STOP

![]({{img:images/63b532a932f407f939b182690c8046aa783fd9def37400662aa2507d910b32dc.jpg}})

If hardware flow control is enabled in the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped via the DMA.RX.STOP task, or when UARTE can only receive four more bytes in its internal RX FIFO.

With flow control disabled, the UARTE will function in the same way as when the flow control is enabled, except that the RTS line will not be used. This means that no signal will be generated when UARTE is only able to receive four additional bytes in its internal RX FIFO. Data received when the internal RX FIFO is full, will be lost.

The UARTE receiver is least active when it is stopped, consuming the least amount of energy. This is before it is started via DMA.RX.START, or after it has been stopped via DMA.RX.STOP and the RXTO event has been generated. See POWER - Power control on page 92 for more information about power modes.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

## 8.25.5 Data frame size

UARTE implements a configurable data frame size of 4 bits to 9 bits and is set in the register CONFIG on page 723. If a value greater than 9 or less than 4 is written to this register, the frame size will be set to 8 bits and the register will read back a value of 8.

When UARTE is used with the 9 bit frame size, a 9th bit is added after the MSB of the 8 bit data frame, and before the parity and stop bits, as shown in the following figure. This bit indicates if the 8 bit data is an address or data. If the 9th bit is 1 , the 8 bit data is interpreted as an address. If the 9th bit is 0 , the 8 bit data is interpreted as data.

Figure 162: UARTE frame

![]({{img:images/a94174eeca2d8742556b2d745397ce3794f1ff4b4fece740d7af4500cf9b0664.jpg}})

| 1 start bit | Data frame: 4 to 8 data bits | 0 to 1 address bits | 0 to 1 parity bits | 1 to 2 stop bits |
| --------------- | ------------------------------ | ----------------------- | ---------------------- | -------------------- |

When UART is in RX configured with a 9 bit frame size, all frames are ignored until a frame with the address bit set is received, and the 8 remaining bits of the data frame matches the address set in the register ADDRESS on page 723. The frames following the matching address are received as an 8 bit data frame until the next frame where the address bit set is received, the address bit is not stored. If the address does not match ADDRESS, the following frames are ignored.

If the parity bit is enabled, the address bit is not included in the parity calculation.

When UART TX is started, the first byte in the buffer read by EasyDMA is treated as an address, and transmitted with the address bit set to 1 . The next bits in the buffer are treated as data and transmitted with the address bit set to 0 .

When UARTE uses a data frame size less than an 8 bits, the data is trimmed from an 8 bit frame size in the RAM buffer for TX, and padded before being stored in the RAM buffer for RX. The ENDIAN field in the register CONFIG defines if the data is trimmed from MSB or LSB of the 8 bit buffer frame.

## 8.25.6 Frame timeout interrupt

UARTE can generate an event after a programmable timeout.

If enabled with the FRAMETIMEOUT field in register CONFIG on page 723, a counter starts when the event EVENTS\_RXDRDY on page 708 is generated, and counts the number of periods given in register FRAMETIMEOUT on page 723. The period time of the counter is equal to the period of one bit on the UART TX line given by the baud rate set in BAUDRATE on page 722 If the task TASKS\_DMA.RX.STOP on page 704 is not triggered before the timeout expires, then the event EVENTS\_FRAMETIMEOUT is generated. The counter is reset when the event EVENTS\_RXDRDY on page 708 is generated. UARTE reception can be stopped on timeout by setting the short from the FRAMETIMEOUT event to the DMA.RX.STOP task in SHORTS on page 716.

This feature can be used to support variable length UART transmission with no end of transmission tag. After the last UART frames are received within the configured timeout, an interrupt is generated and the data can be processed.

The following figure shows an example where the UART receives a transmission with size of two frames, and the FRAMETIMEOUT register is set to 16.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Figure 163: UARTE reception frame timeout

![]({{img:images/16d47aafe8ce899e5dba23b5c0113e5637b5de16d1e82a157fb02d11be8bb662.jpg}})

The minimum value of the FRAMETIMEOUT register must be set to a value larger than the configured UART frame length.

## 8.25.7 Error conditions

An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. A framing error is always generated before a break condition occurs.

An ERROR event will not stop reception. If the error was a parity error, the received byte is still transferred into RAM along with any following bytes. If a framing error occurs (wrong stop bit), that byte will not be stored in RAM but the next incoming bytes will.

## 8.25.8 Using the UARTE without flow control

If flow control is not enabled, the interface will behave as if the CTS and RTS lines are held active.

## 8.25.9 Parity and stop bit configuration

Automatic even parity generation for both transmission and reception can be configured using the register CONFIG on page 723. If odd parity is required, it can be configured using the register CONFIG on page 723. See the register description for details.

The amount of stop bits can be configured in the register CONFIG on page 723.

## 8.25.10 Compare match filter

UARTE has a compare match filter that can watch for a specific sequence of data. This feature is implemented in EasyDMA on the RX channel.

UARTE can generate events or interrupts when the specific data sequence is received. The event EVENTS\_DMA.RX.MATCH[n] (n=0..3) on page 710 is generated when there is a match in the data stream being received. The number of MATCH can be different for each instance. See Registers on page 701 for how many MATCH events are implemented per instance.

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Register DMA.RX.MATCH.CANDIDATE[n] (n=0..3) on page 727 configures the pattern for comparison. The filter is enabled with the corresponding ENABLE bit in register DMA.RX.MATCH.CONFIG on page 726. The DMA.RX.ENABLEMATCH task can be used to set that bit, and the DMA.RX.DISABLEMATCH task will clear that bit. If the ONESHOT[i] field in the CONFIG register is set, the corresponding ENABLE[i] bit will be cleared on a successful match.

For detailed information regarding the use of pattern matching in the EasyDMA engine, see EasyDMA on page 28.

## 8.25.11 Low power

To ensure lowest possible power consumption when the peripheral is not needed, stop and disable UARTE.

The DMA.TX.STOP and DMA.RX.STOP tasks are not always needed (the peripheral might already be stopped). If DMA.TX.STOP or DMA.RX.STOP is sent, software waits until the TXSTOPPED or RXTO event is received before disabling the peripheral through the ENABLE register.

## 8.25.12 Pin configuration

The RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD signals associated with UARTE are mapped to physical pins according to the configuration specified in the PSEL.n registers.

These registers and their configurations are only used when UARTE is enabled, and retained while the device is in System ON mode. The PSEL.n registers can be configured only when UARTE is disabled.

To ensure correct behavior when in System OFF mode, the pins must be configured in the GPIO peripheral as described in the following table.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.

| UARTE signal | UARTE pin | Direction | Output value |
| ---------------- | -------------------------- | ------------- | ---------------- |
| RXD | As specified in PSEL.RXD | Input | Not applicable |
| CTS | As specified in PSEL.CTS | Input | Not applicable |
| RTS | As specified in PSEL.RTS | Output | 1 |
| TXD | As specified in PSEL.TXD | Output | 1 |

Table 68: GPIO configuration before enabling peripheral

![]({{img:images/1ab081c1e306bc48cd54aff8ccb2d05c726e2564c2adccd43c18c1a004f77645.jpg}})

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
NRF54L05	Nordic Semiconductor ASA	—
NRF54L10	Nordic Semiconductor ASA	—
NRF54L10-QFAA-R	Nordic Semiconductor ASA	QFN48 (6.0x6.0 mm)
NRF54L15	Nordic Semiconductor ASA	—
nRF54L15-QFAA	Nordic Semiconductor	QFN48 (6.0x6.0 mm)
NRF54L15/10/05	Nordic Semiconductor ASA	—

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