NRF52840-QFAA-F-R7

Part: nRF52840 by Nordic Semiconductor

Type: Wireless Microcontroller (MCU)

Description: A 32-bit Arm Cortex-M4 MCU with FPU running at 64 MHz, featuring 1 MB Flash, 256 kB RAM, Bluetooth 5, IEEE 802.15.4, and 2.4 GHz transceiver, operating from 1.7 V to 5.5 V.

Operating Conditions:

• Supply voltage: 1.7 V to 5.5 V
• Max CPU clock: 64 MHz
• Radio frequency: 2.4 GHz

Absolute Maximum Ratings:

Key Specs:

• CPU: Arm Cortex-M4 32-bit processor with FPU, 64 MHz
• Flash memory: 1 MB
• RAM: 256 kB
• Bluetooth 5 sensitivity: -103 dBm (125 kbps Bluetooth low energy mode)
• Bluetooth 5 TX power: -20 to +8 dBm, configurable
• GPIO pins: 48
• ADC: 12-bit, 200 ksps, 8 configurable channels
• USB: 2.0 full speed (12 Mbps) controller

Features:

• Bluetooth 5, IEEE 802.15.4-2006, 2.4 GHz transceiver
• Arm TrustZone CryptoCell 310 security subsystem
• Flexible power management with on-chip DC/DC and LDO regulators
• QSPI 32 MHz interface
• High-speed 32 MHz SPI
• Type 2 near field communication (NFC-A) tag with wake-on field
• Programmable peripheral interconnect (PPI)
• I2S, digital microphone interface (PDM)
• Up to four SPI masters/three SPI slaves with EasyDMA
• Up to two I2C compatible two-wire master/slave
• Two UART (CTS/RTS) with EasyDMA

Applications:

• Advanced computer peripherals and I/O devices
• Advanced wearable devices
• Internet of things (IoT)
• Interactive entertainment devices

Package:

• aQFN73 package, 7 x 7 mm
• QFN48 package, 6 x 6 mm
• WLCSP package, 3.544 x 3.607 mm

• Bluetooth ® 5, IEEE 802.15.4-2006, 2.4 GHz transceiver

  • -95 dBm sensitivity in 1 Mbps Bluetooth low energy mode
  • -103 dBm sensitivity in 125 kbps Bluetooth low energy mode (long range)
  • -20 to +8 dBm TX power, configurable in 4 dB steps
  • On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series devices
  • Supported data rates:
    • Bluetooth 5 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps
    • IEEE 802.15.4-2006 250 kbps
    • Proprietary 2.4 GHz 2 Mbps, 1 Mbps
  • Single-ended antenna output (on-chip balun)
  • 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption)
  • 4.8 mA peak current in TX (0 dBm)
  • 4.6 mA peak current in RX
  • RSSI (1 dB resolution)

• Arm Cortex -M4 32-bit processor with FPU, 64 MHz

  • 212 EEMBC CoreMark score running from flash memory
  • 52 μA/MHz running CoreMark from flash memory
  • Watchpoint and trace debug modules (DWT, ETM, and ITM)
  • Serial wire debug (SWD)

• Rich set of security features

  • Arm TrustZone ® CryptoCell ™ 310 security subsystem
    • NIST SP800-90A and SP800-90B compliant random number generator
    • AES-128 ECB, CBC, CMAC/CBC-MAC, CTR, CCM/CCM*
    • Chacha20/Poly1305 AEAD supporting 128- and 256-bit key size
    • SHA-1 and SHA-2 up to 256 bit
    • Keyed-hash message authentication code (HMAC)
    • RSA up to 2048-bit key size
    • SRP up to 3072-bit key size
    • ECC support for most used curves, including P-256 (secp256r1) and Ed25519/Curve25519
    • Application key management using derived key model
  • Secure boot ready
    • Flash access control list (ACL)
    • Root-of-trust (RoT)
    • Debug control and configuration
    • Access port protection (CTRL-AP)
  • Secure erase

• Flexible power management

  • 1.7 V to 5.5 V supply voltage range
  • On-chip DC/DC and LDO regulators with automated low current modes
  • 1.8 V to 3.3 V regulated supply for external components
  • Automated peripheral power management
  • Fast wake-up using 64 MHz internal oscillator
  • 0.4 μA at 3 V in System OFF mode, no RAM retention
  • 1.5 μA at 3 V in System ON mode, no RAM retention, wake on RTC

• 1 MB flash and 256 kB RAM

• Advanced on-chip interfaces

  • USB 2.0 full speed (12 Mbps) controller
  • QSPI 32 MHz interface
  • High-speed 32 MHz SPI
  • Type 2 near field communication (NFC-A) tag with wake-on field
    • Touch-to-pair support
  • Programmable peripheral interconnect (PPI)
  • 48 general purpose I/O pins
  • EasyDMA automated data transfer between memory and peripherals

• Nordic SoftDevice ready with support for concurrent multiprotocol

• 12-bit, 200 ksps ADC 8 configurable channels with programmable gain

• 64 level comparator

• 15 level low-power comparator with wake-up from System OFF mode

• Temperature sensor

• Four 4 channel pulse width modulator (PWM) units with EasyDMA

• Audio peripherals I² S, digital microphone interface (PDM)

• Five 32-bit timers with counter mode

• Up to four SPI masters/three SPI slaves with EasyDMA

• Up to two I² C compatible two-wire master/slave

• Two UART (CTS/RTS) with EasyDMA

• Quadrature decoder (QDEC)

• Three real-time counters (RTC)

• Single crystal operation

• Package variants

  • aQFN73 ™ package, 7 x 7 mm
  • QFN48 package, 6 x 6 mm
  • WLCSP package, 3.544 x 3.607 mm

4413_417 v1.11 ii

• Advanced computer peripherals and I/O devices

  • Mouse
  • Keyboard
  • Multi-touch trackpad

• Advanced wearable devices

  • Health/fitness sensors and monitoring devices
  • Wireless payment enabled devices

• Internet of things (IoT)

  • Smart home sensors and controllers
  • Industrial IoT sensors and controllers

• Interactive entertainment devices

  • Remote controls
  • Gaming controllers

4413_417 v1.11 iii

Pins can be individually configured through the SENSE field in the PIN_CNF[n] register to detect either a high or low level input.

When the correct level is detected on a configured pin, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register, combines all DETECT signals from the pins in the GPIO port into one common DETECT signal and routes it through the system to be utilized by other peripherals. This mechanism is functional in both System ON and System OFF mode. See GPIO port and the GPIO pin details on page 323.

The following figure illustrates the GPIO port containing 32 individual pins, where PIN0 is shown in more detail for reference. All signals on the left side of the illustration are used by other peripherals in the system and therefore not directly available to the CPU.

Figure 49: GPIO port and the GPIO pin details

Pins should be in a level that cannot trigger the sense mechanism before being enabled. If the SENSE condition configured in the PIN_CNF registers is met when the sense mechanism is enabled, the DETECT signal will immediately go high. A PORT event is triggered if the DETECT signal was low before enabling the sense mechanism. See GPIOTE — GPIO tasks and events on page 371.

See the following peripherals for more information about how the DETECT signal is used:

• POWER Power supply on page 81 uses the DETECT signal to exit from System OFF mode.
• GPIOTE GPIO tasks and events on page 371 uses the DETECT signal to generate the PORT event.

When a pin's PINx.DETECT signal goes high, a flag is set in the LATCH register. For example, when the PIN0.DETECT signal goes high, bit 0 in the LATCH register is set to 1. If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by writing a 1 to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low.

The LDETECT signal will be set high when one or more bits in the LATCH register are 1. The LDETECT signal will be set low when all bits in the LATCH register are successfully cleared to 0.

If one or more bits in the LATCH register are 1 after the CPU has performed a clear operation on the LATCH register, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior on page 324.

Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been met on any of the GPIO pins. This is still valid if that condition is no longer met at the time the CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the DETECT signal.

The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE register. It is possible to change from default behavior to the DETECT signal that is derived directly from the LDETECT signal. See GPIO port and the GPIO pin details on page 323. The following figure illustrates the DETECT signal behavior for these two alternatives.

Figure 50: DETECT signal behavior

A GPIO pin input buffer can be disconnected from the pin to enable power savings when the pin is not used as an input, see GPIO port and the GPIO pin details on page 323. Input buffers must be connected to get a valid input value in the IN register, and for the sense mechanism to get access to the pin.

Other peripherals in the system can connect to GPIO pins and override their output value and configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page 323.

Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page 323. The assignment of the analog pins can be found in Pin assignments on page 926.

Note: When a pin is configured as digital input, increased current consumption occurs when the input voltage is between VIL and VIH. It is good practice to ensure that the external circuitry does not drive that pin to levels between VIL and VIH for a long period of time.

uint8_t sample_ed(void) { int val; NRF_RADIO->TASKS_EDSTART = 1; // Start while (NRF_RADIO->EVENTS_EDEND != 1) { // CPU can sleep here or do something else // Use of interrupts are encouraged } val = NRF_RADIO->EDSAMPLE; // Read level return (uint8_t)(val>63 ? 255 : val*ED_RSSISCALE); // Convert to IEEE 802.15.4 scale }

For scaling between hardware value and dBm, see [Conversion between hardware value and dBm](#page-611-0) on page 612.

It is the mlme-scan.req primitive of the MAC layer that is using the ED measurement to detect channels where there might be wireless activity. To assist this primitive a taylored mode of operation is available where the ED measurement runs for a defined number of iterations where it keeps track of the maximum ED level. This is enganged by writing the EDCNT register to a value different from 0, it will then run the specified number of iterations reporting the maximum energy measurement in the EDSAMPLE register. The scan is started with EDSTART task and its end indicated with the EDEND event. This greatly reduces the interrupt frequency and hence power consumtion. The figure below shows how the ED measurement will operate depending on the EDCNT register.