NRF52810-QFAA-R
The NRF52810-QFAA-R is an electronic component from Nordic Semiconductor ASA. View the full NRF52810-QFAA-R datasheet below including key specifications, electrical characteristics.
Manufacturer
Nordic Semiconductor ASA
Category
RF and Wireless
Package
48-VFQFN Exposed Pad
Lifecycle
Active
Key Specifications
| Parameter | Value |
|---|---|
| Current - Receiving | 4.6mA |
| Current - Transmitting | 4.6mA ~ 25mA |
| Data Rate (Max) | 2Mbps |
| DigiKey Programmable | Not Verified |
| Frequency | 2.4GHz |
| GPIO | 32 |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C |
| Package / Case | 48-VFQFN Exposed Pad |
| Packaging | Cut Tape |
| Packaging | Cut Tape |
| Power - Output | 4dBm |
| Protocol | Bluetooth v5.0 |
| RF Family/Standard | Bluetooth |
| Sensitivity | -96dBm |
| Serial Interfaces | I2C, UART |
| Standard Pack Qty | 3000 |
| Standard Pack Qty | 3000 |
| Supplier Device Package | 48-QFN (6x6) |
| Type | TxRx + MCU |
| Supply Voltage | 1.7V ~ 3.6V |
Overview
Part: nRF52840
Type: Bluetooth 5, IEEE 802.15.4, 2.4 GHz SoC with ARM Cortex-M4F MCU
Description: A Bluetooth 5, IEEE 802.15.4, 2.4 GHz SoC featuring an Arm Cortex-M4 32-bit processor with FPU at 64 MHz, 1 MB flash, 256 kB RAM, and a 1.7 V to 5.5 V supply voltage range.
Operating Conditions:
- Supply voltage: 1.7 V to 5.5 V
- Max CPU clock: 64 MHz
- TX power range: -20 to +8 dBm
Key Specs:
- CPU: Arm Cortex-M4 32-bit processor with FPU, 64 MHz
- Flash memory: 1 MB
- RAM: 256 kB
- Bluetooth low energy sensitivity (1 Mbps): -95 dBm
- Bluetooth low energy sensitivity (125 kbps): -103 dBm
- Peak current in TX (0 dBm): 4.8 mA
- Peak current in RX: 4.6 mA
- System OFF mode current (no RAM retention): 0.4 μA at 3 V
- General purpose I/O pins: 48
Features:
- Bluetooth 5, IEEE 802.15.4-2006, 2.4 GHz transceiver
- Arm TrustZone CryptoCell 310 security subsystem
- USB 2.0 full speed (12 Mbps) controller
- Type 2 near field communication (NFC-A) tag with wake-on field
- 12-bit, 200 ksps ADC - 8 configurable channels with programmable gain
- Flexible power management with on-chip DC/DC and LDO regulators
Applications:
- Advanced computer peripherals and I/O devices
- Advanced wearable devices
- Internet of things (IoT)
- Interactive entertainment devices
Package:
- aQFN73 package, 7 x 7 mm
- QFN48 package, 6 x 6 mm
- WLCSP package, 3.544 x 3.607 mm
Features
- Bluetooth ® 5, IEEE 802.15.4-2006, 2.4 GHz transceiver
- -95 dBm sensitivity in 1 Mbps Bluetooth low energy mode
- -103 dBm sensitivity in 125 kbps Bluetooth low energy mode (long range)
- -20 to +8 dBm TX power, configurable in 4 dB steps
- On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series devices
- Supported data rates:
- Bluetooth 5 - 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps
- IEEE 802.15.4-2006 - 250 kbps
- Proprietary 2.4 GHz - 2 Mbps, 1 Mbps
- Single-ended antenna output (on-chip balun)
- 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption)
- 4.8 mA peak current in TX (0 dBm)
- 4.6 mA peak current in RX
- RSSI (1 dB resolution)
- Arm ® Cortex ® -M4 32-bit processor with FPU, 64 MHz
- 212 EEMBC CoreMark ® score running from flash memory
- 52 μA/MHz running CoreMark from flash memory
- Watchpoint and trace debug modules (DWT, ETM, and ITM)
- Serial wire debug (SWD)
- Rich set of security features
- Arm TrustZone ® CryptoCell ™ 310 security subsystem
- NIST SP800-90A and SP800-90B compliant random number generator
- AES-128 - ECB, CBC, CMAC/CBC-MAC, CTR, CCM/CCM*
- Chacha20/Poly1305 AEAD supporting 128- and 256-bit key size
- SHA-1 and SHA-2 up to 256 bit
- Keyed-hash message authentication code (HMAC)
- RSA up to 2048-bit key size
- SRP up to 3072-bit key size
- ECC support for most used curves, including P-256 (secp256r1) and Ed25519/Curve25519
- Application key management using derived key model
- Secure boot ready
- Flash access control list (ACL)
- Root-of-trust (RoT)
- Debug control and configuration
- Access port protection (CTRL-AP)
- Secure erase
- Flexible power management
- 1.7 V to 5.5 V supply voltage range
- On-chip DC/DC and LDO regulators with automated low current modes
- 1.8 V to 3.3 V regulated supply for external components
- Automated peripheral power management
- Fast wake-up using 64 MHz internal oscillator
- 0.4 μA at 3 V in System OFF mode, no RAM retention
- 1.5 μA at 3 V in System ON mode, no RAM retention, wake on RTC
- 1 MB flash and 256 kB RAM
- Advanced on-chip interfaces
- USB 2.0 full speed (12 Mbps) controller
- QSPI 32 MHz interface
- High-speed 32 MHz SPI
- Type 2 near field communication (NFC-A) tag with wake-on field
- Touch-to-pair support
- Programmable peripheral interconnect (PPI)
- 48 general purpose I/O pins
- EasyDMA automated data transfer between memory and peripherals
- Nordic SoftDevice ready with support for concurrent multiprotocol
- 12-bit, 200 ksps ADC - 8 configurable channels with programmable gain
- 64 level comparator
- 15 level low-power comparator with wake-up from System OFF mode
- Temperature sensor
- Four 4 channel pulse width modulator (PWM) units with EasyDMA
- Audio peripherals - I 2 S, digital microphone interface (PDM)
- Five 32-bit timers with counter mode
- Up to four SPI masters/three SPI slaves with EasyDMA
- Up to two I 2 C compatible two-wire master/slave
- Two UART (CTS/RTS) with EasyDMA
- Quadrature decoder (QDEC)
- Three real-time counters (RTC)
- Single crystal operation
- Package variants
- aQFN73 ™ package, 7 x 7 mm
- QFN48 package, 6 x 6 mm
- WLCSP package, 3.544 x 3.607 mm
Applications
- Advanced computer peripherals and I/O devices
- Mouse
- Keyboard
- Multi-touch trackpad
- Advanced wearable devices
- Health/fitness sensors and monitoring devices
- Wireless payment enabled devices
- Internet of things (IoT)
- Smart home sensors and controllers
- Industrial IoT sensors and controllers
- Interactive entertainment devices
- Remote controls
- Gaming controllers
Pin Configuration
Pins can be individually configured through the SENSE field in the PIN_CNF[n] register to detect either a high or low level input.
When the correct level is detected on a configured pin, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register, combines all DETECT signals from the pins in the GPIO port into one common DETECT signal and routes it through the system to be utilized by other peripherals. This mechanism is functional in both System ON and System OFF mode. See GPIO port and the GPIO pin details on page 323.
The following figure illustrates the GPIO port containing 32 individual pins, where PIN0 is shown in more detail for reference. All signals on the left side of the illustration are used by other peripherals in the system and therefore not directly available to the CPU.
Figure 49: GPIO port and the GPIO pin details
Pins should be in a level that cannot trigger the sense mechanism before being enabled. If the SENSE condition configured in the PIN_CNF registers is met when the sense mechanism is enabled, the DETECT signal will immediately go high. A PORT event is triggered if the DETECT signal was low before enabling the sense mechanism. See GPIOTE - GPIO tasks and events on page 371.
See the following peripherals for more information about how the DETECT signal is used:
- POWER - Power supply on page 81 - uses the DETECT signal to exit from System OFF mode.
- GPIOTE - GPIO tasks and events on page 371 - uses the DETECT signal to generate the PORT event.
When a pin's PINx.DETECT signal goes high, a flag is set in the LATCH register. For example, when the PIN0.DETECT signal goes high, bit 0 in the LATCH register is set to 1 . If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by writing a 1 to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low.
The LDETECT signal will be set high when one or more bits in the LATCH register are 1 . The LDETECT signal will be set low when all bits in the LATCH register are successfully cleared to 0 .
If one or more bits in the LATCH register are 1 after the CPU has performed a clear operation on the LATCH register, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior on page 324.
Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been met on any of the GPIO pins. This is still valid if that condition is no longer met at the time the CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the DETECT signal.
The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE register. It is possible to change from default behavior to the DETECT signal that is derived directly from the LDETECT signal. See GPIO port and the GPIO pin details on page 323. The following figure illustrates the DETECT signal behavior for these two alternatives.
Figure 50: DETECT signal behavior
A GPIO pin input buffer can be disconnected from the pin to enable power savings when the pin is not used as an input, see GPIO port and the GPIO pin details on page 323. Input buffers must be connected to get a valid input value in the IN register, and for the sense mechanism to get access to the pin.
Other peripherals in the system can connect to GPIO pins and override their output value and configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page 323.
Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page 323. The assignment of the analog pins can be found in Pin assignments on page 926.
Note: When a pin is configured as digital input, increased current consumption occurs when the input voltage is between VIL and VIH. It is good practice to ensure that the external circuitry does not drive that pin to levels between VIL and VIH for a long period of time.
Electrical Characteristics
For scaling between hardware value and dBm, see Conversion between hardware value and dBm on page 612.
It is the mlme-scan.req primitive of the MAC layer that is using the ED measurement to detect channels where there might be wireless activity. To assist this primitive a taylored mode of operation is available where the ED measurement runs for a defined number of iterations where it keeps track of the maximum ED level. This is enganged by writing the EDCNT register to a value different from 0, it will then run the specified number of iterations reporting the maximum energy measurement in the EDSAMPLE register. The scan is started with EDSTART task and its end indicated with the EDEND event. This greatly reduces the interrupt frequency and hence power consumtion. The figure below shows how the ED measurement will operate depending on the EDCNT register.
Figure 127: Energy detection measurement examples
An ongoing scan can always be stopped by writing the EDSTOP task. It will be followed by the EDSTOPPED event when the module has terminated.
## 6.20.12.4 Clear channel assessment (CCA)
IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when transmitting - namely carrier sense multiple access with collision avoidance (CSMA-CA). The key part of this is measuring if the wireless medium is busy or not.
At least three methods must be supported:
- Mode 1 (energy above threshold): The medium is reported busy upon detecting any energy above the ED threshold
- Mode 2 (carrier sense only): The medium is reported busy upon detection of a signal compliant with the IEEE 802.15.4 standard with the same modulation and spreading characteristics
- Mode 3 (carrier sense and threshold): The medium is reported busy by logically ANDing or ORing the results from mode 1 and mode 2.
It is furthermore specified that the clear channel assessment should survey a period equal to 8 symbols or 128 μs.
The radio module has to be in receive mode and be able to recived correct packets when performing the CCA. The shortcut between READY and START must be disabled if baseband processing is not to be performed while the measurement is running.
Mode 1 is enabled by first configuring the field CCAMODE=EdMode in CCACTRL and writing the CCAEDTHRES field to a chosen value. When the CCASTART task is written the radio module will perform a ED measurement for 8 symbols and compare the measured level with that found in the CCAEDTHRES field. If the measured value is higher than or equal to this threshold the CCABUSY event is generated - the CCAIDLE event is generated if the measured level is less than the threshold.
The conversion from CCAEDTHRES, CCA or EDLEVEL value to dBm can be done with the following equation, where VALHARDWARE is the hardware-reported values, being either CCAEDTHRES, CCA or EDLEVEL, and constants ED\_RSSISCALE and ED\_RSSIOFFS are from electrical specifications:
PRF[dBm] = ED\_RSSIOFFS + ED\_RSSISCALE x VALHARDWARE
Figure 128: Conversion between hardware value and dBm
Mode 2 is enabled by configuring the CCAMODE=CarrierMode. In carrier mode the module will sample to see if a valid SFD is found during the 8 symbols. If a valid SFD is seen the CCABUSY event is generated and the node should not send any data. The CCABUSY event is also generated if the scan was performed during an ongoing frame reception. In the case where the measurement period completes with no SFD detection the CCAIDLE task is generated. With the CCA\_CORR\_COUNT unequal to zero the algorithm will look at the correlator output in addition to the SFD detection signal. If a SFD is reported during the scan period it will terminate immidiately indicating busy medium. Similarly, if the number of peaks above CCA\_CORRTHRES crosses the CCA\_CORR\_COUNT the CCABUSY event is generated. If less than CCA\_CORR\_COUNT crossings are found and no SFD is reported the CCAIDLE signal will be generated and it is ok for the node to commence sending data.
With the CCA\_MODE=CarrierAndEdMode or CCA\_MODE=CarrierOrEdMode a logical combination of the result from running both mode 1 and mode 2 is performed. The CCABUSY or CCAIDLE signal will be generated based on an ANDing or ORing of the internal signals from performing both the energy detection and carrier detection scans.
An ongoing CCA can always be stopped by issuing the CCASTOP task. This will trigger the associated CCASTOPPED event.
For CCA mode automation there are three shortcuts available. One is between CCAIDLE and TXEN. This short must always be used in conjunction with the short between CCAIDLE and STOP. This automation is provided so that the radio can automatically switch between RX (when performing the CCA) and to TX where the packet is sent. The last shortcut associated with the CCA mode is between CCABUSY and DISABLE. This will cause the radio to be disabled whenever the CCA reports a busy medium.
Another handy shortcut is between RXREADY and CCASTART. When the radio has ramped up into RX mode it can immidiately start a CCA.
## 6.20.12.5 Cyclic redundancy check (CRC)
IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MAC header (MHR) and MAC service data unit (MSDU).
The standard defines the following generator polynomial:
<!-- formula-not-decoded -->
In receive mode the radio will trigger the CRC module when the first octet after the frame length (PHR) is received. The CRC will then update on each consecutive octet received. When a complete frame is received the CRCSTATUS register will be updated accordingly and the EVENTS\_CRCOK or EVENTS\_CRCERROR generated. When the CRC module is enabled it will not write the two last octets (CRC) to the frame Data RAM. When transmitting the CRC will be computed on the fly, starting with the first octet after PHR, and inserted as the two last octets in the frame. The EasyDMA will fetch frame length - 2 octets from DataRAM and insert the CRC octets insitu.
Below is a code snippet for configuring the CRC module for correct operation when in IEEE 802.15.4 mode. The CRCCNF is written to 16-bit CRC and the CRCPOLY is written to 0x121. The start value used by IEEE 802.15.4 is zero and CRCINIT is configured to reflect this.
/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/ write_reg(NRFRADIO_REG(CRCCNF), 0x202); write_reg(NRFRADIO_REG(CRCPOLY), 0x11021); write_reg(NRFRADIO_REG(CRCINIT), 0);
The ENDIANESS subregister must be set to little-endian since the FCS field is transmitted leftmost bit first.
## 6.20.12.6 Transmit sequence
The transmission is started by first putting the radio in receive mode sending the RXEN task.
An outline of the IEEE 802.15.4 transmission is illustrated in the figure below.
Figure 129: IEEE 802.15.4 transmit sequence
The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving the ready event the CCA is started by writing to the CCASTART task register. The chosen mode of assessment (CCA\_MODE register) will be performed and signal the CCAIDLE or CCABUSY event 128 μs later. If the CCABUSY is received the radio will have to retry the CCA after a specific back off period as outlined in the IEEE 802.15.4 standard (see Figure 69 in section 7.5.1.4 The CSMA-CA algorithm of the standard).
When the CCAIDLE event on the other hand is generated the user shall write to the TXEN task register to enter the TXRU state. The READY event will be generated when the radio is in TXIDLE state and ready
to transmit. With the PACKETPTR pointing to the length (PHR) field of the frame the START task can be written. The radio will send the four octet preamble sequence followed by the start of frame delimiter (SFD register). The first byte read from the Data RAM is the length field (PHR) followed by the transmission of the number of bytes indicated as the frame length. If the CRC module is configured it will run for PHR-2 octets. The last two octets will be substituted with the results from running the CRC. The necessary CRC parameters are sampled on the START task. The FCS field of the frame is little endian.
In addition to the already available shortcuts, one is provided between READY event and CCASTART task so that a CCA can automatically start when the receiver is ready. And a second shortcut has been added between CCAIDLE event and the TXEN task so that upon detecting a clear channel the radio can immediately enter transmit mode.
## 6.20.12.7 Receive sequence
The reception is started by first putting the radio in receive mode. Writing to the RXEN task the radio will start ramping up and enter the RXRU state.
When the READY event is generated the radio has entered the RXIDLE mode. For the baseband processing to be enabled the START task must be written. An outline of the IEEE 802.15.4 reception can be found in figure below.
Figure 130: IEEE 802.15.4 receive sequence
When a valid SHR is received the radio will start storing future octets (starting with PHR) to the data memory pointed to by PACKETPTR. After the SFD octet is received the FRAMESTART event is generated. If the CRC module is enabled it will start updating with the second byte received (first byte in payload) and run for the full frame length. The two last bytes in the frame is not written to DataRAM when CRC is configured. However, if the result of the CRC after running the full frame is zero the CRCOK event will be generated. The END event is generated when the last octet has been received and is available in DataRAM.
When a packet is received a link quality indicator (LQI) is also generated and appended immediately after the last received octet. When using IEEE 802.15.4 compliant frame this will be just after the MSDU since the FCS is not reported. In the case of a non-complient frame it will be appended after the full frame. The LQI reported by hardware must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by 4, as shown in the code example for ED sampling. The LQI is only valid for frames equal to or longer than three octets. When receiving a frame the RSSI (reported as negative dB) will be measured at three points during the reception. These three values will be sorted and the middle one selected (median 3) for then to be remapped within the LQI range. The following figure illustrates the LQI measurement and how the data is arranged in the DataRAM:
On air frame
Figure 131: IEEE 802.15.4 frame in Data RAM
A shortcut has been added between FRAMESTART event and the BCSTART task. This can be used to trigger a BCMATCH event after N bits, such as when inspecting the MAC addressing fields.
## 6.20.12.8 Interframe spacing (IFS)
The IEEE 802.15.4 standard defines a specific time that is alotted for the MAC sublayer to process received data. Usage of this interframe spacing (IFS) comes into play to avoid that two frames are transmitted too close to eachother in time. If the a transmission is requesting an acknowledgement, the speration to the second frame shall be at least an IFS period.
The IFS is determined to be:
- IFS equals macMinSIFSPeriod (12 symbols) if the MPDU is less than or equal to aMaxSIFSFrameSize (18 octets) octets
- IFS equals macMinLIFSPeriod (40 symbols) if the MPDU is larger than aMaxSIFSFrameSize
Using the efficient assisted modes in the radio module the TIFS will be programmed with the correct value based on the frame being transmitted. If the assisted modes are not being used the user must update the TIFS register manually. The figure below provides details on what IFS period is valid in both acknowledged and unacknowledged transmissions.
Figure 132: Interframe spacing examples
## 6.20.13 EasyDMA
The RADIO uses EasyDMA for reading of data packets from and writing to RAM, without CPU involvement.
As illustrated in RADIO block diagram on page 600, the RADIO's EasyDMA utilizes the same PACKETPTR for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before RADIO is started by the START task. The PACKETPTR registers is double-buffered, meaning that it can be updated and prepared for the next transmission.
Important: If the PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 21 for more information about the different memory regions.
The END event indicates that the last bit has been processed by the radio. The DISABLED event is issued to acknowledge that a DISABLE task is done.
The structure of a radio packet is described in detail in Packet configuration on page 600. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:
- S0
- LENGTH
- S1
- PAYLOAD
In addition, a static add-on is sent immediately after the payload.
The size of each of the above fields in the frame is configurable (see Packet configuration on page 600), and the space occupied in RAM depends on these settings. A size of zero is possible for any of the fields, it is up to the user to make sure that the resulting frame complies with the RF protocol chosen.
All fields are extended in size to align with a byte boundary in RAM. For instance a 3 bit long field on air will occupy 1 byte in RAM while a 9 bit long field will be extended to 2 bytes.
The radio packets elements can be configured as follows:
- CI, TERM1 and TERM2 fields are only present in Bluetooth low energy long range mode
- S0 is configured through the S0LEN field in PCNF0
- LENGTH is configured through the LFLEN field in PCNF0
- S1 is configured through the S1LEN field in PCNF0
- Size of the payload is configured through the value in RAM corresponding to the LENGTH field
- Size of the static add-on to the payload is configured through the STATLEN field in PCNF1
The MAXLEN field in the PCNF1 register configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure that the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means
that if the packet payload length defined by PCNF1.STATLEN and the LENGTH field in the packet specifies a packet larger than MAXLEN, the payload will be truncated at MAXLEN.
Note: The MAXLEN includes the payload and the add-on, but excludes the size occupied by the S0, LENGTH and S1 fields. This has to be taken into account when allocating RAM.
If the payload and add-on length is specified larger than MAXLEN, the RADIO will still transmit or receive in the same way as before, except the payload is now truncated to MAXLEN. The packet's LENGTH field will not be altered when the payload is truncated. The RADIO will calculate CRC as if the packet length is equal to MAXLEN.
Note: If the PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 21 for more information about the different memory regions.
The END event indicates that the last bit has been processed by the radio. The DISABLED event is issued to acknowledge that an DISABLE task is done.
## 6.20.14 Registers
| Instance | Base address | Description |
| ------------ | ---------------- | --------------- |
| RADIO | 0x40001000 | 2.4 GHz radio |
| Register | Offset | Description |
| ----------------- | ---------- | ------------------------------ |
| TASKS_TXEN | 0x000 | Enable RADIO in TX mode |
| TASKS_RXEN | 0x004 | Enable RADIO in RX mode |
| TASKS_START | 0x008 | Start RADIO |
| TASKS_STOP | 0x00C | Stop RADIO |
| TASKS_DISABLE | 0x010 | Disable RADIO |
| TASKS_RSSISTART | 0x014 | Start the RSSI and take one single sample of the receive signal strength |
| TASKS_RSSISTOP | 0x018 | Stop the RSSI measurement |
| TASKS_BCSTART | 0x01C | Start the bit counter |
| TASKS_BCSTOP | 0x020 | Stop the bit counter |
| TASKS_EDSTART | 0x024 | Start the energy detect measurement used in IEEE 802.15.4 mode |
| TASKS_EDSTOP | 0x028 | Stop the energy detect measurement |
| TASKS_CCASTART | 0x02C | Start the clear channel assessment used in IEEE 802.15.4 mode |
| TASKS_CCASTOP | 0x030 | Stop the clear channel assessment |
| EVENTS_READY | 0x100 | RADIO has ramped up and is ready to be started |
| EVENTS_ADDRESS | 0x104 | Address sent or received |
| EVENTS_PAYLOAD | 0x108 | Packet payload sent or received |
| EVENTS_END | 0x10C | Packet sent or received |
| EVENTS_DISABLED | 0x110 | RADIO has been disabled |
| EVENTS_DEVMATCH | 0x114 | A device address match occurred on the last received packet |
| EVENTS_DEVMISS | 0x118 | No device address match occurred on the last received packet |
| EVENTS_RSSIEND | 0x11C | Sampling of receive signal strength complete |
| EVENTS_BCMATCH | 0x128 | Bit counter reached bit count value |
| EVENTS_CRCOK | 0x130 | Packet received with CRC ok |
| EVENTS_CRCERROR | 0x134 | Packet received with CRC error |
| Register | Offset | Description |
| EVENTS_FRAMESTART | 0x138 | IEEE 802.15.4 length field received |
| EVENTS_EDEND | 0x13C | Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. |
| EVENTS_EDSTOPPED | 0x140 | The sampling of energy detection has stopped |
| EVENTS_CCAIDLE | 0x144 | Wireless medium in idle - clear to send |
| EVENTS_CCABUSY | 0x148 | Wireless medium busy - do not send |
| EVENTS_CCASTOPPED | 0x14C | The CCA has stopped |
| EVENTS_RATEBOOST | 0x150 | Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. |
| EVENTS_TXREADY | 0x154 | RADIO has ramped up and is ready to be started TX path |
| EVENTS_RXREADY | 0x158 | RADIO has ramped up and is ready to be started RX path |
| EVENTS_MHRMATCH | 0x15C | MAC header match found |
| EVENTS_SYNC | 0x168 | Preamble indicator. |
| EVENTS_PHYEND | 0x16C | Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. |
| SHORTS | 0x200 | Shortcuts between local events and tasks |
| INTENSET | 0x304 | Enable interrupt |
| INTENCLR | 0x308 | Disable interrupt |
| CRCSTATUS | 0x400 | CRC status |
| RXMATCH | 0x408 | Received address |
| RXCRC | 0x40C | CRC field of previously received packet |
| DAI | 0x410 | Device address match index |
| PDUSTAT | 0x414 | Payload status |
| PACKETPTR | 0x504 | Packet pointer |
| FREQUENCY | 0x508 | Frequency |
| TXPOWER | 0x50C | Output power |
| MODE | 0x510 | Data rate and modulation |
| PCNF0 | 0x514 | Packet configuration register 0 |
| PCNF1 | 0x518 | Packet configuration register 1 |
| BASE0 | 0x51C | Base address 0 |
| BASE1 | 0x520 | Base address 1 |
| PREFIX0 | 0x524 | Prefixes bytes for logical addresses 0-3 |
| PREFIX1 | 0x528 | Prefixes bytes for logical addresses 4-7 |
| TXADDRESS | 0x52C | Transmit address select |
| RXADDRESSES | 0x530 | Receive address select |
| CRCCNF | 0x534 | CRC configuration |
| CRCPOLY | 0x538 | CRC polynomial |
| CRCINIT | 0x53C | CRC initial value |
| TIFS | 0x544 | Interframe spacing in μs |
| RSSISAMPLE | 0x548 | RSSI sample |
| STATE | 0x550 | Current radio state |
| DATAWHITEIV | 0x554 | Data whitening initial value |
| BCC | 0x560 | Bit counter compare |
| DAB[0] | 0x600 | Device address base segment 0 |
| DAB[1] | 0x604 | Device address base segment 1 |
| DAB[2] | 0x608 | Device address base segment 2 |
| DAB[3] | 0x60C | Device address base segment 3 |
| DAB[4] | 0x610 | Device address base segment 4 |
| DAB[5] | 0x614 | Device address base segment 5 |
| DAB[6] | 0x618 | Device address base segment 6 |
| DAB[7] | 0x61C | Device address base segment 7 |
| DAP[0] | 0x620 | Device address prefix 0 Device address prefix 1 |
| DAP[1] DAP[2] | 0x624 0x628 | Device address prefix 2 |
| Register | Offset | Description |
| DAP[3] | 0x62C | Device address prefix 3 |
| DAP[4] | 0x630 | Device address prefix 4 |
| DAP[5] | 0x634 | Device address prefix 5 |
| DAP[6] | 0x638 | Device address prefix 6 |
| DAP[7] | 0x63C | Device address prefix 7 |
| DACNF | 0x640 | Device address match configuration |
| MHRMATCHCONF | 0x644 | Search pattern configuration |
| MHRMATCHMAS | 0x648 | Pattern mask |
| MODECNF0 | 0x650 | Radio mode configuration register 0 |
| SFD | 0x660 | IEEE 802.15.4 start of frame delimiter |
| EDCNT | 0x664 | IEEE 802.15.4 energy detect loop count |
| EDSAMPLE | 0x668 | IEEE 802.15.4 energy detect level |
| CCACTRL | 0x66C | IEEE 802.15.4 clear channel assessment control |
| POWER | 0xFFC | Peripheral power control |
## 6.20.14.1 TASKS\_TXEN
Address offset: 0x000
Enable RADIO in TX mode
## 6.20.14.2 TASKS\_RXEN
Address offset: 0x004
Enable RADIO in RX mode
## 6.20.14.3 TASKS\_START
Address offset: 0x008
Start RADIO
## 6.20.14.4 TASKS\_STOP
Address offset: 0x00C
Stop RADIO
## 6.20.14.5 TASKS\_DISABLE
Address offset: 0x010
Disable RADIO
## 6.20.14.6 TASKS\_RSSISTART
Address offset: 0x014
Start the RSSI and take one single sample of the receive signal strength
## 6.20.14.7 TASKS\_RSSISTOP
Address offset: 0x018
Stop the RSSI measurement
## 6.20.14.8 TASKS\_BCSTART
Address offset: 0x01C
## Start the bit counter
## 6.20.14.9 TASKS\_BCSTOP
Address offset: 0x020
Stop the bit counter
## 6.20.14.10 TASKS\_EDSTART
Address offset: 0x024
Start the energy detect measurement used in IEEE 802.15.4 mode
## 6.20.14.11 TASKS\_EDSTOP
Address offset: 0x028
Stop the energy detect measurement
## 6.20.14.12 TASKS\_CCASTART
Address offset: 0x02C
Start the clear channel assessment used in IEEE 802.15.4 mode
## 6.20.14.13 TASKS\_CCASTOP
Address offset: 0x030
Stop the clear channel assessment
## 6.20.14.14 EVENTS\_READY
Address offset: 0x100
RADIO has ramped up and is ready to be started
## 6.20.14.15 EVENTS\_ADDRESS
Address offset: 0x104
Address sent or received
## 6.20.14.16 EVENTS\_PAYLOAD
Address offset: 0x108
Packet payload sent or received
## 6.20.14.17 EVENTS\_END
Address offset: 0x10C
Packet sent or received
## 6.20.14.18 EVENTS\_DISABLED
Address offset: 0x110
RADIO has been disabled
## 6.20.14.19 EVENTS\_DEVMATCH
Address offset: 0x114
A device address match occurred on the last received packet
## 6.20.14.20 EVENTS\_DEVMISS
Address offset: 0x118
No device address match occurred on the last received packet
## 6.20.14.21 EVENTS\_RSSIEND
Address offset: 0x11C
Sampling of receive signal strength complete
A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register
## 6.20.14.22 EVENTS\_BCMATCH
Address offset: 0x128
Bit counter reached bit count value
Bit counter value is specified in the RADIO.BCC register
## 6.20.14.23 EVENTS\_CRCOK
Address offset: 0x130
Packet received with CRC ok
## 6.20.14.24 EVENTS\_CRCERROR
Address offset: 0x134
Packet received with CRC error
## 6.20.14.25 EVENTS\_FRAMESTART
Address offset: 0x138
IEEE 802.15.4 length field received
## 6.20.14.26 EVENTS\_EDEND
Address offset: 0x13C
Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
## 6.20.14.27 EVENTS\_EDSTOPPED
Address offset: 0x140
The sampling of energy detection has stopped
## 6.20.14.28 EVENTS\_CCAIDLE
Address offset: 0x144
Wireless medium in idle - clear to send
## 6.20.14.29 EVENTS\_CCABUSY
Address offset: 0x148
Wireless medium busy - do not send
## 6.20.14.30 EVENTS\_CCASTOPPED
Address offset: 0x14C
The CCA has stopped
## 6.20.14.31 EVENTS\_RATEBOOST
Address offset: 0x150
Ble\_LR CI field received, receive mode is changed from Ble\_LR125Kbit to Ble\_LR500Kbit. Ble\_LR CI field received, receive mode is changed from Ble\_LR125Kbit to Ble\_LR500Kbit.
## 6.20.14.32 EVENTS\_TXREADY
Address offset: 0x154
RADIO has ramped up and is ready to be started TX path
## 6.20.14.33 EVENTS\_RXREADY
Address offset: 0x158
RADIO has ramped up and is ready to be started RX path
## 6.20.14.34 EVENTS\_MHRMATCH
Address offset: 0x15C
MAC header match found
## 6.20.14.35 EVENTS\_SYNC
## Address offset: 0x168
Preamble indicator.
A possible preamble has been received in Ble\_LR125Kbit, Ble\_LR500Kbit or Ieee802154\_250Kbit modes during an RX transaction. False triggering of the event is possible.
## 6.20.14.36 EVENTS\_PHYEND
Address offset: 0x16C
Generated in Ble\_LR125Kbit, Ble\_LR500Kbit and Ieee802154\_250Kbit modes when last bit is sent on air.
## 6.20.14.37 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
| Bit number | | | 31 30 | 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| -------------- | ------------------------------ | ------------------------------ | ----------- | ------------------------------ |
| ID Reset | 0x00000000 | | 0 0 0 | U T S R Q P O N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value | Description |
| B RW | | Enabled | 1 | Enable shortcut |
| | END_DISABLE | Disabled Enabled | 0 1 | Shortcut between event END and task DISABLE Disable shortcut Enable shortcut |
| D | DISABLED_RXEN | Disabled Enabled | 0 | Disable shortcut Enable shortcut Shortcut between event DISABLED and task RXEN Disable shortcut Enable shortcut Shortcut between event ADDRESS and task Disable shortcut Enable shortcut Shortcut between event END and task START |
| RW | RW | Disabled | 1 | RSSISTART Disable shortcut Enable shortcut |
| E | RW END_START RW | Enabled ADDRESS_RSSISTART Disabled Enabled | 0 1 0 0 1 | Shortcut between event ADDRESS and task BCSTART |
| F RW | ADDRESS_BCSTART DISABLED_RSSISTOP | Disabled Enabled Disabled Enabled Disabled Enabled | 1 0 1 0 1 | Disable shortcut Enable shortcut Shortcut between event DISABLED and task RSSISTOP Disable shortcut Enable shortcut Shortcut between event RXREADY and task CCASTART Shortcut between event CCAIDLE and task TXEN Disable shortcut Enable shortcut Shortcut between event CCABUSY and task DISABLE Disable shortcut Enable shortcut Shortcut between event FRAMESTART and task Disable shortcut |
| G | RXREADY_CCASTART | Disabled Enabled Disabled | 1 0 | Enable shortcut Shortcut between event READY and task EDSTART Disable shortcut |
| H K | RW | Enabled | 0 1 0 | Disable shortcut Enable shortcut |
| L RW | CCAIDLE_TXEN | | | |
| | RW<br>CCABUSY_DISABLE | Disabled | 1 | Enable shortcut |
| M RW | EDEND_DISABLE | Enabled | 1 0 | Enable shortcut Shortcut between event TXREADY and task START Disable shortcut |
| N | | | | |
| | | Enabled Disabled | 1 | Shortcut between event EDEND and task DISABLE Disable shortcut |
| | RW FRAMESTART_BCSTART | Disabled | 0 | BCSTART |
| O RW | CCAIDLE_STOP | Enabled Disabled | 0 1 0 | Enable shortcut Shortcut between event CCAIDLE and task STOP Disable shortcut |
| | RW | Disabled Enabled | 0 1 | Shortcut between event RXREADY and task START Disable shortcut Enable shortcut |
| P | READY_EDSTART | Enabled Disabled Enabled | 1 | |
| Q | RW | Disabled | | Enable shortcut |
| R | RW<br>RXREADY_START<br>TXREADY_START | Enabled | 1<br>0 | |
| S | PHYEND_DISABLE | | | Shortcut between event PHYEND and task |
| T | | | | |
| RW | | | | DISABLE |
| Bit number | | 31 30 | 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | -------------- | ---------------- | ------------------------------ |
| ID | | | U T S R Q P O N M L K H G F E D C B A |
| Reset 0x00000000 | | 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID Value | Description |
| | | Disabled 0 | Disable shortcut |
| | | Enabled 1 | Enable shortcut |
| U RW | PHYEND_START | | Shortcut between event PHYEND and task START |
| | | Disabled 0 | Disable shortcut |
| | | Enabled 1 | Enable shortcut |
## 6.20.14.38 INTENSET
Address offset: 0x304
Enable interrupt
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | | | | | | 7 6 5 4 2 1 | 3 | 0 |
| ------------------ | ------------- | ------------------ | ------------------------------ | ------- | --------------------- | ----------- | --------------- | ---------- | --------------- | ------------------ | ----- |
| ID | | | | Z | V U T S R | Q P O | N M | I | H G F E D | C | B A |
| Reset 0x00000000 | | | 0 0 | 0 0 0 | 0 0 0 0 | 0 0 0 | 0 0 0 | 0 0 | 0 0 0 0 | 0 0 0 | 0 0 |
| ID | R/W Field | Value ID | Value | | Description | | | | | | |
| A | READY<br>RW | Disabled<br>Enabled | 0<br>1 | | Write '1' to enable<br>Read: Disabled<br>Write '1' to | enable | interrupt for<br>interrupt for | READY | | | |
| B | RW ADDRESS | Set Disabled | 1<br>0 | | Enable<br>Read: Disabled | | | ADDRESS | | | |
| C | RW PAYLOAD | Disabled | 0 | | Write '1' to<br>Read: Disabled | enable<br>Enabled | interrupt for | PAYLOAD | | | |
| D | RW END | Disabled<br>Enabled | 1<br>0<br>1 | | Write '1' to<br>Enable<br>Read: Disabled<br>Read: Enabled | enable | interrupt for | END | | | |
| E | RW DISABLED | Set<br>Disabled Enabled | 1<br>0 1 | | Write '1' to Enable<br>Read: Disabled<br>Read: Enabled | enable | interrupt for | DISABLED | | | |
| F | RW<br>DEVMATCH | Set Disabled<br>Enabled | 1<br>1 | | Write '1' to enable<br>Read: Disabled<br>Read: Enabled | | interrupt for | DEVMATCH | | | |
| G | RW<br>DEVMISS | Set<br>Disabled | 1<br>0 | | Write '1' to<br>Enable<br>Read: Disabled | enable | interrupt for | DEVMISS | | | |
| H | RW | | | | Write '1' to<br>new RSSI register | enable<br>sample is | interrupt for<br>ready for | RSSIEND<br>from the | | RADIO.RSSISAMPLE | |
| Bit number | | | 31 30 29 28 27 | 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| --------------------- | ---------------------------- | ------------------------------ | ------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID | | | Z Y | V U T S R Q P O N M L K I H G F E D C B A | V U T S R Q P O N M L K I H G F E D C B A | V U T S R Q P O N M L K I H G F E D C B A |
| Reset 0x00000000 ID | R/W Field | 0 Value ID | 0 0 0 0 0 Value | 0 0 Description | 0 0 Description | 0 0 Description |
| I | RW BCMATCH | | | Write '1' to enable interrupt for event BCMATCH | Write '1' to enable interrupt for event BCMATCH | Write '1' to enable interrupt for event BCMATCH |
| K | Set CRCOK | Disabled 0 Enabled 1 | 1 | Bit counter value is specified in the RADIO.BCC register Enable Read: Disabled Enabled | Bit counter value is specified in the RADIO.BCC register Enable Read: Disabled Enabled | Read: |
| | RW | Set Disabled | 1 | Write '1' to enable interrupt for event CRCOK Enable Read: Disabled | Write '1' to enable interrupt for event CRCOK Enable Read: Disabled | Write '1' to enable interrupt for event CRCOK Enable Read: Disabled |
| L | RW CRCERROR | Enabled Set Disabled Enabled Set Disabled | 0 1 | Read: Enabled Write '1' to enable interrupt for event CRCERROR | Read: Enabled Write '1' to enable interrupt for event CRCERROR | Read: Enabled Write '1' to enable interrupt for event CRCERROR |
| M RW EDEND | RW FRAMESTART | 1 0 Enabled 1 Set 1 | 1 0 1 | Enable Read: Disabled Read: Enabled '1' to enable Disabled Enabled '1' to enable | Enable Read: Disabled Read: Enabled '1' to enable Disabled Enabled '1' to enable | Write Enable Read: Read: Write Enable |
| N O | RW EDSTOPPED Set | Disabled 0 Enabled 1 1 Disabled 0 Enabled 1 Set 1 Disabled 0 Enabled | 1 0 1 | Disabled Enabled '1' to enable Disabled Enabled '1' to enable Enable Read: Disabled Read: Enabled | Disabled Enabled '1' to enable Disabled Enabled '1' to enable Enable Read: Disabled Read: Enabled | Disabled Enabled '1' to enable Disabled Enabled '1' to enable Enable Read: Disabled Read: Enabled |
| P | RW CCAIDLE | 1 Set 1 Disabled Enabled | | Write '1' to enable interrupt for event RATEBOOST | Write '1' to enable interrupt for event RATEBOOST | Write '1' to enable interrupt for event RATEBOOST |
| S | CCASTOPPED | Set Disabled Enabled | 1 0 | Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit Ble_LR500Kbit. Enable | Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit Ble_LR500Kbit. Enable | Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit Ble_LR500Kbit. Enable |
| | RW CCABUSY RW RW RATEBOOST | | 1 | to | to | to |
| Q | | 0 1 | | Disabled Enabled<br>Read: Disabled | Disabled Enabled<br>Read: Disabled | Disabled Enabled<br>Read: Disabled |
| R | | | 1 | Read: Enabled Write '1' to enable interrupt for event TXREADY Enable | Read: Enabled Write '1' to enable interrupt for event TXREADY Enable | Read: Enabled Write '1' to enable interrupt for event TXREADY Enable |
| T | | Set Disabled | 0<br>1 | Read: Disabled | Read: Disabled | Read: Disabled |
| | | Set<br>Enabled | 1 | Read: Enabled Write '1' to enable interrupt for event RXREADY<br>Read: Disabled Read: Enabled Write '1' to enable interrupt for event CCABUSY Enable | Read: Enabled Write '1' to enable interrupt for event RXREADY<br>Read: Disabled Read: Enabled Write '1' to enable interrupt for event CCABUSY Enable | Read: Enabled Write '1' to enable interrupt for event RXREADY<br>Read: Disabled Read: Enabled Write '1' to enable interrupt for event CCABUSY Enable |
| | RW<br>TXREADY | Enabled<br>Set Disabled | | Enable<br>Write '1' to enable interrupt for event CCASTOPPED | Enable<br>Write '1' to enable interrupt for event CCASTOPPED | Enable<br>Write '1' to enable interrupt for event CCASTOPPED |
| U | RXREADY | Disabled | 0 | Read:<br>Disabled | Read:<br>Disabled | Read:<br>Disabled |
| RW | | | | | | |
| Bit number |
| -------------- |
## 6.20.14.39 INTENCLR
Address offset: 0x308
Disable interrupt
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 | | | | | | | | | 6 5 4 | 3 2 | 1 0 |
| -------------- | ------------- | ---------------- | ------------------------------ | ------- | ---- | ----- | -------------------------- | ------------------- | --------------- | ----------- | --------- | ---------- | --------- | ------- |
| ID | | | | | Z | Y | V U T S R | Q P O N | M | L K | I | | H G | F E |
| 0x00000000 | 0x00000000 | | 0 0 | | 0 | 0 0 | 0 | | 0 | 0 0 0 | | 0 0 | 0 0 | 0 0 |
| Reset | | | | | 0 | | 0 0 0 | 0 | 0 0 | | | | 0 | 0 0 |
| ID A | R/W Field<br>RW READY | Value ID<br>Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | Value | | | Description Write '1' to<br>Disable<br>Read: Disabled<br>Read: Enabled | disable | interrupt | for event | READY | | | |
| B RW | ADDRESS | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | | Write '1' to Disable<br>Read: Disabled<br>Read: Enabled | disable interrupt | for | event | | | ADDRESS | |
| C | RW PAYLOAD | Disabled<br>Enabled | 0<br>1 | | | | Write '1' to<br>Disable Read: Disabled<br>Read: Enabled | disable | interrupt for | event | PAYLOAD | | | |
| D | RW END | Clear Disabled<br>Enabled | 1<br>0<br>1 | | | | Write '1' to<br>Disable<br>Read: Disabled<br>Read: Enabled | disable | interrupt for | event | END | | | |
| E | RW DISABLED | Clear<br>Disabled<br>Enabled | 1<br>1 | 0 | | | Write '1' to<br>Disable<br>Read: Disabled<br>Read: Enabled | disable | interrupt | for event | | DISABLED | | |
| F | RW DEVMATCH | Clear<br>Disabled | 1<br>0 | | | | Write '1' to<br>Disable Read:<br>Disabled | disable | interrupt for | event | | DEVMATCH | | |
| Bit number | | | 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| --------------- | ------------------------------ | ------------------------------ | ------- | ------------------------------ | ------------------------------ | ------------------------------ |
| ID | | | | Z Y V U T S R Q P O N M L K I H G F E D C B A | Z Y V U T S R Q P O N M L K I H G F E D C B A | Z Y V U T S R Q P O N M L K I H G F E D C B A |
| Reset 0 | 0x00000000 | | 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description | Description | Description |
| G | RW DEVMISS | | | Write '1' to disable interrupt for event DEVMISS | Write '1' to disable interrupt for event DEVMISS | Write '1' to disable interrupt for event DEVMISS |
| 1 H I | Clear Disabled Enabled RW RSSIEND RW | Clear Disabled Enabled Clear | 1 0 | Disable Read: Disabled Read: Enabled Write '1' to disable interrupt for event RSSIEND A Bit | new register Disable Read: Read: Write '1' counter | RSSI sample is ready for Disabled Enabled to disable interrupt for value is specified in |
| 1 L | BCMATCH | Disabled Enabled Clear | 0 1 1 | Read: Enabled Write '1' to disable interrupt for event EDEND Disable Read: Disabled | Read: Enabled Write '1' to disable interrupt for event EDEND Disable Read: Disabled | Read: Enabled Write '1' to disable interrupt for event EDEND Disable Read: Disabled |
| 1 0 1 K 1 0 N | RW CRCOK | | 1 | | Disable Read: Read: Write '1' Disable Read: | Disabled Enabled to disable interrupt for Disabled |
| 1 0 1 M 1 | RW CRCERROR RW FRAMESTART EDSTOPPED | Disabled Enabled Clear Disabled Enabled Clear Disabled | 0 1 | Read: Enabled Write '1' to disable interrupt for event EDSTOPPED Disable Read: Disabled | Read: Enabled Write '1' to disable interrupt for event EDSTOPPED Disable Read: Disabled | Read: Enabled Write '1' to disable interrupt for event EDSTOPPED Disable Read: Disabled |
| 0 | RW<br>RW EDEND | Enabled Clear<br>Disabled Enabled | 1 0<br>1 | Read: Enabled | Read: Enabled | Read: Enabled |
| 1 | | | | | | |
| O | RW CCAIDLE | Clear Disabled Enabled | 1 0 | | | |
| P | | Clear Disabled | 1 | Write '1' to disable interrupt for event CCAIDLE Disable Read: Disabled<br>Read: Enabled | Write '1' to disable interrupt for event CCAIDLE Disable Read: Disabled<br>Read: Enabled | Write '1' to disable interrupt for event CCAIDLE Disable Read: Disabled<br>Read: Enabled |
| Q | RW<br>CCABUSY | Clear<br>Enabled<br>Disabled Enabled | 1 0 | Write '1' to disable interrupt for event CCABUSY Disable Read: Disabled | Write '1' to disable interrupt for event CCABUSY Disable Read: Disabled | Write '1' to disable interrupt for event CCABUSY Disable Read: Disabled |
| | RW | Clear | 1<br>1 | Read: Enabled<br>Write '1' to disable interrupt for | Read: Enabled<br>Write '1' to disable interrupt for | Read: Enabled<br>Write '1' to disable interrupt for |
| R | | | | Disable<br>event | Disable<br>event | Disable<br>event |
| | | Disabled<br>Enabled | 0 | Read: Disabled<br>CCASTOPPED | Read: Disabled<br>CCASTOPPED | Read: Disabled<br>CCASTOPPED |
| | CCASTOPPED | | 1 | Read: Enabled | Read: Enabled | Read: Enabled |
| Bit number | | | 31 | 30 | 28 27 | 26 25 24 23 22 | 19 18 17 16 15 14 | 21 20 | | 13 12 11 10 | 9 8 7 6 5 3 2 1 | 0 | 4 |
| -------------- | ------- | ------------ | ---------- | ------- | --------- | ------------------ | ------------------------------ | ------------------------------ | --------------- | ----------------------------- | ---------------------------- | ------- | --------------- |
| ID | | | | | Z | | R Q | V U T S | P O N M | L | K I H G F | C B A | E D |
| Reset | Reset | 0x00000000 | | 0 0 | 0 0 | 0 0 | 0 0 | 0 0 0 0 | 0 | 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 | 0 0 0 |
| ID | R/W | Field | Value ID | Value | | | | Description | | | | | |
| S | RW | RATEBOOST | Clear<br>Enabled | 1<br>1 | | | | Write '1' to disable interrupt for<br>Ble_LR CI field received,<br>Ble_LR500Kbit.<br>Disable Read: Disabled<br>Read: Enabled | | event<br>receive mode is changed | RATEBOOST<br>from | to | Ble_LR125Kbit |
| T | RW | TXREADY | Clear<br>Enabled | 1<br>1 | | | disable | Write '1' to<br>Disable Read: Disabled<br>Read: Enabled | | interrupt for event TXREADY | | | |
| U | RW | RXREADY | Disabled | 1<br>0 | | | Disabled | Write '1' to disable<br>Read: | interrupt for | | event RXREADY | | |
| V | RW | MHRMATCH | Clear<br>Disabled<br>Enabled | 1<br>1<br>0<br>1 | | | | Read: Enabled Write '1' to disable<br>Disable<br>Read: Disabled Read: | | interrupt for | event MHRMATCH | | |
| Y | RW | SYNC | Disabled<br>Disabled | 0<br>1<br>0 | | | Enabled disable | A possible Read:<br>Disabled<br>Write '1' to<br>Read: Enabled Write '1' to<br>Disable | interrupt | for<br>for | False<br>during an RX transaction.<br>event PHYEND<br>received in Ble_LR125Kbit, | of<br>or | triggering<br>Ble_LR500Kbit |
| Z | RW | PHYEND | Clear<br>Enabled<br>Clear | 1<br>1<br>1 | | | disable<br>Enabled<br>preamble Ieee802154_250Kbit possible. | Read: Disabled<br>event is Disable Read: | interrupt<br>modes | has been | event SYNC | the | |
## 6.20.14.40 CRCSTATUS
Address offset: 0x400
CRC status
## 6.20.14.41 RXMATCH
Address offset: 0x408
Received address
CRC status of packet received
Packet received with CRC error
Logical address of which previous packet was received
## 6.20.14.42 RXCRC
Address offset: 0x40C
CRC field of previously received packet
CRC field of previously received packet
## 6.20.14.43 DAI
Address offset: 0x410
Device address match index
## 6.20.14.44 PDUSTAT
Address offset: 0x414
Payload status
## 6.20.14.45 PACKETPTR
Address offset: 0x504
## Packet pointer
Packet pointer
Packet address to be used for the next transmission or reception. When transmitting, the packet pointed to by this address will be transmitted and when receiving, the received packet will be written to this address. This address is a byte aligned RAM address.
Note: See the memory chapter for details about which memories are available for EasyDMA.
A
RW
PACKETPTR
## 6.20.14.46 FREQUENCY
Address offset: 0x508
Frequency
| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID B A A A A A | ID B A A A A A | ID B A A A A A | ID B A A A A A |
| Reset 0x00000002 | Reset 0x00000002 | Reset 0x00000002 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 |
| ID R/W | Field Value ID | Value | Description |
| A RW | FREQUENCY | [0..100] | Radio channel frequency<br>Frequency = 2400 + FREQUENCY (MHz). |
| B RW | MAP Default | 0 | Channel map selection. Channel map between 2400 MHZ .. 2500 MHz<br>Frequency = 2400 + FREQUENCY (MHz) |
| | Low | 1 | Channel map between 2360 MHZ .. 2460 MHz<br>Frequency = 2360 + FREQUENCY (MHz) |
## 6.20.14.47 TXPOWER
Address offset: 0x50C
Output power
Pos8dBm
0x8
+8 dBm
Pos7dBm
0x7
+7 dBm
Pos6dBm
0x6
+6 dBm
Pos5dBm
0x5
+5 dBm
Pos4dBm
0x4
+4 dBm
Pos3dBm
0x3
+3 dBm
## 6.20.14.48 MODE
## Address offset: 0x510
## Data rate and modulation
## 6.20.14.49 PCNF0
## Address offset: 0x514
## Packet configuration register 0
| Bit number 1 0 | | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 |
| ------------------------------ | ----------- | -------- | ------------------------------ | ------------------------------ |
| ID H H G F F E E D C C C C B A A A | | | | A |
| Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | | | | |
| ID | R/W Field | | | Value ID Value Description |
| A | RW | LFLEN | Length on air of LENGTH field in number of bits. | |
| B | RW | S0LEN | Length on air of S0 field in number of bytes. | |
| C | RW | S1LEN | Length on air of S1 field in number of bits. | |
| D | RW | S1INCL | Include or exclude S1 field in RAM | |
| Include | | | Automatic | 0 S1 field in RAM only if S1LEN > 0 |
| Always | | | Include | 1 include S1 field in RAM independent of S1LEN |
| E | RW | CILEN | Length of code indicator - long range | |
| F | RW | PLEN | Length of preamble on air. Decision point: TASKS_START task | |
| 8-bit | | | 8bit | 0 preamble |
| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID H H | ID H H | ID H H | G F F E E D C C C C B A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value | Description |
| | 16bit | 1 | 16-bit preamble |
| | 32bitZero | 2 | 32-bit zero preamble - used for IEEE 802.15.4 |
| | LongRange | 3 | Preamble - used for BLE long range |
| G RW | CRCINC | | Indicates if LENGTH field contains CRC or not |
| | Exclude | 0 | LENGTH does not contain CRC |
| | Include | 1 | LENGTH includes CRC |
| H RW | TERMLEN | | Length of TERM field in Long Range operation |
## 6.20.14.50 PCNF1
Address offset: 0x518
Packet configuration register 1
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------------------ |
| ID | | E |
| Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 |
| ID R/W | Field | Value |
| A | RW MAXLEN | [0..255] |
| B | RW STATLEN | [0..255] |
| C | RW BALEN | [2..4] |
| D RW | ENDIAN | 0 1 |
| E | | |
| | RW WHITEEN | 0 |
## 6.20.14.51 BASE0
Address offset: 0x51C
Base address 0
| Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------------------ |
| ID | A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A |
| Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value Description |
| A RW BASE0 | Base address 0 |
Radio base address 0.
## 6.20.14.52 BASE1
Address offset: 0x520
Base address 1
Radio base address 1.
## 6.20.14.53 PREFIX0
Address offset: 0x524
Prefixes bytes for logical addresses 0-3
| Bit number | Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | ID | D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | | Value | Description |
| A | RW | AP0 | | Address prefix 0. |
| B | RW | AP1 | | Address prefix 1. |
| C | RW | AP2 | | Address prefix 2. |
| D | RW | AP3 | | Address prefix 3. |
## 6.20.14.54 PREFIX1
Address offset: 0x528
Prefixes bytes for logical addresses 4-7
| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value Description |
| A | RW AP4 | | Address prefix 4. |
| B | RW AP5 | | Address prefix 5. |
| C | RW AP6 | | Address prefix 6. |
| D | RW AP7 | | Address prefix 7. |
## 6.20.14.55 TXADDRESS
Address offset: 0x52C
Transmit address select
Logical address to be used when transmitting a packet.
## 6.20.14.56 RXADDRESSES
Address offset: 0x530
Receive address select
| Bit number | | 31 30 | 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ---------------- | ------------------------------ |
| ID | | | H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID Value | Description |
| A RW | ADDR0 | | Enable or disable reception on logical address 0. |
| | | Disabled 0 | Disable |
| | | Enabled 1 | Enable |
| B RW | ADDR1 | | Enable or disable reception on logical address 1. |
| | | Disabled | 0 Disable |
| | | Enabled 1 | Enable |
| C RW | ADDR2 | | Enable or disable reception on logical address 2. |
| | | Disabled<br>Enabled | 0 Disable |
| D | | | Enable<br>1 |
| RW | ADDR3 | | Enable or disable reception on logical address 3. |
| | | Enabled | 1 Enable |
| E RW | | Disabled 0 | Enable or disable reception on logical |
| | ADDR4 | | address 4. |
| | | Enabled 1 | Disable Enable |
| F RW | | | reception on logical address 5. |
| | | Disabled 0 | Disable |
| | ADDR5 | | Enable or disable |
| G RW | ADDR6 | | Enable or disable reception on logical address 6. |
| | | Disabled 0 | Disable |
| | | Enabled 1 | Enable |
| H RW | ADDR7 | Disabled 0 | Enable or disable reception on logical address 7. |
| | | Enabled 1 | Disable<br>Enable |
## 6.20.14.57 CRCCNF
Address offset: 0x534
CRC configuration
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------ | ------------------------------ |
| ID | | B B A A |
| Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW LEN | | [1..3] CRC length in number of bytes.<br>Note: For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported |
| | Disabled | 0 CRC length is zero and CRC calculation is disabled |
| | One | 1 CRC length is one byte and CRC calculation is enabled |
| | Two | 2 CRC length is two bytes and CRC calculation is enabled |
| | Three | 3 CRC length is three bytes and CRC calculation is enabled |
| B RW SKIPADDR | | Include or exclude packet address field out of CRC calculation. |
| | Include | 0 CRC calculation includes address field |
| | Skip | 1 CRC calculation does not include address field. The CRC calculation will start<br>at the first byte after the address. |
| | Ieee802154 | 2 CRC calculation as per 802.15.4 standard. Starting at first byte after length |
## 6.20.14.58 CRCPOLY
Address offset: 0x538
CRC polynomial
Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/ bit is hard-wired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
## 6.20.14.59 CRCINIT
Address offset: 0x53C
CRC initial value
Initial value for CRC calculation
## 6.20.14.60 TIFS
Address offset: 0x544
Interframe spacing in μs
## 6.20.14.61 RSSISAMPLE
Address offset: 0x548
RSSI sample
## 6.20.14.62 STATE
Address offset: 0x550
Current radio state
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ----------- | ------------------------------ |
| ID | | A A A A |
| Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A R STATE | | Current radio state |
| | Disabled | 0 RADIO is in the Disabled state |
| | RxRu | 1 RADIO is in the RXRU state |
| | RxIdle | 2 RADIO is in the RXIDLE state |
| | Rx | 3 RADIO is in the RX state |
| | RxDisable | 4 RADIO is in the RXDISABLED state |
| | TxRu | 9 RADIO is in the TXRU state |
| | TxIdle | 10 RADIO is in the TXIDLE state |
| | Tx | 11<br>RADIO is in the TX state |
| | TxDisable | 12 RADIO is in the TXDISABLED state |
## 6.20.14.63 DATAWHITEIV
Address offset: 0x554
Data whitening initial value
Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5, etc.
## 6.20.14.64 BCC
Address offset: 0x560
Bit counter compare
Bit counter compare register
## 6.20.14.65 DAB[0]
Address offset: 0x600
Device address base segment 0
## 6.20.14.66 DAB[1]
Address offset: 0x604
Device address base segment 1
## 6.20.14.67 DAB[2]
Address offset: 0x608
Device address base segment 2
## 6.20.14.68 DAB[3]
Address offset: 0x60C
Device address base segment 3
## 6.20.14.69 DAB[4]
Address offset: 0x610
Device address base segment 4
## 6.20.14.70 DAB[5]
Address offset: 0x614
Device address base segment 5
## 6.20.14.71 DAB[6]
Address offset: 0x618
Device address base segment 6
## 6.20.14.72 DAB[7]
Address offset: 0x61C
Device address base segment 7
## 6.20.14.73 DAP[0]
Address offset: 0x620
Device address prefix 0
## 6.20.14.74 DAP[1]
Address offset: 0x624
Device address prefix 1
## 6.20.14.75 DAP[2]
Address offset: 0x628
Device address prefix 2
## 6.20.14.76 DAP[3]
Address offset: 0x62C
Device address prefix 3
## 6.20.14.77 DAP[4]
Address offset: 0x630
Device address prefix 4
## 6.20.14.78 DAP[5]
Address offset: 0x634
Device address prefix 5
## 6.20.14.79 DAP[6]
Address offset: 0x638
Device address prefix 6
## 6.20.14.80 DAP[7]
Address offset: 0x63C
Device address prefix 7
## 6.20.14.81 DACNF
Address offset: 0x640
## Device address match configuration
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------ | ---------- | ------------------------------ |
| ID | | | P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value Description |
| A RW | ENA0 | | Enable or disable device address matching using device address 0 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| B RW | ENA1 | | Enable or disable device address matching using device address 1 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| C RW | ENA2 | | Enable or disable device address matching using device address 2 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| D RW | ENA3 | | Enable or disable device address matching using device address 3 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| E RW | ENA4 | | Enable or disable device address matching using device address 4 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| F RW | ENA5 | | Enable or disable device address matching using device address 5 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| G RW | ENA6 | | Enable or disable device address matching using device address 6 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| H RW | ENA7 | | Enable or disable device address matching using device address 7 |
| | | Disabled | 0 Disabled |
| | | Enabled | 1 Enabled |
| I RW | TXADD0 | | TxAdd for device address 0 |
| J RW | TXADD1 | | TxAdd for device address 1 |
| K RW | TXADD2 | | TxAdd for device address 2 |
| L RW | TXADD3 | | TxAdd for device address 3 |
| M RW | TXADD4 | | TxAdd for device address 4 |
| N RW | TXADD5 | | TxAdd for device address 5 |
| O RW | TXADD6 | | TxAdd for device address 6 |
| P RW | TXADD7 | | TxAdd for device address 7 |
## 6.20.14.82 MHRMATCHCONF
Address offset: 0x644
Search pattern configuration
## 6.20.14.83 MHRMATCHMAS
Address offset: 0x648
Pattern mask
## 6.20.14.84 MODECNF0
Address offset: 0x650
Radio mode configuration register 0
| Bit number | 31 30 29 28 | 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | --------------- | ------------------------------ |
| ID | | B B A |
| Reset 0x00000200 | 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value | Description |
| A RW RU | 0 | Radio ramp-up time Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 |
| | 1 | Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information |
| B RW DTX | | Default TX value Specifies what the RADIO will transmit when it is not started, i.e. between: RADIO.EVENTS_READY and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.TASKS_START |
| | 0 | Transmit '1' |
## 6.20.14.85 SFD
Address offset: 0x660
IEEE 802.15.4 start of frame delimiter
Pattern mask
## 6.20.14.86 EDCNT
Address offset: 0x664
IEEE 802.15.4 energy detect loop count
Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE
## 6.20.14.87 EDSAMPLE
Address offset: 0x668
IEEE 802.15.4 energy detect level
## 6.20.14.88 CCACTRL
Address offset: 0x66C
IEEE 802.15.4 clear channel assessment control
| Bit number | Bit number | Bit number | Bit number | Bit number |
| -------------- | -------------- | -------------- | -------------- | -------------- |
## 6.20.14.89 POWER
Address offset: 0xFFC
Peripheral power control
Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
Disabled
0
Peripheral is powered off
Enabled
1
Peripheral is powered on
## 6.20.15 Electrical specification
## 6.20.15.1 General radio characteristics
| Symbol | Description | Min. | Typ. | Max. | Units |
| ----------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| f OP | Operating frequencies | 2360 | | 2500 | MHz |
| f PLL,CH,SP | PLL channel spacing | | 1 | | MHz |
| f DELTA,1M | Frequency deviation@1Mbps | | ±170 | | kHz |
| f DELTA,BLE,1M | Frequency deviation @BLE 1 Mbps | | ±250 | | kHz |
| f DELTA,2M | Frequency deviation@2Mbps | | ±320 | | kHz |
| f DELTA,BLE,2M | Frequency deviation @BLE 2 Mbps | | ±500 | | kHz |
| fsk BPS | On-the-air data rate | 125 | | 2000 | kbps |
| f chip, IEEE 802.15.4 | Chip rate in IEEE 802.15.4 mode | | 2000 | | kchip/s |
## 6.20.15.2 Radio current consumption (transmitter)
| Symbol | Description | Min. | Typ. | Max. | Units |
| ----------------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| I TX,PLUS8dBM,DCDC | TX only run current (DC/DC, 3 V) P RF = +8 dBm | | 14.8 | | mA |
| I TX,PLUS8dBM | TX only run current P RF = +8 dBm | | 32.7 | | mA |
| I TX,PLUS4dBM,DCDC | TX only run current (DC/DC, 3 V) P RF = +4 dBm | | 9.6 | | mA |
| I TX,PLUS4dBM | TX only run current P RF = +4 dBm | | 21.4 | | mA |
| I TX,0dBM,DCDC,5V,REG0HIGH. | TX only run current (DC/DC, 5 V, REG0 out = 3.3 V)P RF = 0 dBm | | 3 | | mA |
| I TX,0dBM,DCDC,5V,REG0LOW | TX only run current (DC/DC, 5 V, REG0 out = 1.8 V)P RF = 0 dBm | | 3 | | mA |
| I TX,0dBM,DCDC | TX only run current (DC/DC, 3 V)P RF = 0 dBm | | 4.8 | | mA |
| I TX,0dBM | TX only run current P RF = 0 dBm | | 10.6 | | mA |
| I TX,MINUS4dBM,DCDC | TX only run current DC/DC, 3 V P RF = -4 dBm | | 3.1 | | mA |
| I TX,MINUS4dBM | TX only run current P RF = -4 dBm | | 8.1 | | mA |
| I TX,MINUS8dBM,DCDC | TX only run current DC/DC, 3 V P RF = -8 dBm | | 3.3 | | mA |
| I TX,MINUS8dBM | TX only run current P RF = -8 dBm | | 7.2 | | mA |
| I TX,MINUS12dBM,DCDC | TX only run current DC/DC, 3 V P RF = -12 dBm | | 3 | | mA |
| I TX,MINUS12dBM | TX only run current P RF = -12 dBm | | 6.4 | | mA |
| I TX,MINUS16dBM,DCDC | TX only run current DC/DC, 3 V P RF = -16 dBm | | 2.8 | | mA |
| I TX,MINUS16dBM | TX only run current P RF = -16 dBm | | 6 | | mA |
| I TX,MINUS20dBM,DCDC | TX only run current DC/DC, 3 V P RF = -20 dBm | | 2.7 | | mA |
| I TX,MINUS20dBM | TX only run current P RF = -20 dBm | | 5.6 | | mA |
| I TX,MINUS40dBM,DCDC | TX only run current DC/DC, 3 V P RF = -40 dBm | | 2.3 | | mA |
| I TX,MINUS40dBM | TX only run current P RF = -40 dBm | | 4.6 | | mA |
| I START,TX,DCDC | TX start-up current DC/DC, 3 V, P RF = 4 dBm | | 5.2 | | mA |
| I START,TX | TX start-up current, P RF = 4 dBm | | 11 | | mA |
## 6.20.15.3 Radio current consumption (Receiver)
| Symbol | Description | Min. | Typ. | Max. | Units |
| -------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| I RX,1M,DCDC | RX only run current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE | | 4.6 | | mA |
| I RX,1M | RX only run current (LDO, 3 V) 1 Mbps/1 Mbps BLE | | 9.9 | | mA |
| I RX,2M,DCDC | RX only run current (DC/DC, 3 V) 2 Mbps/2 Mbps BLE | | 5.2 | | mA |
| I RX,2M | RX only run current (LDO, 3 V) 2 Mbps/2 Mbps BLE | | 11.1 | | mA |
| I START,RX,1M,DCDC | RX start-up current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE | | 3.7 | | mA |
| I START,RX,1M | RX start-up current 1 Mbps/1 Mbps BLE | | 6.7 | | mA |
## 6.20.15.4 Transmitter specification
| Symbol | Description | Min. | Typ. | Max. | Units |
| -------------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| P RF | Maximum output power | | 8 | | dBm |
| P RFC | RF power control range | | 28 | | dB |
| P RFCR | RF power accuracy | | | ±4 | dB |
| P RF1,1 | 1st Adjacent Channel Transmit Power 1 MHz (1 Mbps) | | -24.8 | | dBc |
| P RF2,1 | 2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps) | | -54 | | dBc |
| P RF1,2 | 1st Adjacent Channel Transmit Power 2 MHz (2 Mbps) | | -25 | | dBc |
| P RF2,2 | 2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps) | | -54 | | dBc |
| E vm | Error vector magnitude IEEE 802.15.4 | | 8 | | %rms |
| P harm2nd, IEEE 802.15.4 | 2nd harmonics in IEEE 802.15.4 mode | | -51 | | dBm |
| P harm3rd, IEEE 802.15.4 | 3rd harmonics in IEEE 802.15.4 | | -48 | | dBm |
Figure 133: Output power, 1 Mbps Bluetooth low energy mode, at maximum TXPOWER setting (typical values)
| Symbol | Description | Min. | Typ. | Max. | Units |
| ------------------------ | ------------------------------ | -------- | -------- | -------- | --------- |
| P ACP,R, IEEE 802.15.4 | IEEE 802.15.4 Relative adjacent Channel Power, offset > 3.5 MHz 19 | | -42 | | dBc |
| P ACP,A, IEEE 802.15.4 | IEEE 802 15.4 Absolute adjacent Channel Power, offset > 3.5 MHz 19 | | -46 | | dBm |
**Figure 133: Output power, 1 Mbps Bluetooth low energy mode, at maximum TXPOWER setting (typical values)**
19 Output power set to maximum TXPOWER setting, resolution bandwidth (RBW) set to 100 kHz, and transmitter Duty-Cycle approximately 85%.
Figure 134: Output power, 1 Mbps Bluetooth low energy mode, at 0 dBm TXPOWER setting (typical values)
## 6.20.15.5 Receiver operation
| Symbol | Description | Min. | Typ. | Max. | Units |
| ---------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| P RX,MAX | Maximum received signal strength at < 0.1% PER | | 0 | | dBm |
| P SENS,IT,1M | Sensitivity, 1 Mbps nRF mode ideal transmitter 20 | | -93 | | dBm |
| P SENS,IT,2M | Sensitivity, 2 Mbps nRF mode ideal transmitter 21 | | -89 | | dBm |
| P SENS,IT,SP,1M,BLE | Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≤ 37 bytes BER=1E-3 22 | | -95 | | dBm |
| P SENS,IT,LP,1M,BLE | Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≥ 128 bytes BER=1E-4 23 | | -94 | | dBm |
| P SENS,IT,SP,2M,BLE | Sensitivity, 2 Mbps BLE ideal transmitter, packet length ≤ 37 bytes | | -92 | | dBm |
| P SENS,IT,BLE LE125k | Sensitivity, 125 kbps BLE mode | | -103 | | dBm |
| P SENS,IT,BLE LE500k | Sensitivity, 500 kbps BLE mode | | -99 | | dBm |
| P SENS,IEEE 802.15.4 | Sensitivity in IEEE 802.15.4 mode | | -100 | | dBm |
Figure 135: Sensitivity, 1 Mbps Bluetooth low energy mode, Regulator = LDO (typical values)
## 6.20.15.6 RX selectivity
RX selectivity with equal modulation on interfering signal 24
| Symbol | Description | Min. | Typ. | Max. | Units |
| ---------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| C/I 1M,co-channel | 1Mbps mode, Co-Channel interference | | 9 | | dB |
| C/I 1M,-1MHz | 1 Mbps mode, Adjacent (-1 MHz) interference | | -2 | | dB |
| C/I 1M,+1MHz | 1 Mbps mode, Adjacent (+1 MHz) interference | | -10 | | dB |
| C/I 1M,-2MHz | 1 Mbps mode, Adjacent (-2 MHz) interference | | -19 | | dB |
| C/I 1M,+2MHz | 1 Mbps mode, Adjacent (+2 MHz) interference | | -42 | | dB |
| C/I 1M,-3MHz | 1 Mbps mode, Adjacent (-3 MHz) interference | | -38 | | dB |
| C/I 1M,+3MHz | 1 Mbps mode, Adjacent (+3 MHz) interference | | -48 | | dB |
| C/I 1M,±6MHz | 1 Mbps mode, Adjacent (≥6 MHz) interference | | -50 | | dB |
| C/I 1MBLE,co-channel | 1 Mbps BLE mode, Co-Channel interference | | 6 | | dB |
| C/I 1MBLE,-1MHz | 1 Mbps BLE mode, Adjacent (-1 MHz) interference | | -2 | | dB |
| C/I 1MBLE,+1MHz | 1 Mbps BLE mode, Adjacent (+1 MHz) interference | | -9 | | dB |
| C/I 1MBLE,-2MHz | 1 Mbps BLE mode, Adjacent (-2 MHz) interference | | -22 | | dB |
| C/I 1MBLE,+2MHz | 1 Mbps BLE mode, Adjacent (+2 MHz) interference | | -46 | | dB |
| C/I 1MBLE,>3MHz | 1 Mbps BLE mode, Adjacent (≥3 MHz) interference | | -50 | | dB |
| C/I 1MBLE,image | Image frequency interference | | -22 | | dB |
| C/I 1MBLE,image,1MHz | Adjacent (1 MHz) interference to in-band image frequency | | -35 | | dB |
| C/I 2M,co-channel | 2 Mbps mode, Co-Channel interference | | 10 | | dB |
| C/I 2M,-2MHz | 2 Mbps mode, Adjacent (-2 MHz) interference | | 6 | | dB |
| C/I 2M,+2MHz | 2 Mbps mode, Adjacent (+2 MHz) interference | | -19 | | dB |
| C/I 2M,-4MHz | 2 Mbps mode, Adjacent (-4 MHz) interference | | -20 | | dB |
| C/I 2M,+4MHz | 2 Mbps mode, Adjacent (+4 MHz) interference | | -44 | | dB |
| Symbol | Description | Min. | Typ. | Max. | Units |
| C/I 2M,-6MHz | 2 Mbps mode, Adjacent (-6 MHz) interference | | -42 | | dB |
| C/I 2M,+6MHz | 2 Mbps mode, Adjacent (+6 MHz) interference | | -42 | | dB |
| C/I 2M,≥12MHz | 2 Mbps mode, Adjacent (≥12 MHz) interference | | -52 | | dB |
| C/I 2MBLE,co-channel | 2 Mbps BLE mode, Co-Channel interference | | 6.8 | | dB |
| C/I 2MBLE,±2MHz | 2 Mbps BLE mode, Adjacent (±2 MHz) interference | | -10 | | dB |
| C/I 2MBLE,±4MHz | 2 Mbps BLE mode, Adjacent (±4 MHz) interference | | -45 | | dB |
| C/I 2MBLE,≥6MHz | 2 Mbps BLE mode, Adjacent (≥6 MHz) interference | | -48 | | dB |
| C/I 2MBLE,image | Image frequency interference | | -24 | | dB |
| C/I 2MBLE,image, 2MHz | Adjacent (2 MHz) interference to in-band image frequency | | -35 | | dB |
| C/I 125k BLE LR,co-channel | 125 kbps BLE LR mode, Co-Channel interference | | 4.4 | | dB |
| C/I 125k BLE LR,-1MHz | 125 kbps BLE LR mode, Adjacent (-1 MHz) interference | | -4 | | dB |
| C/I 125k BLE LR,+1MHz | 125 kbps BLE LR mode, Adjacent (+1 MHz) interference | | -12 | | dB |
| C/I 125k BLE LR,-2MHz | 125 kbps BLE LR mode, Adjacent (-2 MHz) interference | | -28 | | dB |
| C/I 125k BLE LR,+2MHz | 125 kbps BLE LR mode, Adjacent (+2 MHz) interference | | -50 | | dB |
| C/I 125k BLE LR,>3MHz | 125 kbps BLE LR mode, Adjacent (≥3 MHz) interference | | -55 | | dB |
| C/I 125k BLE LR,image | Image frequency interference | | -29 | | dB |
## 6.20.15.7 RX intermodulation
## RX intermodulation 25
| Symbol | Description | Min. | Typ. | Max. | Units |
| ------------------ | ------------------------------ | -------- | -------- | -------- | --------- |
| P IMD,5TH,1M | IMD performance, 1 Mbps, 5th offset channel, packet length ≤ 37 bytes | | -33 | | dBm |
| P IMD,5TH,1M,BLE | IMD performance, BLE 1 Mbps, 5th offset channel, packet length ≤ 37 bytes | | -30 | | dBm |
| P IMD,5TH,2M | IMD performance, 2 Mbps, 5th offset channel, packet length ≤ 37 bytes | | -33 | | dBm |
| P IMD,5TH,2M,BLE | IMD performance, BLE 2 Mbps, 5th offset channel, packet length ≤ 37 bytes | | -31 | | dBm |
## 6.20.15.8 Radio timing
| Symbol | Description | Min. | Typ. | Max. | Units |
| ---------------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| t TXEN,BLE,1M | Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE and 150 μs TIFS) | 140 | | 140 | μs |
| t TXEN,FAST,BLE,1M | Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up and 150 μs TIFS) | 40 | | 40 | μs |
| t TXDIS,BLE,1M | When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit | 6 | | 6 | μs |
| t RXEN,BLE,1M | Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE) | 140 | | 140 | μs |
| t RXEN,FAST,BLE,1M | Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up) | 40 | | 40 | μs |
| t RXDIS,BLE,1M | When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit | 0 | | 0 | μs |
| t TXDIS,BLE,2M | When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit | 4 | | 4 | μs |
| t RXDIS,BLE,2M | When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit | 0 | | 0 | μs |
| t TXEN,IEEE 802.15.4 | Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4) | 130 | | 130 | μs |
| Symbol | Description | Min. | Typ. | Max. | Units |
| t TXEN,FAST,IEEE 802.15.4 | Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 with fast ramp-up) | 40 | | 40 | μs |
| t TXDIS,IEEE 802.15.4 | When in TX, delay between DISABLE task and DISABLED event (IEEE 802.15.4) | 21 | | 21 | μs |
| t RXEN,IEEE 802.15.4 | Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4) | 130 | | 130 | μs |
| t RXEN,FAST,IEEE 802.15.4 | Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 with fast ramp-up) | 40 | | 40 | μs |
| t RXDIS,IEEE 802.15.4 | When in RX, delay between DISABLE task and DISABLED event (IEEE 802.15.4) | 0.5 | | 0.5 | μs |
| t RX-to-TX turnaround | Maximum TX-to-RX or RX-to-TX turnaround time in IEEE 802.15.4 mode | | 40 | | μs |
## 6.20.15.9 Received signal strength indicator (RSSI) specifications
| Symbol | Description | Min. | Typ. | Max. | Units |
| ----------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| RSSI ACC | RSSI accuracy valid range -90 to -20 dBm | | ±2 | | dB |
| RSSI RESOLUTION | RSSI resolution | | 1 | | dB |
| RSSI PERIOD | RSSI sampling time from RSSI_START task | | 0.25 | | μs |
| RSSI SETTLE | RSSI settling time after signal level change | | 15 | | μs |
## 6.20.15.10 Jitter
| Symbol | Description | Min. | Typ. | Max. | Units |
| ------------------ | ------------------------------ | -------- | -------- | -------- | --------- |
| t DISABLEDJITTER | Jitter on DISABLED event relative to END event when shortcut between END<br>and DISABLE is enabled | | 0.25 | | μs |
| t READYJITTER | Jitter on READY event relative to TXEN and RXEN task | | 0.25 | | μs |
## 6.20.15.11 IEEE 802.15.4 energy detection constants
| Symbol | Description | Min. | Typ. | Max. | Units |
| -------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| ED_RSSISCALE | Scaling value when converting between hardware-reported value and dBm | 4 | 4 | 4 | |
| ED_RSSIOFFS | Offset value when converting between hardware-reported value and dBm | -92 | -92 | -92 | |
## 6.21 RNG - Random number generator
The Random number generator (RNG) generates true non-deterministic random numbers based on internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value.
Figure 136: Random number generator
The RNG is started by triggering the START task and stopped by triggering the STOP task. When started, new random numbers are generated continuously and written to the VALUE register when ready. A VALRDY event is generated for every new random number that is written to the VALUE register. This means that after a VALRDY event is generated, the CPU has the time until the next VALRDY event to read out the random number from the VALUE register before it is overwritten by a new random number.
**Figure 136: Random number generator**
## 6.21.1 Bias correction
A bias correction algorithm is employed on the internal bit stream to remove any bias toward 1 or 0 . The bits are then queued into an eight-bit register for parallel readout from the VALUE register.
It is possible to enable bias correction in the CONFIG register. This will result in slower value generation, but will ensure a statistically uniform distribution of the random values.
## 6.21.2 Speed
The time needed to generate one random byte of data is unpredictable, and may vary from one byte to the next. This is especially true when bias correction is enabled.
## 6.21.3 Registers
| Instance | Base address | Description |
| ------------ | ---------------- | ------------------------- |
| RNG | 0x4000D000 | Random number generator |
| Register | Offset | Description |
| --------------- | ---------- | ------------------------------ |
| TASKS_START | 0x000 | Task starting the random number generator |
| TASKS_STOP | 0x004 | Task stopping the random number generator |
| EVENTS_VALRDY | 0x100 | Event being generated for every new random number written to the VALUE register |
| SHORTS | 0x200 | Shortcuts between local events and tasks |
| INTENSET | 0x304 | Enable interrupt |
| INTENCLR | 0x308 | Disable interrupt |
| CONFIG | 0x504 | Configuration register |
| VALUE | 0x508 | Output random number |
## 6.21.3.1 TASKS\_START
Address offset: 0x000
Task starting the random number generator
## 6.21.3.2 TASKS\_STOP
Address offset: 0x004
Task stopping the random number generator
## 6.21.3.3 EVENTS\_VALRDY
Address offset: 0x100
Event being generated for every new random number written to the VALUE register
## 6.21.3.4 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
## 6.21.3.5 INTENSET
Address offset: 0x304
Enable interrupt
## 6.21.3.6 INTENCLR
Address offset: 0x308
Disable interrupt
## 6.21.3.7 CONFIG
Address offset: 0x504
Configuration register
## 6.21.3.8 VALUE
Address offset: 0x508
Output random number
## 6.21.4 Electrical specification
## 6.21.4.1 RNG Electrical Specification
| Symbol | Description | Min. | Typ. | Max. | Units |
| ------------- | ------------------------------ | -------- | -------- | -------- | --------- |
| t RNG,START | Time from setting the START task to generation begins. This is a one-time delay on START signal and does not apply between samples. | | 128 | | μs |
| t RNG,RAW | Run time per byte without bias correction. Uniform distribution of 0 and 1 not guaranteed. | | 30 | | μs |
| t RNG,BC | Run time per byte with bias correction. Uniform distribution of 0 and 1 is guaranteed. Time to generate a byte cannot be guaranteed. | | 120 | | μs |
## 6.22 RTC - Real-time counter
The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock source (LFCLK).
Figure 137: RTC block schematic
The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick event generator for low power, tickless RTOS implementation.
## 6.22.1 Clock source
The RTC runs off the LFCLK.
The COUNTER resolution is 30.517 μs. Depending on the source, the RTC is able to run while the HFCLK is OFF and PCLK16M is not available.
The software has to explicitly start LFCLK before using the RTC.
See CLOCK - Clock control on page 157 for more information about clock sources.
## 6.22.2 Resolution versus overflow and the PRESCALER
Counter increment frequency:
fRTC [kHz] = 32.768 / (PRESCALER + 1 )
The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only once the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect.
The PRESCALER is restarted on START, CLEAR, and TRIGOVRFLW, meaning the prescaler value is latched to an internal register (<<PRESC>>) on these tasks.
Examples of different frequency configurations are as following:
- Desired COUNTER frequency 100 Hz (10 ms counter period)
PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327
fRTC = 99.9 Hz
10009.576 μs counter period
- Desired COUNTER frequency 8 Hz (125 ms counter period)
PRESCALER = round(32.768 kHz / 8 Hz) - 1 = 4095
fRTC = 8 Hz
## 125 ms counter period
Table 38: RTC resolution versus overflow
| Prescaler | Counter resolution | Overflow |
| ------------- | ---------------------- | ---------------- |
| 0 | 30.517 μs | 512 seconds |
| 2 8 -1 | 7812.5 μs | 131072 seconds |
| 2 12 -1 | 125 ms | 582.542 hours |
## 6.22.3 COUNTER register
The COUNTER increments on LFCLK when the internal PRESCALER register (<<PRESC>>) is 0x00. <<PRESC>> is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment of the COUNTER. The TICK event is disabled by default.
SysClk
LFClk
PRESC
<<PRESC>>
0x000
0x000
0x000
0x000
TICK
COUNTER
0x000002
0x000003
0x000
0x000001
0x000000
Figure 138: Timing diagram - COUNTER\_PRESCALER\_0
SysClk
LFClk
PRESC
<<PRESC>>
0x001
0x001
0x000
0x001
TICK
COUNTER
0x000001
0x000
0x000000
Figure 139: Timing diagram - COUNTER\_PRESCALER\_1
**Figure 139: Timing diagram - COUNTER_PRESCALER_1**
## 6.22.4 Overflow features
The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition. OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0.
Note: The OVRFLW event is disabled by default.
## 6.22.5 TICK event
The TICK event enables low power tickless RTOS implementation as it optionally provides a regular interrupt source for a RTOS without the need to use the ARM SysTick feature.
Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active.
Note: The TICK event is disabled by default.
## 6.22.6 Event control feature
To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK being requested when those events are triggered. This is managed using the EVTEN register.
For example, if the TICK event is not required for an application, this event should be disabled as it is frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for long durations.
This means that the RTC implements a slightly different task and event system compared to the standard system described in Peripheral interface on page 173. The RTC task and event system is illustrated in Tasks, events, and interrupts in the RTC on page 662.
Figure 140: Tasks, events, and interrupts in the RTC
## 6.22.7 Compare feature
There are a number of Compare registers.
For more information, see Registers on page 667.
When setting a compare register, the following behavior of the RTC compare event should be noted:
- If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
CC[0]
COMPARE[0]
0x000
X
0x000000
0x000000
0
CLEAR
Figure 141: Timing diagram - COMPARE\_CLEAR
- If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
CC[0]
COMPARE[0]
0x000
N-1
N
N
0
START
N+1
Figure 142: Timing diagram - COMPARE\_START
- COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N.
SysClk
LFClk
PRESC
COUNTER
CC[0]
COMPARE[0]
0x000
N-2
N-1
N
N+1
N
0
1
Figure 143: Timing diagram - COMPARE
- If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2.
SysClk
LFClk
PRESC
COUNTER
CC[0]
COMPARE[0]
0x000
N-1
N
N+1
N+2
0
1
X
N+2
> 62.5 ns
Figure 144: Timing diagram - COMPARE\_N+2
- If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
CC[0]
COMPARE[0]
0x000
N-2
N-1
N
N+1
0
X
N+1
≥ 0
Figure 145: Timing diagram - COMPARE\_N+1
- If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a match may trigger on the previous CC value before the new value takes effect. If the current CC value is greater than N+2 when the new value is written, there will be no event due to the old value.
SysClk
LFClk
PRESC
COUNTER
CC[0]
COMPARE[0]
0x000
N-2
N-1
N
N+1
0
1
N
X
≥ 0
Figure 146: Timing diagram - COMPARE\_N-1
## 6.22.8 TASK and EVENT jitter/delay
Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not synchronous to the faster PCLK16M.
Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register which is actually modified each time the RTC ticks. These registers must be synchronised between clock domains (PCLK16M and LFCLK).
The following is a summary of the jitter introduced on tasks and events.
Table 39: RTC jitter magnitudes on tasks
Table 40: RTC jitter magnitudes on events
Note: 32.768 kHz clock jitter is additional to the numbers provided above.
CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and rising of the LFCLK. This is between 15.2585 μs and 45.7755 μs - rounded to 15 μs and 46 μs for the remainder of the section.
Figure 147: Timing diagram - DELAY\_CLEAR
**Note: 32.768 kHz clock jitter is additional to the numbers provided above.**
Figure 148: Timing diagram - DELAY\_STOP
**Figure 147: Timing diagram - DELAY_CLEAR**
The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. In some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to ~250 μs. The software should therefore wait for the first TICK if it has to make sure the RTC is running. Sending a
26 Assumes RTC runs continuously between these events.
TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK, but the update will then be delayed by the same amount of time of up to ~250 μs. The figures show the shortest and longest delays on the START task which appears as a +/-15 μs jitter on the first COUNTER increment.
Figure 150: Timing diagram - JITTER\_START+
**Figure 150: Timing diagram - JITTER_START+**
## 6.22.9 Reading the COUNTER register
To read the COUNTER register, the internal <<COUNTER>> value is sampled.
To ensure that the <<COUNTER>> is safely sampled (considering an LFCLK transition may occur during a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five PCLK16M clock cycles.
**Figure 151: Timing diagram - COUNTER_READ**
Figure 151: Timing diagram - COUNTER\_READ
## 6.22.10 Registers
| Instance | Base address | Description |
| ------------ | ---------------- | --------------------- |
| RTC0 | 0x4000B000 | Real-time counter 0 |
| RTC1 | 0x40011000 | Real-time counter 1 |
| RTC2 | 0x40024000 | Real-time counter 2 |
## Configuration
| Instance | Configuration |
| ------------ | ------------------------------ |
| RTC0 | CC[0..2] implemented, CC[3] not implemented |
| RTC1 | CC[0..3] implemented |
| RTC2 | CC[0..3] implemented |
| Register | Offset | Description |
| ------------------- | ---------- | ------------------------------ |
| TASKS_START | 0x000 | Start RTC COUNTER |
| TASKS_STOP | 0x004 | Stop RTC COUNTER |
| TASKS_CLEAR | 0x008 | Clear RTC COUNTER |
| TASKS_TRIGOVRFLW | 0x00C | Set COUNTER to 0xFFFFF0 |
| EVENTS_TICK | 0x100 | Event on COUNTER increment |
| EVENTS_OVRFLW | 0x104 | Event on COUNTER overflow |
| EVENTS_COMPARE[0] | 0x140 | Compare event on CC[0] match |
| EVENTS_COMPARE[1] | 0x144 | Compare event on CC[1] match |
| EVENTS_COMPARE[2] | 0x148 | Compare event on CC[2] match |
| EVENTS_COMPARE[3] | 0x14C | Compare event on CC[3] match |
| INTENSET | 0x304 | Enable interrupt |
| INTENCLR | 0x308 | Disable interrupt |
| EVTEN | 0x340 | Enable or disable event routing |
| EVTENSET | 0x344 | Enable event routing |
| EVTENCLR | 0x348 | Disable event routing |
| COUNTER | 0x504 | Current COUNTER value |
| PRESCALER | 0x508 | 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. |
| CC[0] | 0x540 | Compare register 0 |
| CC[1] | 0x544 | Compare register 1 |
| CC[2] | 0x548 | Compare register 2 |
| CC[3] | 0x54C | Compare register 3 |
## 6.22.10.1 TASKS\_START
Address offset: 0x000
Start RTC COUNTER
## 6.22.10.2 TASKS\_STOP
Address offset: 0x004
Stop RTC COUNTER
## 6.22.10.3 TASKS\_CLEAR
Address offset: 0x008
Clear RTC COUNTER
## 6.22.10.4 TASKS\_TRIGOVRFLW
Address offset: 0x00C
Set COUNTER to 0xFFFFF0
## 6.22.10.5 EVENTS\_TICK
Address offset: 0x100
Event on COUNTER increment
## 6.22.10.6 EVENTS\_OVRFLW
Address offset: 0x104
Event on COUNTER overflow
## 6.22.10.7 EVENTS\_COMPARE[0]
Address offset: 0x140
Compare event on CC[0] match
## 6.22.10.8 EVENTS\_COMPARE[1]
Address offset: 0x144
Compare event on CC[1] match
## 6.22.10.9 EVENTS\_COMPARE[2]
Address offset: 0x148
Compare event on CC[2] match
## 6.22.10.10 EVENTS\_COMPARE[3]
Address offset: 0x14C
Compare event on CC[3] match
## 6.22.10.11 INTENSET
Address offset: 0x304
Enable interrupt
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | | | | | | | 0 |
| ------------------ | ------------------ | ---------- | ------------------------------ | ---- | ---- | ---- | ---- | ---- | ------- | ----- |
| ID | | | | | | | B | A | | |
| Reset 0x00000000 | Reset 0x00000000 | | 0 0 | 0 | 0 | 0 | 0 | | 0 0 0 | |
| ID | R/W Field | Value ID | Value | | | | | | | |
| A | RW | TICK<br>Set<br>Disabled<br>Enabled | 1<br>0<br>1 | | | | | | | |
| B | RW<br>OVRFLW | Disabled<br>Enabled | 0<br>1 | | | | | | | |
| C | RW COMPARE[0] | | | | | | | | | |
| D | COMPARE[1]<br>RW | Set<br>Disabled | 1<br>0 | | | | | | | |
| E | RW | | 1 | | | | | | | |
| F | COMPARE[2]<br>COMPARE[3]<br>RW | Set<br>Disabled<br>Enabled<br>Set<br>Disabled | 0<br>1<br>1<br>0 | | | | | | | |
## 6.22.10.12 INTENCLR
Address offset: 0x308
Disable interrupt
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | | | | | | | | 0 |
| ------------------ | ------------------ | ------------ | ------------------------------ | ------- | ----- | ---------------- | ------- | ------------ | ---- | ----- | ----- |
| ID | | | | | | | | | B | | A |
| Reset 0x00000000 | Reset 0x00000000 | | 0 | 0 | 0 0 | 0 0 | 0 0 0 | 0 0 0 0 | | 0 0 | |
| ID | R/W Field | Value ID | | Value | | Description | | | | | |
| A | RW TICK | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | Write<br>Disable<br>Read: Disabled<br>Read: Enabled | | TICK | | | |
| B | RW | OVRFLW<br>Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | Write<br>Disable<br>Read: Disabled<br>Read: | | OVRFLW | | | |
| C RW | COMPARE[0] | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | Write<br>Disable<br>Read: Disabled<br>Read: Enabled | | COMPARE[0] | | | |
| D RW | COMPARE[1] | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | Write '1'<br>Disable<br>Read: Disabled<br>Read: Enabled | | COMPARE[1] | | | |
| E | RW COMPARE[2] | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | Write<br>Disable<br>Read: Disabled<br>Read: Enabled | | COMPARE[2] | | | |
| F | RW | COMPARE[3]<br>Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | Write<br>Disable<br>Read:<br>Read: | | COMPARE[3] | | | |
## 6.22.10.13 EVTEN
## Address offset: 0x340
Enable or disable event routing
| Bit number | 31 30 29 | Bit number |
| -------------- | ------------ | -------------- |
## 6.22.10.14 EVTENSET
Address offset: 0x344
Enable event routing
| Bit number | | 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ------------------- | ------------------------------ | ------------------------------ |
| ID | | | E D B |
| Reset 0x00000000 | Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value |
| A RW | TICK | Disabled 0 Enabled 1 | event |
| B RW C RW | OVRFLW COMPARE[0] | Disabled 0 Enabled 1 Set 1 Disabled 0 Enabled 1 Set | event event 1 0 |
| D RW | COMPARE[1] | Disabled Enabled | 1 |
| E RW | | Set | 1 0 |
| | COMPARE[2] | Disabled Enabled 1 | 1 |
| F RW | | Set Disabled | 0 |
| | COMPARE[3]<br>Set | Enabled | 1<br>1 |
## 6.22.10.15 EVTENCLR
Address offset: 0x348
Disable event routing
| Bit number | | 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 | | 1 0 |
| ------------------ | ------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID | | | E D C | F | B A |
| Reset 0x00000000 | Reset 0x00000000 | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 | 0 0 0 0 0 0 0 |
| ID R/W | Field | Value ID | Value | Description | |
| A RW | TICK | Disabled 0 | Write '1' Read: Disabled | to disable event routing for Enabled | event TICK |
| B RW C RW | OVRFLW | Disabled 0 Enabled 1 Clear 1 0 | Write '1' to disable event Read: Disabled Read: Enabled Disable Write '1' to disable event routing for event COMPARE[0] | routing for | event OVRFLW |
| | COMPARE[0] | Disabled Enabled 1 Clear 1 | Read: Disabled Read: Enabled Disable | | |
| D RW | | 0 1 | Read: Disabled Read: Enabled | Write '1' to disable event routing | event |
| | COMPARE[1] | Disabled Enabled | | Disable | for COMPARE[1] |
| E RW | COMPARE[2] | Clear 0 1 | 1 | '1' to disable event Disabled | Write '1' to disable event routing for event COMPARE[2] Read: Disabled Read: Enabled |
| F | | Disabled Enabled Clear | 1 0 | Read: | Disable |
| RW | COMPARE[3]<br>Clear | Disabled<br>Enabled | 1<br>1 | Read: Enabled<br>Disable | Write routing for event COMPARE[3] |
## 6.22.10.16 COUNTER
Address offset: 0x504
Current COUNTER value
## 6.22.10.17 PRESCALER
Address offset: 0x508
12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped.
Counter value
## 6.22.10.18 CC[0]
Address offset: 0x540
Compare register 0
## 6.22.10.19 CC[1]
Address offset: 0x544
Compare register 1
## 6.22.10.20 CC[2]
Address offset: 0x548
Compare register 2
A
RW
COMPARE
## 6.22.10.21 CC[3]
Address offset: 0x54C
Compare register 3
Compare value
## 6.23 SAADC - Successive approximation analog-todigital converter
The SAADC peripheral is a differential successive approximation register (SAR) analog-to-digital converter.
The main features of the SAADC are the following:
- 8/10/12-bit resolution, 14-bit resolution with oversampling
- Up to eight channels for single-ended inputs and four channels for differential inputs, depending on the package variant
- Full scale input range (0 V to VDD)
- Multiple inputs
- Input pins AIN0 to AIN7
- VDD input
- VDDHDIV5 input
- Individual reference selection for each channel
- VDD
- Internal reference
- Continuous sampling
- Output samples automatically stored in RAM using EasyDMA as 16-bit two's complement values
- Internal resistor string
Figure 152: Block diagram
## 6.23.1 Channel and input configuration
Up to eight SAADC channels can be enabled and configured for SAADC.
A channel is connected to an analog input using the registers CH[n].PSELP and CH[n].PSELN. Each SAADC channel can be configured to use either single-ended mode or differential input mode. Setting register CH[n].PSELP enables the corresponding channel. Setting register CH[n].PSELN has no effect for singleended channels.
Register CH[n].CONFIG configures SAADC channels. In Single-ended mode, the negative channel input is shorted to ground internally. In Single-ended mode, the assumption is that the internal ground of the ADC is the same as the external ground that the measured voltage is referred to. This makes SAADC sensitive to ground bounce on the PCB. To avoid this, use the differential input mode instead.
Before sampling is started, the length and location of the memory buffer in RAM must be configured. Use registers RESULT.MAXCNT on page 714 and RESULT.PTR on page 713 to configure the length and location where the output values are to be written. The START task must be triggered to apply the configuration. See EasyDMA on page 679 for details on memory configuration and how the results are stored in memory.
SAADC is stopped by triggering the STOP task. The STOP task also terminates the ongoing sampling. SAADC generates a STOPPED event when it has stopped. If SAADC is not started when the STOP task is triggered, the STOPPED event is still generated.
## 6.23.1.1 Shared resources
The SAADC peripheral shares analog resources with other analog peripherals.
While it is possible to use COMP and SAADC at the same time, selecting the same analog input pin for both peripherals is not supported.
## 6.23.1.2 Acquisition time
To sample input voltage, SAADC connects a capacitor to the input, as shown in the following figure.
Figure 153: Simplified SAADC sample network
Acquisition time is the amount of time the capacitor is connected, see the TACQ field in the CH[n].CONFIG register. The required acquisition time depends on the source resistance Rsource. For high source resistance, increase the acquisition time according to the following table:
Table 41: Acquisition time
**Figure 153: Simplified SAADC sample network**
| TACQ [μs] | Maximum source resistance [kΩ] |
| ------------- | ------------------------------ |
| 3 | 10 |
| 5 | 40 |
| 10 | 100 |
| 15 | 200 |
| 20 | 400 |
| 40 | 800 |
When using VDDHDIV5 as input, the acquisition time must be 10 μs or longer.
## 6.23.1.3 Internal resistor string (resistor ladder)
SAADC has an internal resistor string for positive and negative input. The resistors are controlled in register CH[n].CONFIG.
The following figure illustrates the resistor ladder for positive and negative input:
Figure 154: Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP)
## 6.23.1.4 Reference voltage and gain settings
Each SAADC channel can have individual reference and gain settings. These settings are configured in register CH[n].CONFIG.
The following configuration options are available:
- VDD/4 or internal 0.6 V reference
- Gain ranging from 1/6 to 4
The gain setting controls the effective input range of SAADC, as shown in the following equation:
Input range = (±0.6 V or ±VDD/4)/gain
For example, selecting VDD as reference, single-ended input (grounded negative input), and a gain of 1/4 gives the following input range:
Input range = (VDD/4)/(1/4) = VDD
With internal reference, single-ended input (grounded negative input) and a gain of 1/6, the input range is the following:
Input range = (0.6 V)/(1/6) = 3.6 V
Inputs AIN0 to AIN7 cannot exceed VDD or be lower than VSS.
## 6.23.2 Operation modes
The SAADC configuration supports Single-channel Single Conversion mode, Single-channel Continuous Conversion mode, and scan mode. Only one mode can be enabled at a time.
Single-channel sampling happens in either Single Conversion mode or Continuous Conversion mode. Scan mode is entered when more than one channel is enabled.
Oversampling can be used to improve the signal-to-noise ratio (SNR). It is not recommended to use oversampling for scan mode. For more information about oversampling, see Oversampling on page 678.
## 6.23.2.1 Single-channel Single Conversion mode
SAADC performs one conversion of a single channel and stops once complete.
This mode of operation is configured by enabling only one of the available channels defined by the registers CH[n].PSELP, CH[n].PSELN, and CH[n].CONFIG. When the SAMPLE task is triggered, SAADC starts sampling the input voltage.
A DONE event signals that the sample was taken. In this mode, the RESULTDONE and DONE events are equal when oversampling does not happen. Both events can occur before EasyDMA transfers the value to RAM. For more information, see EasyDMA on page 679. The END event is generated when RESULT.MAXCNT on page 714 values are transferred to RAM.
## 6.23.2.2 Single-channel Continuous Conversion mode
In Single-channel Continuous Conversion mode, a single channel is sampled continuously.
Continuous sampling is achieved with an internal timer in the SAADC peripheral. The register SAMPLERATE on page 713 configures the Single-channel Continuous Conversion mode and sample rate.
The sample rate must fulfill the following criteria:
fSAMPLE < 1 / (tACQ + tconv)
When Single-channel Continuous Conversion mode is selected, SAADC is started by triggering the SAMPLE task once. Triggering the STOP task stops sampling. A DONE event signals that one sample was taken. In this mode, the RESULTDONE and DONE events are equal when oversampling does not happen. Both events may occur before EasyDMA transfers the value to RAM. For more information, see EasyDMA on page 679. The END event is generated when RESULT.MAXCNT on page 714 values are transferred to RAM.
## 6.23.2.3 Scan mode
If more than one channel is enabled, SAADC functions in scan mode.
In scan mode, one SAMPLE task triggers one conversion per enabled channel.
The time it takes to sample all channels is less than the sum of the conversion time of all enabled channels. The conversion time for a channel is defined as the sum of the acquisition time tACQ and the conversion time tCONV.
The events DONE and RESULTDONE are generated when one sample is taken. Both events may occur before EasyDMA transfers the values into RAM, see EasyDMA on page 679 for more information.
Note: Continuous conversion mode is not supported in scan mode.
## 6.23.2.4 Oversampling
An accumulator in SAADC can be used to find the average of several analog input samples. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling does not improve the integral nonlinearity (INL) or differential non-linearity (DNL).
Oversampling is configured in register OVERSAMPLE. When oversampling, 2 OVERSAMPLE samples are averaged before one result is transferred to memory. The mode used to sample the input determines when and how those samples are taken.
When oversampling is configured, DONE event is generated for every input sample taken. RESULTDONE event is generated for every averaged value ready to be transferred into RAM. END event is generated when RESULT.MAXCNT averaged values are transferred into RAM.
Note: Oversampling should only be used when a single input channel is enabled, as averaging is performed over all enabled channels.
## 6.23.3 Digital output
The digital output value is calculated using the following formula.
RESULT = [V(P) - V(N)] * (GAIN/REFERENCE) * 2 (RESOLUTION - m)
where V(P) is the voltage at input P , V(N) is the voltage at input N, GAIN is the selected gain, REFERENCE is the selected reference voltage, RESOLUTION is output resolution in bits, as configured in register RESOLUTION on page 712, and m being 0 for single-ended channels and 1 for differential channels.
Results are sign extended to 16 bits and stored in RAM in little-endian byte order.
Results generated by SAADC deviate due to DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the gain block, settling errors due to high source impedance, and sampling jitter. DC errors affect the most for battery measurement.
## 6.23.4 EasyDMA
SAADC resources are started by triggering the START task. The SAADC uses EasyDMA to store results in a buffer in RAM.
Registers RESULT.PTR on page 713 and RESULT.MAXCNT on page 714 must be configured before SAADC is started.
The result buffer is located at the address specified in register RESULT.PTR on page 713. This register is double-buffered, and it can be updated and prepared for the next START task immediately after the STARTED event is generated. Register RESULT.MAXCNT on page 714 specifies the size of the result buffer. SAADC generates an END event when the result buffer is full, as shown in the following figure.
Figure 155: SAADC
The following figure provides an example of results in Data RAM with an even RESULT.MAXCNT on page 714 and channels 1, 2, and 5 enabled.
Figure 156: Example of RAM placement (even RESULT.MAXCNT), channels 1, 2, and 5 enabled
| | 31 16 | 15 |
| ------------------------------ | ------------------- | ------------------- |
| RESULT.PTR | CH[2] 1 st result | CH[1] 1 st result |
| RESULT.PTR + 4 | CH[1] 2 nd result | CH[5] 1 st result |
| RESULT.PTR + 8 | CH[5] 2 nd result | CH[2] 2 nd result |
| | (…) | (…) |
| RESULT.PTR + 2*RESULT.MAXCNT - 4 | CH[5] last result | CH[2] last result |
The following figure provides an example of results in Data RAM with an odd RESULT.MAXCNT on page 714 and channels 1, 2, and 5 enabled.
Figure 157: Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2, and 5 enabled
| | 31 | 15 |
| ------------------------------ | ------------------- | ------------------- |
| RESULT.PTR | CH[2] 1 st result | CH[1] 1 st result |
| RESULT.PTR + 4 | CH[1] 2 nd result | CH[5] 1 st result |
| RESULT.PTR + 8 | CH[5] 2 nd result | CH[2] 2 nd result |
| | (…) | (…) |
| RESULT.PTR + 2*RESULT.MAXCNT - 2 | | CH[5] last result |
The last 32-bit word is populated with only one 16-bit result.
See Memory on page 21 for more information about the different memory regions.
EasyDMA is finished accessing RAM when events END or STOPPED are generated. To see the number of results transferred to the RAM result buffer since the START task was triggered, read register RESULT.AMOUNT on page 714.
## 6.23.5 Event monitoring using limits
Using limits allows event monitoring on channels.
A high and low limit can be configured in the CH[n].LIMIT register. The high limit must be higher than or equal to the low limit.
Relevant events are generated when the conversion results (sampled input signals) are outside of the defined limits. It is not possible to generate an event when the input signal is inside a defined range by switching the high and low limit. An example of event monitoring using limits is illustrated in the following figure:
Figure 158: Event monitoring on channel[n] using limits
Limit comparison does not need to be enabled. If event monitoring is not required, related events should be ignored.
## 6.23.6 Calibration
The SAADC peripheral has a temperature dependent offset.
It is recommended to calibrate SAADC at least once before use, and recalibrate when the ambient temperature changes by more than 10°C.
Offset calibration is started by triggering the CALIBRATEOFFSET task. The CALIBRATEDONE event is generated when calibration is finished.
## 6.23.7 Registers
| Instance | Base address | Description |
| ------------ | ---------------- | ----------------------------- |
| SAADC | 0x40007000 | Analog to digital converter |
| Register | Offset | Description |
| ----------------------- | ---------- | ------------------------------ |
| TASKS_START | 0x000 | Starts the SAADC and prepares the result buffer in RAM |
| TASKS_SAMPLE | 0x004 | Takes one SAADC sample |
| TASKS_STOP | 0x008 | Stops the SAADC and terminates all on-going conversions |
| TASKS_CALIBRATEOFFSET | 0x00C | Starts offset auto-calibration |
| EVENTS_STARTED | 0x100 | The SAADC has started |
| Register | Offset | Description |
| EVENTS_END | 0x104 | The SAADC has filled up the result buffer |
| EVENTS_DONE | 0x108 | A conversion task has been completed. Depending on the configuration, be needed for a result to be transferred to RAM. |
| EVENTS_RESULTDONE | 0x10C | Result ready for transfer to RAM |
| EVENTS_CALIBRATEDONE | 0x110 | Calibration is complete |
| EVENTS_STOPPED | 0x114 | The SAADC has stopped |
| EVENTS_CH[0].LIMITH | 0x118 | Last result is equal or above CH[0].LIMIT.HIGH |
| EVENTS_CH[0].LIMITL | 0x11C | Last result is equal or below CH[0].LIMIT.LOW |
| EVENTS_CH[1].LIMITH | 0x120 | Last result is equal or above CH[1].LIMIT.HIGH |
| EVENTS_CH[1].LIMITL | 0x124 | Last result is equal or below CH[1].LIMIT.LOW |
| EVENTS_CH[2].LIMITH | 0x128 | Last result is equal or above CH[2].LIMIT.HIGH |
| EVENTS_CH[2].LIMITL | 0x12C | Last result is equal or below CH[2].LIMIT.LOW |
| EVENTS_CH[3].LIMITH | 0x130 | Last result is equal or above CH[3].LIMIT.HIGH |
| EVENTS_CH[3].LIMITL | 0x134 | Last result is equal or below CH[3].LIMIT.LOW |
| EVENTS_CH[4].LIMITH | 0x138 | Last result is equal or above CH[4].LIMIT.HIGH |
| EVENTS_CH[4].LIMITL | 0x13C | Last result is equal or below CH[4].LIMIT.LOW |
| EVENTS_CH[5].LIMITH | 0x140 | Last result is equal or above CH[5].LIMIT.HIGH |
| EVENTS_CH[5].LIMITL | 0x144 | Last result is equal or below CH[5].LIMIT.LOW |
| EVENTS_CH[6].LIMITH | 0x148 | Last result is equal or above CH[6].LIMIT.HIGH |
| EVENTS_CH[6].LIMITL | 0x14C | Last result is equal or below CH[6].LIMIT.LOW |
| EVENTS_CH[7].LIMITH | 0x150 | Last result is equal or above CH[7].LIMIT.HIGH |
| EVENTS_CH[7].LIMITL | 0x154 | Last result is equal or below CH[7].LIMIT.LOW |
| INTEN | 0x300 | Enable or disable interrupt |
| INTENSET | 0x304 | Enable interrupt |
| INTENCLR | 0x308 | Disable interrupt |
| STATUS | 0x400 | Status |
| ENABLE | 0x500 | Enable or disable SAADC |
| CH[0].PSELP | 0x510 | Input positive pin selection for CH[0] |
| CH[0].PSELN | 0x514 | Input negative pin selection for CH[0] |
| CH[0].CONFIG | 0x518 | Input configuration for CH[0] |
| CH[0].LIMIT | 0x51C | High/low limits for event monitoring of a channel |
| CH[1].PSELP | 0x520 | Input positive pin selection for CH[1] |
| CH[1].PSELN | 0x524 | Input negative pin selection for CH[1] |
| CH[1].CONFIG | 0x528 | Input configuration for CH[1] |
| CH[1].LIMIT | 0x52C | High/low limits for event monitoring of a channel |
| CH[2].PSELP | 0x530 | Input positive pin selection for CH[2] |
| CH[2].PSELN | 0x534 | Input negative pin selection for CH[2] |
| CH[2].CONFIG | 0x538 | Input configuration for CH[2] |
| CH[2].LIMIT | 0x53C | High/low limits for event monitoring of a channel |
| CH[3].PSELP | 0x540 | Input positive pin selection for CH[3] |
| CH[3].PSELN | 0x544 | Input negative pin selection for CH[3] |
| CH[3].CONFIG | 0x548 | Input configuration for CH[3] |
| CH[3].LIMIT | 0x54C | High/low limits for event monitoring of a channel |
| CH[4].PSELP | 0x550 | Input positive pin selection for CH[4] |
| CH[4].PSELN | 0x554 | Input negative pin selection for CH[4] |
| CH[4].CONFIG | 0x558 | Input configuration for CH[4] |
| CH[4].LIMIT | 0x55C | High/low limits for event monitoring of a channel |
| CH[5].PSELP | 0x560 | Input positive pin selection for CH[5] |
| CH[5].PSELN | 0x564 | Input negative pin selection for CH[5] |
| CH[5].CONFIG | 0x568 | Input configuration for CH[5] |
| CH[5].LIMIT | 0x56C | High/low limits for event monitoring of a channel |
| CH[6].PSELP CH[6].PSELN | 0x570 0x574 | Input positive pin selection for CH[6] Input negative pin selection for CH[6] |
| Register | Offset | Description |
| CH[6].CONFIG | 0x578 | Input configuration for CH[6] |
| CH[6].LIMIT | 0x57C | High/low limits for event monitoring of a channel |
| CH[7].PSELP | 0x580 | Input positive pin selection for CH[7] |
| CH[7].PSELN | 0x584 | Input negative pin selection for CH[7] |
| CH[7].CONFIG | 0x588 | Input configuration for CH[7] |
| CH[7].LIMIT | 0x58C | High/low limits for event monitoring of a channel |
| RESOLUTION | 0x5F0 | Resolution configuration |
| OVERSAMPLE | 0x5F4 | Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. |
| SAMPLERATE | 0x5F8 | Controls normal or continuous sample rate |
| RESULT.PTR | 0x62C | Data pointer |
| RESULT.MAXCNT | 0x630 | Maximum number of 16-bit samples to be written to output RAM buffer |
| RESULT.AMOUNT | 0x634 | Number of 16-bit samples written to output RAM buffer since the previous START task |
## 6.23.7.1 TASKS\_START
Address offset: 0x000
Starts the SAADC and prepares the result buffer in RAM
## 6.23.7.2 TASKS\_SAMPLE
Address offset: 0x004
Takes one SAADC sample
## 6.23.7.3 TASKS\_STOP
Address offset: 0x008
Stops the SAADC and terminates all on-going conversions
## 6.23.7.4 TASKS\_CALIBRATEOFFSET
Address offset: 0x00C
Starts offset auto-calibration
## 6.23.7.5 EVENTS\_STARTED
Address offset: 0x100
The SAADC has started
## 6.23.7.6 EVENTS\_END
Address offset: 0x104
The SAADC has filled up the result buffer
## 6.23.7.7 EVENTS\_DONE
Address offset: 0x108
A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
## 6.23.7.8 EVENTS\_RESULTDONE
Address offset: 0x10C
Result ready for transfer to RAM
## 6.23.7.9 EVENTS\_CALIBRATEDONE
Address offset: 0x110
Calibration is complete
## 6.23.7.10 EVENTS\_STOPPED
Address offset: 0x114
The SAADC has stopped
## 6.23.7.11 EVENTS\_CH[0]
Peripheral events.
## 6.23.7.11.1 EVENTS\_CH[0].LIMITH
Address offset: 0x118
Last result is equal or above CH[0].LIMIT.HIGH
## 6.23.7.11.2 EVENTS\_CH[0].LIMITL
Address offset: 0x11C
Last result is equal or below CH[0].LIMIT.LOW
## 6.23.7.12 EVENTS\_CH[1]
Peripheral events.
## 6.23.7.12.1 EVENTS\_CH[1].LIMITH
Address offset: 0x120
Last result is equal or above CH[1].LIMIT.HIGH
## 6.23.7.12.2 EVENTS\_CH[1].LIMITL
Address offset: 0x124
Last result is equal or below CH[1].LIMIT.LOW
## 6.23.7.13 EVENTS\_CH[2]
Peripheral events.
## 6.23.7.13.1 EVENTS\_CH[2].LIMITH
Address offset: 0x128
Last result is equal or above CH[2].LIMIT.HIGH
## 6.23.7.13.2 EVENTS\_CH[2].LIMITL
Address offset: 0x12C
Last result is equal or below CH[2].LIMIT.LOW
## 6.23.7.14 EVENTS\_CH[3]
Peripheral events.
## 6.23.7.14.1 EVENTS\_CH[3].LIMITH
Address offset: 0x130
Last result is equal or above CH[3].LIMIT.HIGH
## 6.23.7.14.2 EVENTS\_CH[3].LIMITL
Address offset: 0x134
Last result is equal or below CH[3].LIMIT.LOW
## 6.23.7.15 EVENTS\_CH[4]
Peripheral events.
## 6.23.7.15.1 EVENTS\_CH[4].LIMITH
Address offset: 0x138
Last result is equal or above CH[4].LIMIT.HIGH
## 6.23.7.15.2 EVENTS\_CH[4].LIMITL
Address offset: 0x13C
Last result is equal or below CH[4].LIMIT.LOW
## 6.23.7.16 EVENTS\_CH[5]
Peripheral events.
## 6.23.7.16.1 EVENTS\_CH[5].LIMITH
Address offset: 0x140
Last result is equal or above CH[5].LIMIT.HIGH
## 6.23.7.16.2 EVENTS\_CH[5].LIMITL
Address offset: 0x144
Last result is equal or below CH[5].LIMIT.LOW
## 6.23.7.17 EVENTS\_CH[6]
Peripheral events.
## 6.23.7.17.1 EVENTS\_CH[6].LIMITH
Address offset: 0x148
Last result is equal or above CH[6].LIMIT.HIGH
## 6.23.7.17.2 EVENTS\_CH[6].LIMITL
Address offset: 0x14C
Last result is equal or below CH[6].LIMIT.LOW
## 6.23.7.18 EVENTS\_CH[7]
Peripheral events.
## 6.23.7.18.1 EVENTS\_CH[7].LIMITH
Address offset: 0x150
Last result is equal or above CH[7].LIMIT.HIGH
## 6.23.7.18.2 EVENTS\_CH[7].LIMITL
Address offset: 0x154
Last result is equal or below CH[7].LIMIT.LOW
## 6.23.7.19 INTEN
Address offset: 0x300
Enable or disable interrupt
| Bit number | | | 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID V U T S R Q P O N M L K J I H G F E D C B A | ID V U T S R Q P O N M L K J I H G F E D C B A | ID V U T S R Q P O N M L K J I H G F E D C B A | ID V U T S R Q P O N M L K J I H G F E D C B A | ID V U T S R Q P O N M L K J I H G F E D C B A | ID V U T S R Q P O N M L K J I H G F E D C B A | ID V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value ID | Value | Description | Description | Description |
| | | Enabled | 1 | Enable | Enable | Enable |
| C | RW DONE | | | Enable or disable interrupt for event DONE Disable | Enable or disable interrupt for event DONE Disable | Enable or disable interrupt for event DONE Disable |
| | | Disabled Enabled | 0 1 | Enable | Enable | Enable |
| D RW | RESULTDONE | Disabled | 0 | Enable or disable interrupt for event RESULTDONE Disable Enable | Enable or disable interrupt for event RESULTDONE Disable Enable | Enable or disable interrupt for event RESULTDONE Disable Enable |
| E RW | RW CALIBRATEDONE STOPPED | Disabled Enabled Disabled Enabled | 0 1 0 | Enable or disable interrupt for event CALIBRATEDONE Disable Enable Enable or disable interrupt for event STOPPED Disable | Enable or disable interrupt for event CALIBRATEDONE Disable Enable Enable or disable interrupt for event STOPPED Disable | Enable or disable interrupt for event CALIBRATEDONE Disable Enable Enable or disable interrupt for event STOPPED Disable |
| F G | RW CH0LIMITH RW CH0LIMITL | Disabled Enabled Disabled Enabled | 1 0 1 | Enable or disable interrupt for event CH0LIMITL Disable Enable Enable or disable interrupt for event CH1LIMITH Disable Enable Enable or disable interrupt for event CH1LIMITL Disable Enable Enable or disable interrupt for event CH2LIMITH | Enable or disable interrupt for event CH0LIMITL Disable Enable Enable or disable interrupt for event CH1LIMITH Disable Enable Enable or disable interrupt for event CH1LIMITL Disable Enable Enable or disable interrupt for event CH2LIMITH | Enable or disable interrupt for event CH0LIMITL Disable Enable Enable or disable interrupt for event CH1LIMITH Disable Enable Enable or disable interrupt for event CH1LIMITL Disable Enable Enable or disable interrupt for event CH2LIMITH |
| H RW | CH1LIMITH | Disabled Enabled | 0 1 | | | |
| I | CH1LIMITL | Disabled | 0 1 | | | |
| J RW | CH2LIMITH | Enabled | 0 1 | Disable | Disable | Disable |
| RW | | Disabled | 0 1 | Enable Enable or disable interrupt for event CH2LIMITL | Enable Enable or disable interrupt for event CH2LIMITL | Enable Enable or disable interrupt for event CH2LIMITL |
| K | | Enabled | | Disable Enable | Disable Enable | Disable Enable |
| L RW | CH2LIMITL | | 0 | | | |
| | | Disabled Enabled | 1 | Enable or disable interrupt for event CH3LIMITH | Enable or disable interrupt for event CH3LIMITH | Enable or disable interrupt for event CH3LIMITH |
| M RW | CH3LIMITH | Disabled Enabled | 0 1 | Disable Enable Enable or disable interrupt for event CH3LIMITL Disable | Disable Enable Enable or disable interrupt for event CH3LIMITL Disable | Disable Enable Enable or disable interrupt for event CH3LIMITL Disable |
| N | RW | Disabled | 0 1 | Enable | Enable | Enable |
| | CH3LIMITL | Enabled | | Enable or disable interrupt for event CH4LIMITH Disable | Enable or disable interrupt for event CH4LIMITH Disable | Enable or disable interrupt for event CH4LIMITH Disable |
| O RW | RW CH4LIMITH CH4LIMITL | Disabled Enabled Disabled | 0 1 0 0 1 | Enable Enable or disable interrupt for event CH5LIMITH Disable | Enable Enable or disable interrupt for event CH5LIMITH Disable | Enable Enable or disable interrupt for event CH5LIMITH Disable |
| P | CH5LIMITH | Enabled Disabled Enabled | 1 | Enable or disable interrupt for event CH4LIMITL Disable | Enable or disable interrupt for event CH4LIMITL Disable | Enable or disable interrupt for event CH4LIMITL Disable |
| Q | RW<br>CH5LIMITL | Disabled | | Enable<br>Enable or disable interrupt for event | Enable<br>Enable or disable interrupt for event | Enable<br>Enable or disable interrupt for event |
| | | | 0 | Disable<br>CH5LIMITL | Disable<br>CH5LIMITL | Disable<br>CH5LIMITL |
| R | | Enabled | | | | |
| | | | 1 | Enable<br>CH6LIMITH<br>event<br>for | Enable<br>CH6LIMITH<br>event<br>for | Enable<br>CH6LIMITH<br>event<br>for |
| | RW | | | interrupt | interrupt | interrupt |
| S | CH6LIMITH<br>RW | | | disable<br>Enable or | disable<br>Enable or | disable<br>Enable or |
| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | Reset 0x00000000 | Reset 0x00000000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W | Field Value ID | Value | Description |
| | Disabled | 0 | Disable |
| | Enabled | 1 | Enable |
| T RW | CH6LIMITL | | Enable or disable interrupt for event CH6LIMITL |
| | Disabled | 0 | Disable |
| | Enabled | 1 | Enable |
| U RW | CH7LIMITH | | Enable or disable interrupt for event CH7LIMITH |
| | Disabled | 0 | Disable |
| | Enabled | 1 | Enable |
| V RW | CH7LIMITL | | Enable or disable interrupt for event CH7LIMITL |
| | Disabled | 0 | Disable |
| | Enabled | 1 | Enable |
## 6.23.7.20 INTENSET
Address offset: 0x304
Enable interrupt
| Bit number | | | | 31 30 29 | 17 16 15 14 13 | 6 5 4 | 2 1 | 0 | 3 |
| ------------------ | ----- | --------------- | ---------- | ------------ | --------------------- | --------- | ------- | ----- | ----- |
| ID | | | | | R Q P O N | G F E D | C B A | | |
| Reset 0x00000000 | | | | 0 0 | 0 0 0 0 0 | 0 0 0 | 0 | | 0 |
| ID | R/W | Field | Value ID | Value | | | | | |
| A | RW | STARTED | Set<br>Enabled | 1<br>1 | interrupt for event | | | | |
| B | RW | END | Set<br>Enabled | 1 0<br>1 | interrupt for event | | | | |
| C | RW<br>RW | DONE<br>RESULTDONE | Enabled | 1 | event | | | | |
| D | | | Enabled | 0 1 | interrupt for | | | | |
| E | RW | CALIBRATEDONE | Disabled | 0 | interrupt | | | | |
| F | RW | STOPPED | Set<br>Disabled<br>Enabled | 1<br>0<br>1 | interrupt for | | | | |
| G | RW | CH0LIMITH | | 1 | for event | | 0 0 | | |
| Bit number | | | 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| -------------- | ------------------------------ | ------------------------------ | ------------------------------ | ------------------------------ |
| ID | 0x00000000 | | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A |
| ID | R/W Field | Value ID | Value | Description |
| H | RW CH0LIMITL | Set | | Write '1' to enable interrupt for event CH0LIMITL Enable |
| I K | RW RW CH1LIMITL | Disabled Enabled Set Disabled | 1 0 0 1 1 0 1 1 0 1 | Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITH Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH1LIMITL Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH2LIMITH Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH4LIMITH |
| L O | CH1LIMITH | Enabled | 1 | Write '1' to enable interrupt for event CH2LIMITL Enable Read: Disabled Read: Enabled |
| | CH4LIMITH | Set Disabled Enabled | 1 1 0 1 | Enable Read: Disabled Read: Enabled |
| J M N | RW CH2LIMITH RW CH2LIMITL RW CH3LIMITH | Enabled Set Disabled Enabled Set Disabled Set Disabled Enabled Set Disabled | 1 0 1 1 0 1 | Write '1' to enable interrupt for event CH3LIMITH Enable Read: Disabled Read: Enabled Write '1' to enable interrupt for event CH3LIMITL Write '1' to enable interrupt for event CH4LIMITL Enable Read: Disabled Read: Enabled |
| Q | CH4LIMITL | Disabled Enabled Set | 1 0 1 | Write '1' to enable interrupt for event |
| | CH5LIMITH | | 1<br>0 1 | Enable<br>Read: Disabled |
| P | RW CH3LIMITL RW | Enabled Set Disabled Enabled<br>Set | 1 0 1 | Read: Enabled<br>Write '1' to enable interrupt for event |
| | RW<br>RW | Disabled<br>Enabled | 0 1<br>1 | Enable Read: Disabled Read: Enabled<br>Write '1' to enable interrupt for event<br>CH5LIMITH<br>CH5LIMITL<br>Enable |
| R | CH5LIMITL | Set Disabled<br>Enabled | 1 | |
| | CH6LIMITH | Set Disabled | | Read: Disabled |
| S | RW<br>RW | Enabled | 0 | CH6LIMITH |
| | CH6LIMITL | Set | 1 | Read: Enabled Write '1' to enable interrupt for event |
| T | RW | | 1 | CH6LIMITL<br>Enable |
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ---------- | ------------------------------ |
| ID | | V U T S R Q P O N M L K J I H G F E D C B A |
| Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| ID R/W Field | Disabled | 0 Read: Disabled |
| ID R/W Field | Enabled | 1 Read: Enabled |
| U RW CH7LIMITH | | Write '1' to enable interrupt for event CH7LIMITH |
| U RW CH7LIMITH | Set | 1 Enable |
| U RW CH7LIMITH | Disabled | 0 Read: Disabled |
| U RW CH7LIMITH | Enabled | 1 Read: Enabled |
| V RW CH7LIMITL | | Write '1' to enable interrupt for event CH7LIMITL |
| V RW CH7LIMITL | Set | 1 Enable |
| V RW CH7LIMITL | Disabled | 0 Read: Disabled |
| V RW CH7LIMITL | Enabled | 1 Read: Enabled |
## 6.23.7.21 INTENCLR
Address offset: 0x308
Disable interrupt
| | | | Bit number 31 | 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 | 5 4 | 3 | 2 1 | | 0 | 6 |
| ------------------ | ------------------ | ----------- | ----------------- | ------------------------------ | ------- | ------- | ------- | ---- | ----- | --------------- |
| ID | ID | | | | F E | D C B | A | | | G |
| Reset 0x00000000 | Reset 0x00000000 | | 0 | 0 0 | 0 0 | 0 0 0 | | 0 | | |
| ID | R/W | Field | Value ID | Value | | | | | | |
| A | RW | Disabled<br>Enabled | Clear 1<br>0 | 1 | | | | | | |
| B | RW END | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | | | | | |
| C | RW DONE | Clear<br>Enabled | 1<br>Disabled 0 | 1 | | | | | | |
| D | RW RESULTDONE | Clear<br>Disabled<br>Enabled | 1<br>0<br>1 | | | | | | | |
| E | RW CALIBRATEDONE | Clear<br>Disabled | 1<br>0 | | | | | | | CALIBRATEDONE |
| F | RW STOPPED | Enabled<br>Clear<br>Disabled<br>Enabled | 1<br>1<br>0 | 1 | | | | | | |
| G | RW | CH0LIMITH<br>Clear<br>Disabled | 1<br>0 | | | | | | | |
| H | RW | CH0LIMITL | | | | | | | | |
| Bit number | | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 |
| -------------- | -------------- | ---------- | ------------------------------ | ------------------------------ | ------------------------------ |
| ID | | | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A | V U T S R Q P O N M L K J I H G F E D C B A |
| | | | 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Reset 0x00000000 |
| ID | Field | Value ID | Value | Description | R/W |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| I | CH1LIMITH | | | Write '1' to disable interrupt for event CH1LIMITH | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| J | CH1LIMITL | | | Write '1' to disable interrupt for event CH1LIMITL | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| K | CH2LIMITH | | | Write '1' to disable interrupt for event CH2LIMITH | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| L | CH2LIMITL | | | Write '1' to disable interrupt for event CH2LIMITL | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | RW CH3LIMITH | Enabled | 1 | Read: Enabled Write '1' to disable interrupt for event CH3LIMITH | M |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| RW | CH3LIMITL | | | Write '1' to disable interrupt for event CH3LIMITL | N |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| O | CH4LIMITH | | | Write '1' to disable interrupt for event CH4LIMITH | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| | CH4LIMITL | | | Write '1' to disable interrupt for event CH4LIMITL | P RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| Q | CH5LIMITH | | | Write '1' to disable interrupt for event CH5LIMITH | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| R | CH5LIMITL | | | Write '1' to disable interrupt for event CH5LIMITL | RW |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | | Enabled | 1 | Read: Enabled | |
| S RW | CH6LIMITH | | | Write '1' to disable interrupt for event CH6LIMITH | |
| | | Clear | 1 | Disable | |
| | | Disabled | 0 | Read: Disabled | |
| | CH6LIMITL | Enabled | 1 | Read: Enabled | |
| | | Clear | 1 | Disable<br>Write '1' to disable interrupt for event CH6LIMITL | RW<br>T |
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | ---------- | ------------------------------ |
| ID | | V U T S R Q P O N M L K J I H G F E D C B |
| Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| | Enabled | 1 Read: Enabled |
| U RW CH7LIMITH | | Write '1' to disable interrupt for event CH7LIMITH |
| | Clear | 1 Disable |
| | Disabled | 0 Read: Disabled |
| | Enabled | 1 Read: Enabled |
| V RW CH7LIMITL | | Write '1' to disable interrupt for event CH7LIMITL |
| | Clear | 1 Disable |
| | Disabled | 0 Read: Disabled |
| | Enabled | 1 Read: Enabled |
## 6.23.7.22 STATUS
## Address offset: 0x400
## Status
## 6.23.7.23 ENABLE
Address offset: 0x500
Enable or disable SAADC
## 6.23.7.24 CH[0].PSELP
Address offset: 0x510
Input positive pin selection for CH[0]
## 6.23.7.25 CH[0].PSELN
Address offset: 0x514
Input negative pin selection for CH[0]
## 6.23.7.26 CH[0].CONFIG
Address offset: 0x518
Input configuration for CH[0]
| Bit | | number 31 30 29 28 27 26 25 24 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 | | | | | 3 | 2 1 | 0 |
| ------------------ | ------------------ | ------------------------------ | ------------------------------ | ------- | -------------------- | ------------------ | ----------- | ----- | ------- | ----- |
| ID | | | | | G F | E | B | B | | |
| Reset 0x00020000 | Reset 0x00020000 | | 0 | 0 0 | 0 0 0 0 0 | 0 0 0 | 0 | 0 | 0 0 | 0 |
| ID | R/W Field | Value ID | | Value | Description | | | | | |
| B RW | RESN | Bypass<br>Pulldown<br>Pullup<br>VDD1_2 | 0<br>1<br>2<br>3 | | Negative channel<br>Bypass resistor<br>Pull-down to<br>Pull-up to VDD<br>Set input at | resistor control | | | | |
| C RW | GAIN | Gain1_6<br>Gain1_5<br>Gain1_4<br>Gain1_3<br>Gain1<br>Gain2 | 0<br>1<br>2<br>3<br>5<br>6 | | Gain control<br>1/6<br>1/5<br>1/4<br>1/3<br>1<br>2 | | | | | |
| D- RW | REFSEL | Internal<br>VDD1_4 | 0<br>1 | | Reference control<br>Internal reference<br>VDD/4 as reference | V) | | | | |
| E RW | TACQ | 3us<br>5us 10us<br>15us<br>20us<br>40us | 0<br>1 2<br>3<br>4<br>5 | | Acquisition<br>3 μs<br>5 μs 10 μs<br>15 μs<br>20 μs 40 μs | time the SAADC | the input | | | |
## 6.23.7.27 CH[0].LIMIT
Address offset: 0x51C
High/low limits for event monitoring of a channel
| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A |
| Reset 0x7FFF8000 | Reset 0x7FFF8000 | Reset 0x7FFF8000 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value | Value Description |
| A | RW | LOW | [-32768 to +32767] Low level limit |
| B | RW | HIGH | [-32768 to +32767] High level limit |
## 6.23.7.28 CH[1].PSELP
Address offset: 0x520
Input positive pin selection for CH[1]
## 6.23.7.29 CH[1].PSELN
Address offset: 0x524
Input negative pin selection for CH[1]
| Bit number | | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
| ------------------ | -------------- | ------------------------------ |
| ID | | A A A A |
| Reset 0x00000000 | | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID R/W Field | Value ID | Value Description |
| A RW PSELN | | Analog negative input, enables differential channel |
| | NC | 0 Not connected |
| | AnalogInput0 | 1 AIN0 |
| | AnalogInput1 | 2 AIN1 |
| | AnalogInput2 | 3 AIN2 |
| | AnalogInput3 | 4 AIN3 |
| | AnalogInput4 | 5 AIN4 |
| | AnalogInput5 | 6 AIN5 |
| | AnalogInput6 | 7 AIN6 |
| | AnalogInput7 | 8 AIN7 |
| | VDD | 9 VDD |
| | VDDHDIV5 | 0x0D VDDH/5 |
## 6.23.7.30 CH[1].CONFIG
Address offset: 0x528
Input configuration for CH[1]
| Bit | | number 31 30 29 28 27 26 25 24 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 | | | | | 3 | 2 1 | 0 |
| ------------------ | ------------------ | ------------------------------ | ------------------------------ | ------- | -------------------- | ------------------ | ----------- | ----- | ------- | ----- |
| ID | | | | | G F | E | B | B | | |
| Reset 0x00020000 | Reset 0x00020000 | | 0 | 0 0 | 0 0 0 0 0 | 0 0 0 | 0 | 0 | 0 0 | 0 |
| ID | R/W Field | Value ID | | Value | Description | | | | | |
| B RW | RESN | Bypass<br>Pulldown<br>Pullup<br>VDD1_2 | 0<br>1<br>2<br>3 | | Negative channel<br>Bypass resistor<br>Pull-down to<br>Pull-up to VDD<br>Set input at | resistor control | | | | |
| C RW | GAIN | Gain1_6<br>Gain1_5<br>Gain1_4<br>Gain1_3<br>Gain1<br>Gain2 | 0<br>1<br>2<br>3<br>5<br>6 | | Gain control<br>1/6<br>1/5<br>1/4<br>1/3<br>1<br>2 | | | | | |
| D- RW | REFSEL | Internal<br>VDD1_4 | 0<br>1 | | Reference control<br>Internal reference<br>VDD/4 as reference | V) | | | | |
| E RW | TACQ | 3us<br>5us 10us<br>15us<br>20us<br>40us | 0<br>1 2<br>3<br>4<br>5 | | Acquisition<br>3 μs<br>5 μs 10 μs<br>15 μs<br>20 μs 40 μs | time the SAADC | the input | | | |
## 6.23.7.31 CH[1].LIMIT
Address offset: 0x52C
High/low limits for event monitoring of a channel
| Bit number | Bit number | Bit number | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| ------------------ | ------------------ | ------------------ | ------------------------------ |
| ID | ID | ID | B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A |
| Reset 0x7FFF8000 | Reset 0x7FFF8000 | Reset 0x7FFF8000 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| ID | R/W Field | Value | Value Description |
| A | RW | LOW | [-32768 to +32767] Low level limit |
| B | RW | HIGH | [-32768 to +32767] High level limit |
## 6.23.7.32 CH[2].PSELP
Address offset: 0x530
Input positive pin selection for CH[2]
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| nRF52840 | Nordic Semiconductor | — |
| nRF52840-CKAA-F-R7 | Nordic Semiconductor ASA | 94-UFBGA, WLCSP |
| nRF52840-CKAA-R7 | Nordic Semiconductor ASA | 94-UFBGA, WLCSP |
| NRF52840-QFAA-F-R7 | Nordic Semiconductor ASA | 48-VFQFN Exposed Pad |
| NRF52840-QIAA-R7 | Nordic Semiconductor | 73-VFQFN Dual Rows, Exposed Pad |
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