NRF52832-QFAA

Part: nRF52832 (Manufacturer not specified)

Type: Bluetooth Low Energy SoC

Key Specs:

• 2.4 GHz Transceiver Sensitivity: -96 dBm in Bluetooth low energy mode
• 2.4 GHz Transceiver TX Power: -20 to +4 dBm
• CPU: ARM Cortex-M4 32-bit processor with FPU, 64 MHz
• Flash Memory: Up to 512 kB
• RAM: Up to 64 kB
• Supply Voltage Range: 1.7 V–3.6 V
• OFF Mode Current: 0.3 μA at 3 V (no RAM retention)
• ADC: 12-bit, 200 ksps

Features:

• 2.4 GHz transceiver with 2 Mbps Bluetooth low energy mode
• ARM Cortex-M4 32-bit processor with FPU and trace capabilities
• Flexible power management with automatic LDO and DC/DC regulator system
• Nordic SoftDevice ready and concurrent multi-protocol support
• Type 2 near field communication (NFC-A) tag with wakeup-on-field
• 8 configurable channels 12-bit, 200 ksps ADC with programmable gain
• 32 general purpose I/O pins
• Multiple serial interfaces (SPI, I2C, I2S, UART) with EasyDMA
• AES HW encryption with EasyDMA
• Autonomous peripheral operation without CPU intervention using PPI and EasyDMA
• On-chip balun for single-ended RF

Applications:

• Internet of Things (IoT)
• Home automation
• Sensor networks
• Building automation
• Health/fitness sensor and monitor devices
• Key fobs and wrist watches
• Remote controls
• Gaming controllers
• Beacons
• Computer peripherals (Mouse, Keyboard, Multi-touch trackpad)

Package:

• QFN48 package: 6 × 6 mm
• WLCSP package: 3.0 × 3.2 mm

{
  "manufacturer": null,
  "

The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition. OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0.

Important: The OVRFLW event is disabled by default.

Here we cover the pin assignments for each variant of the chip.

4.1 QFN48 pin assignments

Figure 2: QFN48 pin assignments, top view

Table 3: QFN48 pin assignments

Pin	Name	Type	Description
Left Side of chip
1	DEC1	Power	0.9 V regulator digital supply decoupling
2	P0.00	Digital I/O	General purpose I/O
	XL1	Analog input	Connection for 32.768 kHz crystal (LFXO)
3	P0.01	Digital I/O	General purpose I/O
	XL2	Analog input	Connection for 32.768 kHz crystal (LFXO)
4	P0.02	Digital I/O	General purpose I/O
	AIN0	Analog input	SAADC/COMP/LPCOMP input
5	P0.03	Digital I/O	General purpose I/O
	AIN1	Analog input	SAADC/COMP/LPCOMP input
6	P0.04	Digital I/O	General purpose I/O
	AIN2	Analog input	SAADC/COMP/LPCOMP input
7	P0.05	Digital I/O	General purpose I/O
	AIN3	Analog input	SAADC/COMP/LPCOMP input
8	P0.06	Digital I/O	General purpose I/O
9	P0.07	Digital I/O	General purpose I/O

Pin	Name	Type	Description
10	P0.08	Digital I/O	General purpose I/O
11	NFC1	NFC input	NFC antenna connection
	P0.09	Digital I/O	General purpose I/O1
12	NFC2	NFC input	NFC antenna connection
	P0.10	Digital I/O	General purpose I/O1
Bottom side of chip
13	VDD	Power	Power supply
14	P0.11	Digital I/O	General purpose I/O
15	P0.12	Digital I/O	General purpose I/O
16	P0.13	Digital I/O	General purpose I/O
17	P0.14	Digital I/O	General purpose I/O
	TRACEDATA[3]		Trace port output
18	P0.15	Digital I/O	General purpose I/O
	TRACEDATA[2]		Trace port output
19	P0.16	Digital I/O	General purpose I/O
	TRACEDATA[1]		Trace port output
20	P0.17	Digital I/O	General purpose I/O
21	P0.18	Digital I/O	General purpose I/O
	TRACEDATA[0] / SWO		Single wire output Trace port output
22	P0.19	Digital I/O	General purpose I/O
23	P0.20	Digital I/O	General purpose I/O
	TRACECLK		Trace port clock output
24	P0.21	Digital I/O	General purpose I/O
	nRESET		Configurable as pin reset
Right Side of chip
25	SWDCLK	Digital input	Serial wire debug clock input for debug and programming
26	SWDIO	Digital I/O	Serial wire debug I/O for debug and programming
27	P0.22	Digital I/O	General purpose I/O2
28	P0.23	Digital I/O	General purpose I/O2
29	P0.24	Digital I/O	General purpose I/O2
30	ANT	RF	Single-ended radio antenna connection
31	VSS	Power	Ground (Radio supply)
32	DEC2	Power	1.3 V regulator supply decoupling (Radio supply)
33	DEC3	Power	Power supply decoupling
34	XC1	Analog input	Connection for 32 MHz crystal
35	XC2	Analog input	Connection for 32 MHz crystal
36	VDD	Power	Power supply
Top side of chip
37	P0.25	Digital I/O	General purpose I/O2
38	P0.26	Digital I/O	General purpose I/O2
39	P0.27	Digital I/O	General purpose I/O2
40	P0.28	Digital I/O	General purpose I/O2
	AIN4	Analog input	SAADC/COMP/LPCOMP input
41	P0.29	Digital I/O	General purpose I/O2
	AIN5	Analog input	SAADC/COMP/LPCOMP input
42	P0.30	Digital I/O	General purpose I/O2
	AIN6	Analog input	SAADC/COMP/LPCOMP input
43	P0.31	Digital I/O	General purpose I/O pin2
	AIN7	Analog input	SAADC/COMP/LPCOMP input

Pin	Name	Type	Description
44	NC		No connect Leave unconnected
45	VSS	Power	Ground
46	DEC4	Power	1.3 V regulator supply decoupling Input from DC/DC regulator Output from 1.3 V LDO
47	DCC	Power	DC/DC regulator output
48	VDD	Power	Power supply
Bottom of chip
Die pad	VSS	Power	Ground pad Exposed die pad must be connected to ground (VSS) for proper device operation.

4.2 WLCSP ball assignments

Figure 3: WLCSP ball assignments, top view

Table 4: WLCSP ball assignments

Ball	Name	Type	Description
A1	XC2	Analog input	Connection for 32 MHz crystal
A2	DEC2	Power	1.3 V regulator supply decoupling (Radio supply)
A3	P0.28	Digital I/O	General purpose I/O¹
	AIN4	Analog input	SAADC/COMP/LPCOMP input
A4	P0.29	Digital I/O	General purpose I/O¹
	AIN5	Analog input	SAADC/COMP/LPCOMP input
A5	P0.30	Digital I/O	General purpose I/O¹
	AIN6	Analog input	SAADC/COMP/LPCOMP input
A6	DEC4	Power	1.3 V regulator supply decoupling Input from DC/DC converter. Output from 1.3 V LDO
A7	VDD	Power	Power supply
B2	XC1	Analog input	Connection for 32 MHz crystal
B3	P0.25	Digital I/O	General purpose I/O¹

1 See GPIO located near the radio on page 17 for more information.

2 See NFC antenna pins on page 17 for more information.

Ball	Name		Description
B4	P0.27	Digital I/O	General purpose I/O3
B5	P0.31	Digital I/O	General purpose I/O3
	AIN7	Analog input	SAADC/COMP/LPCOMP input
B6	DCC	Power	DC/DC converter output
B7	DEC1	Power	0.9 V regulator digital supply decoupling
C2	DEC3	Power	Power supply decoupling
C3	NC	N/A	Not connected
C4	VSS	Power	Ground
C5	VSS	Power	Ground
C6	P0.02	Digital I/O	General purpose I/O
	AIN0	Analog input	SAADC/COMP/LPCOMP input
C7	P0.01	Digital I/O	General purpose I/O
D1	XL2 ANT	Analog input RF	Connection for 32.768 kHz crystal (LFXO) Single-ended radio antenna connection
D2	VSS_PA	Power	Ground (Radio supply)
D3	P0.26	Digital I/O	General purpose I/O 3
D6	P0.03	Digital I/O	General purpose I/O
	AIN1	Analog input	SAADC/COMP/LPCOMP input
D7	P0.00	Digital I/O	General purpose I/O
	XL1	Analog input	Connection for 32.768 kHz crystal (LFXO)
E1	P0.24	Digital I/O	General purpose I/O3
E2	P0.23	Digital I/O	General purpose I/O3
E3	VSS	Power	Ground
E6	P0.04	Digital I/O	General purpose I/O
	AIN2	Analog input	SAADC/COMP/LPCOMP input
E7	P0.05	Digital I/O	General purpose I/O
	AIN3	Analog input	SAADC/COMP/LPCOMP input
F1	SWDCLK	Digital input	Serial wire debug clock input for debug and programming
F2	P0.22	Digital I/O	General purpose I/O3
F3	P0.19	Digital I/O	General purpose I/O
F4	P0.11	Digital I/O	General purpose I/O
F5	VSS	Power	Ground
F6	P0.07	Digital I/O	General purpose I/O
F7	P0.06	Digital I/O	General purpose I/O
G1	SWDIO	Digital I/O	Serial wire debug I/O for debug and programming
G2	P0.20	Digital I/O	General purpose I/O
	TRACECLK		Trace port clock output
G3	P0.17	Digital I/O	General purpose I/O
G4	P0.13	Digital I/O	General purpose I/O
G5	NFC2	NFC input	NFC antenna connection
	P0.10	Digital I/O	General purpose I/O4
G6	NFC1	NFC input	NFC antenna connection General purpose I/O4
G7	P0.09 P0.08	Digital I/O Digital I/O	General purpose I/O
H1	P0.21	Digital I/O	General purpose I/O
	nRESET		Configurable as pin reset
H2	P0.18	Digital I/O	General purpose I/O
	TRACEDATA[0]		Trace port output
H3	P0.16	Digital I/O	General purpose I/O
	TRACEDATA[1]		Trace port output
H4	P0.15	Digital I/O	General purpose I/O

Ball	Name	Type	Description
A1	XC2	Analog input	Connection for 32 MHz crystal
A2	DEC2	Power	1.3 V regulator supply decoupling (Radio supply)
A3	P0.28	Digital I/O	General purpose I/O¹
A4	AIN4	Analog input	SAADC/COMP/LPCOMP input
	P0.29	Digital I/O	SAADC/COMP/LPCOMP input
A5	AIN5	Analog input	SAADC/COMP/LPCOMP input
	P0.30	Digital

4.3 GPIO usage restrictions

4.3.1 GPIO located near the radio

Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large sink/source current close to the Radio power supply and antenna pins.

Table 5: GPIO recommended usage for QFN48 package on page 17 and Table 6: GPIO recommended usage for WLCSP package on page 17 identify some GPIO that have recommended usage guidelines to maximize radio performance in an application.

Table 5: GPIO recommended usage for QFN48 package

Pin	GPIO	Recommended usage
27	P0.22	Low drive, low frequency I/O only.
28	P0.23
29	P0.24
37	P0.25
38	P0.26
39	P0.27
40	P0.28
41	P0.29
42	P0.30
43	P0.31

Table 6: GPIO recommended usage for WLCSP package

Pin	GPIO	Recommended usage
F2	P0.22	Low drive, low frequency I/O only.
E2	P0.23
E1	P0.24
B3	P0.25
D3	P0.26
B4	P0.27
A3	P0.28
A4	P0.29
A5	P0.30
B5	P0.31

4.3.2 NFC antenna pins

Two physical pins can be configured either as NFC antenna pins (factory default), or as GPIOs, as shown below.

Table 7: GPIO pins used by NFC

NFC pad name	GPIO
NFC1	P0.09
NFC2	P0.10

When configured as NFC antenna pins, the GPIOs on those pins will automatically be set to DISABLE state and a protection circuit will be enabled preventing the chip from being damaged in the presence of a strong NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2 V.

³ See GPIO located near the radio on page 17 for more information.

⁴ See NFC antenna pins on page 17 for more information.

For information on how to configure these pins as normal GPIOs, see NFCT — Near field communication tag on page 416 and UICR — User information configuration registers on page 54. Note that the device will not be protected against strong NFC field damage if the pins are configured as GPIO and an NFC antenna is connected to the device. The pins will always be configured as NFC pins during power-on reset until the configuration is set according to the UICR register.

These two pins will have some limitations when configured as GPIO. The pin capacitance will be higher on these pins, and there is some current leakage between the two pins if they are driven to different logical values. To avoid leakage between the pins when configured as GPIO, these GPIOs should always be at the same logical value whenever entering one of the device power saving modes. See Electrical specification.

Symbol	Description	Min.	Typ.	Max.	Units
fSPIM	Bit rates for SPIM25			26 8	Mbps
ISPIM,2Mbps	Run current for SPIM, 2 Mbps		50		μA
ISPIM,8Mbps	Run current for SPIM, 8 Mbps		50		μA
ISPIM,IDLE	Idle current for SPIM (STARTed, no CSN activity)		1		μA
tSPIM,START	Time from START task to transmission started				μs

Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device.

Table 8: Absolute maximum ratings

	Min.	Max.	Unit
Supply voltages
VDD	-0.3	+3.9	V
VSS		0	V
I/O pin voltage
VI/O, VDD ≤3.6 V	-0.3	VDD + 0.3 V	V
VI/O, VDD >3.6 V	-0.3	3.9 V	V
NFC antenna pin current
INFC1/2		80	mA
Radio
RF input level		10	dBm
Environmental QFN48, 6×6 mm package
Storage temperature	-40	+125	°C
MSL (moisture sensitivity level)		2
ESD HBM (human body model)		4	kV
ESD CDM (charged device model)		1000	V
Environmental WLCSP, 3.0×3.2 mm package
Storage temperature	-40	+125	°C
MSL		1
ESD HBM		2	kV
ESD CDM		500	V
Flash memory
Endurance	10 000		Write/erase cycles
Retention	10 years at 40°C

The operating conditions are the physical parameters that the chip can operate within.

Table 9: Recommended operating conditions

Symbol	Parameter	Notes	Min.	Nom.	Max.	Units
VDD	Supply voltage, independent of DCDC enable		1.7	3.0	3.6	V
tR_VDD	Supply rise time (0 V to 1.7 V)				60	ms
TA	Operating temperature		-40	25	85	°C

Important: The on-chip power-on reset circuitry may not function properly for rise times longer than the specified maximum.

6.1 WLCSP light sensitivity

All WLCSP package variants are sensitive to visible and close-range infrared light. This means that a final product design must shield the chip properly, either by final product encapsulation or by shielding/coating of the WLCSP device.