Skip to main content

MM32F0140

Microcontroller

The MM32F0140 is a microcontroller from MindMotion. View the full MM32F0140 datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

MindMotion

Category

Microcontroller

Overview

Part: MM32F0140 — MindMotion

Type: 32-bit Microcontroller

Description: 32-bit Arm Cortex-M0 microcontroller operating at up to 48 MHz, with up to 64 Kbytes Flash memory and 8 Kbytes SRAM.

Operating Conditions:

  • Supply voltage: 2.0–5.5 V
  • Operating temperature: -40 to +105 °C
  • CPU frequency: Up to 48 MHz

Absolute Maximum Ratings:

  • Max supply voltage: 6.0 V
  • Max continuous current: 120 mA
  • Max junction/storage temperature: 150 °C

Key Specs:

  • VDD operating voltage: 2.0 V to 5.5 V
  • CPU frequency: Up to 48 MHz
  • Flash memory: Up to 64 Kbytes
  • SRAM: Up to 8 Kbytes
  • Run mode current: 10.5 mA (Typ, VDD=3.3V, fCPU=48MHz, all peripherals off)
  • Stop mode current: 1.5 μA (Typ, VDD=3.3V, TA=25°C)
  • ADC resolution: 12-bit
  • ADC conversion rate: 1.5 MSPS

Features:

  • Arm® Cortex®-M0 core
  • Up to 48 MHz operating frequency
  • Up to 64 Kbytes Flash memory, 8 Kbytes SRAM
  • Clock management (HSI, LSI, HSE, PLL)
  • POR/PDR, PVD reset and power management
  • Low-power modes (Sleep, Stop, Standby)
  • DMA controller
  • Timers (Advanced, General-purpose, Basic), Watchdogs, RTC
  • GPIO with external interrupt capability
  • Communication interfaces: UART, I2C, SPI, I2S, FlexCAN
  • 12-bit ADC, Comparators, CRC calculation unit
  • Serial Wire Debug (SWD)

Package:

  • LQFP48
  • LQFP32
  • QFN32 5x5 mm2
  • QFN32 4x4 mm2
  • TSSOP20

Features

  • Core and system

  • -32-bit Arm ® Cortex ® ­M0.

  • -Frequency up to 72MHz.

  • Memory

  • -Up to 64KB embedded Flash storage.

  • -Up to 8KB SRAM.

  • -Embedded Bootloader to support In-System-Programming (ISP).

  • Clock, reset and power management

  • -Power supply ranges from 2.0 to 5.5V.

  • -Power-on and Power-down reset (POR/PDR), Programmable voltage detector (PVD).

  • -4 to 24MHz high speed crystal oscillator.

  • -8MHz factory-trimmed high speed RC oscillator.

  • -Integrated PLL to generate up to 72MHz system clock and support multiple prescaler rate to provide clock sources to bus matrix and peripherals.

  • -40KHz low speed oscillator.

  • Low power

  • -Multiple low power modes including Sleep mode, Stop mode, Deep Stop mode and Standby mode.

  • One DMA controller with 5 channels to support peripherals including timers, ADC, UART, I2C, SPI, and FlexCAN.

  • Total 9 timers:

  • -One 16-bit 4-channel advanced timer (TIM1), each channel providing two PWM output including one complementary output, supports hardware dead-time insertion and emergency break when fault detected.

  • -One 16-bit general purpose timer (TIM3) and one 32-bit general purpose timer (TIM2), with up to four input capture or output compare channels and can be used for infrared decode.

  • -Three 16-bit basic timers (TIM14 / TIM16 / TIM17), with one input capture or output compare channel and one complementary output, support hardware deadtime insertion, emergency break when fault detected, and integrated modulator circuit for infrared control.

  • -Two watchdog timers, including one independent watchdog (IWDG) and one window watchdog (WWDG).

  • -One 24-bit Systick timer.

  • Up to 40 fast I/O ports:

  • -All I/O ports can be mapped to 16 external interrupts.

  • -All I/O ports can accept input or generate output signal voltage level is not higher than VDD.

  • Up to 7 communication interfaces:

  • -Three UART.

  • -One I2C.

  • -Two SPI (support I2S mode).

  • -One FlexCAN module supports CAN 2.0B interface.

  • One 12-bit Analog-to-Digital converter (ADC), support 1μs conversion duration, with up to 14 external inputs and 2 internal inputs

  • -Conversion range: 0 to VDDA.

  • -Configurable sampling cycles and resolution.

  • -On-chip temperature sensor.

  • -On-chip voltage sensor.

  • One high speed analog comparator

  • 32-bit hardware divider

  • Embedded CRC engine

  • 96bit unique chip ID (UID)

  • Debug mode

  • -Serial Wire Debug (SWD).

  • Available in LQFP48, LQFP32, QFN32 and TSSOP20 packages

Pin Configuration

Table 4-1 Pin assignment table

LQFP48LQFP32QFN32 5x5 mm2QFN32 4x4 mm2TSSOP20NameType (1)I/O level (2)Main functionMultiplex functionAdditional function
1­­­­NC­­­­­
2­­­­PC13I/OTCPC13TIM2_CH1­
3­­­­PC14I/OTCPC14TIM2_CH2­
4­­­­PC15I/OTCPC15TIM2_CH3­
52222PD0 OSC_INI/OTCPD0UART3_TX I2C_SDA­
63333PD1 OSC_OUTI/OTCPD1UART3_RX I2C_SCL­
74444NRST1I/O­NRST1­­
8­­­­VSSS­VSS­­
95515VDDAS­VDDA­­
106656PA0 WKUPI/OTCPA0UART2_CTS TIM2_CH1/TIM2_ETR SPI2_NSS/I2S2_WS TIM2_CH3 COMP1_OUTADC1_VIN[0]
117767PA1I/OTCPA1UART2_RTS TIM2_CH2ADC1_VIN[1] COMP_INP[0]
128878PA2I/OTCPA2UART2_TX TIM2_CH3 SPI2_NSS/I2S2_WSADC1_VIN[2] COMP_INP[1]
139989PA3I/OTCPA3UART2_RX TIM2_CH4ADC1_VIN[3] COMP_INP[2]
141010910PA4I/OTCPA4SPI1_NSS/I2S1_WS TIM1_BKIN TIM14_CH1 I2C_SDAADC1_VIN[4] COMP_INP[3]
1511111011PA5I/OTCPA5SPI1_SCK/I2S1_CK TIM2_CH1/TIM2_ETR TIM1_ETR I2C_SCLADC1_VIN[5] COMP_INM[0]
1612121112PA6I/OTCPA6TIM1_CH3N SPI1_MISO/I2S1_MCK TIM3_CH1 TIM1_BKIN UART2_RX TIM1_ETR TIM16_CH1 TIM1_CH3ADC1_VIN[6] COMP_INM[1]
1713131213PA7I/OTCPA7COMP1_OUT SPI1_MOSI/I2S1_SD TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 TIM1_CH2N TIM1_CH3NADC1_VIN[7] COMP_INM[2]
18141413­PB0I/OTCPB0TIM3_CH3 TIM1_CH2N TIM1_CH1N TIM1_CH3ADC1_VIN[8]
1915151414PB1I/OTCPB1TIM14_CH1 TIM3_CH4 TIM1_CH3N TIM1_CH4 TIM1_CH2N MCO TIM1_CH2 TIM1_CH1NADC1_VIN[9]
20­1615­PB2I/OTCPB2­­
LQFP48LQFP32QFN32 5x5 mm2QFN32 4x4 mm2TSSOP20NameType (1)I/O level (2)Main functionMultiplex functionAdditional function
21­­­­PB10I/OTCPB10I2C_SCL TIM2_CH3 UART3_TX SPI2_SCK/I2S2_CK­
22­­­­PB11I/OTCPB11I2C_SDA TIM2_CH4 UART3_RX­
2316­­15VSSS­VSS­­
241717­16VDDS­VDD­­
25­­­­PB12I/OTCPB12SPI2_NSS/I2S2_WS SPI2_SCK/I2S2_CK TIM1_BKIN SPI2_MOSI/I2S2_SD SPI2_MISO/I2S2_MCK­
26­­16­PB13I/OTCPB13SPI2_SCK/I2S2_CK SPI2_MISO/I2S2_MCK TIM1_CH1N SPI2_NSS/I2S2_WS SPI2_MOSI/I2S2_SD I2C_SCL TIM1_CH3N TIM2_CH1 UART3_CTS­
27­­17­PB14I/OTCPB14SPI2_MISO/I2S2_MCK SPI2_MOSI/I2S2_SD TIM1_CH2N SPI2_SCK/I2S2_CK SPI2_NSS/I2S2_WS I2C_SDA TIM1_CH3 TIM1_CH1­
28­­­­PB15I/OTCPB15UART3_RTS SPI2_MOSI/I2S2_SD SPI2_NSS/I2S2_WS TIM1_CH3N SPI2_MISO/I2S2_MCK SPI2_SCK/I2S2_CK TIM1_CH2N TIM1_CH2­
29181818­PA8I/OTCPA8MCO TIM1_CH1 TIM1_CH2 TIM1_CH3­
3019191917PA9I/OTCPA9UART1_TX TIM1_CH2 UART1_RX I2C_SCL MCO TIM1_CH1N TIM1_CH4 CAN_RX­
3120202018PA10I/OTCPA10TIM17_BKIN UART1_RX TIM1_CH3 UART1_TX I2C_SDA TIM1_CH1 SPI2_SCK/I2S2_CK­
32212121­PA11I/OTCPA11UART3_TX UART1_CTS TIM1_CH4 CAN_RX SPI2_MOSI/I2S2_SD I2C_SCL COMP1_OUT­
LQFP48LQFP32QFN32 5x5 mm2QFN32 4x4 mm2TSSOP20NameType (1)I/O level (2)Main functionMultiplex functionAdditional function
332222 22­PA12I/OTCPA12UART1_RTS TIM1_ETR CAN_TX I2C_SDA TIM1_CH2UART3_RX SPI2_MISO/I2S2_MCK­
3423232319PA13I/OTCPA13SWDIO UART1_TX SPI2_MISO/I2S2_MCK MCO TIM1_CH2 TIM1_BKIN­
35­­­­PD2I/OTCPD2­­
36­­­­PD3I/OTCPD3­­
3724242420PA14I/OTCPA14SWDCLK UART2_TX UART1_RX SPI1_NSS/I2S1_WS­
38252525­PA15I/OTCPA15SPI1_NSS/I2S1_WS UART2_RX TIM2_CH1/TIM2_ETR­
39262626­PB3I/OTCPB3SPI1_SCK/I2S1_CK TIM2_CH2 UART1_TX TIM2_CH3 TIM1_CH1 TIM2_CH1ADC1_VIN[10]
40272727­PB4I/OTCPB4SPI1_MISO/I2S1_MCK TIM3_CH1 UART1_RX TIM17_BKIN TIM1_CH2ADC1_VIN[11]
41282828­PB5I/OTCPB5SPI1_MOSI/I2S1_SD TIM3_CH2 TIM16_BKIN MCO TIM1_CH3 TIM2_CH3­
42292929­PB6I/OTCPB6UART1_TX I2C_SCL TIM16_CH1N TIM2_CH1­
43303030­PB7I/OTCPB7UART1_RX I2C_SDA TIM17_CH1N UART2_TXADC1_VIN[12]
443131­1PD5 BOOT0I/OTCPD5­­
45­3231­PB8I/OTCPB8I2C_SCL TIM16_CH1 CAN_RX UART2_RX­
46­­­­PB9I/OTCPB9I2C_SDA TIM17_CH1 CAN_TX TIM1_CH4 SPI2_NSS/I2S2_WS­
­­­32­PD6I/OTCPD6SPI1_MISO/I2S1_MCK TIM3_CH1 TIM1_BKIN UART2_RX TIM1_ETR TIM16_CH1 TIM1_CH3ADC1_VIN[13] COMP_INM[3]
4732­­­VSSS­VSS­­
LQFP48LQFP32QFN32 5x5 mm2QFN32 4x4 mm2TSSOP20NameType (1)I/O level (2)Main functionMultiplex functionAdditional function
48111­VDDS­VDD­­
  1. I = input, O = output, S = power pins, HiZ = high resistance state.
  2. TC: standard IO. Input signal level should not exceed VDD.

Electrical Characteristics

The definitions and values of the input and output AC characteristics are given in the following figure and table, respectively.

Unless otherwise stated, the parameters listed in the following table are provided under the ambient temperature and supply voltage in accordance with the condition Table 5-3.

Table 5-23 I/O AC characteristics (1)(2)(3)

MODE[1:0]SymbolParameterConditionsMinimumTypicalMaximumUnit
11t f(IO)outOutput fall timeC L = 50pF VDD=3.3V3.344.49.27ns
11t r(IO)outOutput rise timeC L = 50pF VDD=3.3V3.344.49.27ns
10t f(IO)outOutput fall timeC L = 50pF VDD=3.3V5.9110.917ns
10t r(IO)outOutput rise timeC L = 50pF VDD=3.3V5.9110.617ns
01t f(IO)outOutput fall timeC L = 50pF VDD=3.3V6.0610.917.4ns
MODE[1:0]SymbolParameterConditionsMinimumTypicalMaximumUnit
t r(IO)outOutput rise time6.0610.817.4ns
  1. The speed of the I/O port can be configured through MODEx[1:0]. Refer to the description of the GPIO port configuration register in this chip user manual.
  2. The maximum frequency is defined in Figure 5-8.
  3. Guaranteed by design, not tested in production.

Figure 5-8 I/O AC characteristics

Absolute Maximum Ratings

Stresses above the absolute maximum ratings given in "Absolute Group Maximum Ratings" list (Table 5-1, Table 5-2 and Table 5-3) may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 5-1 Voltage characteristics

SymbolDescriptionMinimumMaximumUnit
V DDx ­V SSxExternal main supply voltage (including V DDA and V SSA ) (1)­0.35.8V
V IN (2)Input voltage on other pinsV SS ­0.3V DD +0.3V
  1. All power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply system within the permitted range.
  2. The maximum value of VIN must be respected. Refer to the table below for the maximum allowed injected current values.
  3. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to an external power supply in the permitted range.
  4. This current consumption must be correctly distributed to all I/O and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP package.
  5. The reverse injection current can interfere with the analog performance of the device.
  6. When VIN > VDDA, a positive injected current is generated; when VIN < VSS, a reverse injected current is generated. Do not exceed IINJ(PIN).
  7. When there is simultaneous injection current for multiple inputs, the maximum value of ΣIINJ(PIN) is equal to the sum of the absolute values of the forward injection current and the reverse injection current (instantaneous value) .

Table 5-2 Current characteristics

SymbolDescriptionMaximumUnit
I VDD/VDDA (1)Total current through V DD /V DDA power pins (supply current) (1)+120mA
I VSS/VSSA (1)Total current through V SS /V SSA ground pins (outflow current) (1)­120mA
I IOOutput sink current on any I/O and control pins+25mA
I IOOutput current on any I/O and control pins­25mA
I INJ(PIN) (2)(3)NRST pin injection current±5mA
I INJ(PIN) (2)(3)HSE OSC_IN pin injection current±5mA
∑I INJ(PIN) (5)Other pins injection current (4)±25mA

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
MM32F0140C7PMindMotion
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.

Get structured datasheet data via API

Get started free