MC74HC00A
The MC74HC00A is an electronic component from onsemi. View the full MC74HC00A datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
onsemi
Overview
Part: MC74HC00A — onsemi Type: Quad 2-Input NAND Gate Description: High-performance silicon-gate CMOS quad 2-input NAND gate with 2 to 6 V operating voltage range and 10 LSTTL loads output drive capability.
Operating Conditions:
- Supply voltage: 2.0–6.0 V
- Operating temperature: -55 to +125 °C
- Input/Output voltage: 0 to V CC V
Absolute Maximum Ratings:
- Max supply voltage: +6.5 V
- Max continuous current: ±50 mA (DC Supply Current, V CC and GND Pins)
- Max junction/storage temperature: +150 °C
Key Specs:
- Minimum High-Level Input Voltage (V IH ): 1.50 V (V CC = 2.0 V, -55 to 25 °C)
- Maximum Low-Level Input Voltage (V IL ): 0.50 V (V CC = 2.0 V, -55 to 25 °C)
- Minimum High-Level Output Voltage (V OH ): 1.9 V (V CC = 2.0 V, -55 to 25 °C)
- Maximum Low-Level Output Voltage (V OL ): 0.1 V (V CC = 2.0 V, -55 to 25 °C)
- Maximum Input Leakage Current (I in ): ±0.1 μA (V CC = 6.0 V, -55 to 25 °C)
- Maximum Quiescent Supply Current (I CC ): 1.0 μA (V CC = 6.0 V, -55 to 25 °C)
- Maximum Propagation Delay (t PLH, t PHL ): 15 ns (V CC = 4.5 V, -55 to 25 °C)
- Maximum Input Capacitance (C in ): 10 pF
Features:
- Outputs Directly Interface to CMOS, NMOS and TTL
- Output Drive Capability: 10 LSTTL Loads
- High Noise Immunity Characteristic of CMOS Devices
- Low Input Current: 1 μA
- In Compliance With the JEDEC Standard No. 7 A Requirements
- -Q Suffix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable
- Chip Complexity: 32 FETs or 8 Equivalent Gates
- Pb-Free, Halogen Free and RoHS Compliant
Applications:
Package:
- SOIC-14
- TSSOP-14
Features
- Outputs Directly Interface to CMOS, NMOS and TTL
- Output Drive Capability: 10 LSTTL Loads
- Operating Voltage Range: 2 to 6 V
- High Noise Immunity Characteristic of CMOS Devices
- Low Input Current: 1 m A
- In Compliance With the JEDEC Standard No. 7 A Requirements
- -Q Suffix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC -Q100 Qualified and PPAP Capable
- Chip Complexity: 32 FETs or 8 Equivalent Gates
- These Devices are Pb -Free, Halogen Free and are RoHS Compliant
Figure 1. Logic Diagram
Figure 1. Logic Diagram
Electrical Characteristics
| V CC | Guaranteed Limit | Guaranteed Limit | Guaranteed Limit | |||
|---|---|---|---|---|---|---|
| Symbol | Parameter | Condition | V | - 55 to 25 ° C | ≤ 85 ° C | ≤ 125 ° C |
| V IH | Minimum High - Level Input Volt- age | V out = 0.1V or V CC - 0.1V \ | I out \ | ≤ 20 m A | 2.0 3.0 4.5 6.0 | 1.50 2.10 3.15 4.20 |
| V IL | Maximum Low - Level Input Volt- age | V out = 0.1V or V CC - 0.1V \ | I out \ | ≤ 20 m A | 2.0 3.0 4.5 6.0 | 0.50 0.90 1.35 1.80 |
| V OH | Minimum High - Level Output Voltage | V in = V IH or V IL \ | I out \ | ≤ 20 m A | 2.0 4.5 6.0 | 1.9 4.4 5.9 |
| V OH | V in =V IH or V IL \ | I out \ | ≤ \ | I out \ | ≤ \ | |
| V OL | Maximum Low - Level Output Voltage | V in = V IH or V IL \ | I out \ | ≤ 20 m A | 2.0 4.5 6.0 | 0.1 0.1 0.1 |
| V OL | V in = V IH or V IL \ | I out \ | ≤ \ | I out \ | ≤ \ | |
| I in | Maximum Input Leakage Current | V in = V CC or GND | 6.0 | ± 0.1 | ± 1.0 | ± 1.0 |
| I CC | Maximum Quiescent Supply Current (per Package) | V in = V CC or GND I out = 0 m A | 6.0 | 1.0 | 10 | 40 |
Absolute Maximum Ratings
| Symbol | Parameter | Parameter | Value | Unit |
|---|---|---|---|---|
| V CC | DC Supply Voltage | DC Supply Voltage | - 0.5 to +6.5 | V |
| V I | DC Input Voltage | DC Input Voltage | - 0.5 to V CC + 0.5 | V |
| V O | DC Output Voltage | DC Output Voltage | - 0.5 to V CC + 0.5 | V |
| I IN | DC Input Current, per Pin | DC Input Current, per Pin | ± 20 | mA |
| I OUT | DC Output Current, Per Pin | DC Output Current, Per Pin | ± 25 | mA |
| I CC | DC Supply Current, V CC and GND Pins | DC Supply Current, V CC and GND Pins | ± 50 | mA |
| I IK | Input Clamp Current (V IN < 0 or V IN > V CC ) | Input Clamp Current (V IN < 0 or V IN > V CC ) | ± 20 | mA |
| I OK | Output Clamp Current (V OUT < 0 or V OUT > V CC ) | Output Clamp Current (V OUT < 0 or V OUT > V CC ) | ± 20 | mA |
| T STG | Storage Temperature Range | Storage Temperature Range | - 65 to +150 | ° C |
| T L | Lead Temperature, 1 mmfrom Case for 10 secs | Lead Temperature, 1 mmfrom Case for 10 secs | 260 | ° C |
| T J | Junction Temperature Under Bias | Junction Temperature Under Bias | +150 | ° C |
| q JA | Thermal Resistance (Note 1) | SOIC - 14 QFN14 TSSOP - 14 | 116 130 150 | ° C/W |
| P D | Power Dissipation in Still Air at 25 ° C | SOIC - 14 QFN14 TSSOP - 20 | 1077 962 833 | mW |
| MSL | Moisture Sensitivity | Moisture Sensitivity | Level 1 | - |
| F R | Flammability Rating | Oxygen Index: 28 to 34 | UL 94 V - 0 @0.125 in | - |
| V ESD | ESD Withstand Voltage (Note 2) | Human Body Model Charged Device Model | > 2000 > 1000 | V |
Recommended Operating Conditions
| Symbol | Parameter | Min | Max | Unit |
|---|---|---|---|---|
| V CC | DC Supply Voltage (Referenced to GND) | 2.0 | 6.0 | V |
| V IN , V OUT | DC Input, Output Voltage (Referenced to GND) (Note 3) | 0 | V CC | V |
| T A | Operating Free - Air Temperature | - 55 | +125 | ° C |
| t r , t f | Input Rise or Fall Rate | - 0 0 0 | 1000 500 400 | ns |
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.
- Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| HGC0402R5105K500NTEJ | — | — |
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