HGC0402R5105K500NTEJ

Part: SPC584Bx Type: 32-bit Power Architecture Microcontroller

Key Specs:

• CPU: e200z420, 32-bit Power Architecture
• Core Frequency: 120 MHz
• On-chip Flash Memory: 2112 KB (2048 KB code + 64 KB data)
• HSM Dedicated Flash Memory: 176 KB (1

• AEC-Q100 qualified
• High performance e200z420
  • 32-bit Power Architecture technology CPU
  • Core frequency as high as 120 MHz
  • Variable Length Encoding (VLE)
• 2112 KB (2048 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
• 176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
• 128 KB on-chip general-purpose SRAM (in addition to 64 KB core local data RAM
• Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
• Multi-channel direct memory access controller (eDMA) with 64 channels
• 1 interrupt controller (INTC)
• Comprehensive new generation ASIL-B safety concept
  • ASIL-B of ISO 26262
  • FCCU for collection and reaction to failure notifications
• Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
• Cyclic redundancy check (CRC) unit
• Enhanced low power support
  • Ultra low power STANDBY
  • Smart Wake-up Unit
  • Fast wake-up and execute from RAM
• Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution
• Body cross triggering unit (BCTU)
  • Triggers ADC conversions from any eMIOS channel
  • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
• Enhanced analog-to-digital converter system with:
  • 2 independent fast 12-bit SAR analog converters
  • 1 supervisor 12-bit SAR analog converter
  • 1 10-bit SAR analog converter with STDBY mode support
• Communication interfaces
  • 1 Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
  • 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support
  • 14 LINFlexD modules
  • 7 Deserial Serial Peripheral Interface (DSPI) modules
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
• Nexus Development Interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard

This is information on a product in full production.

• Boot Assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART

• Junction temperature range -40 °C to 150 °C

• eTQFP64

• eTQFP100

• eTQFP144

• eTQFP176

Table 1. Device summary

Features

• AEC-Q100 qualified
• High performance e200z420
  • 32-bit Power Architecture technology CPU
  • Core frequency as high as 120 MHz
  • Variable Length Encoding (VLE)
• 2112 KB (2048 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
• 176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
• 128 KB on-chip general-purpose SRAM (in addition to 64 KB core local data RAM
• Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
• Multi-channel direct memory access controller (eDMA) with 64 channels
• 1 interrupt controller (INTC)
• Comprehensive new generation ASIL-B safety concept
  • ASIL-B of ISO 26262
  • FCCU for collection and reaction to failure notifications
• Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
• Cyclic redundancy check (CRC) unit
• Enhanced low power support
  • Ultra low power STANDBY
  • Smart Wake-up Unit
  • Fast wake-up and execute from RAM
• Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution
• Body cross triggering unit (BCTU)
  • Triggers ADC conversions from any eMIOS channel
  • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
• Enhanced analog-to-digital converter system with:
  • 2 independent fast 12-bit SAR analog converters
  • 1 supervisor 12-bit SAR analog converter
  • 1 10-bit SAR analog converter with STDBY mode support
• Communication interfaces
  • 1 Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
  • 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support
  • 14 LINFlexD modules
  • 7 Deserial Serial Peripheral Interface (DSPI) modules
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
• Nexus Development Interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard

This is information on a product in full production.

• Boot Assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART

• Junction temperature range -40 °C to 150 °C

• eTQFP64

• eTQFP100

• eTQFP144

• eTQFP176

Table 1. Device summary

4.1 Introduction

The present document contains the target Electrical Specification for the 40 nm family 32-bit MCU SPC584Bx products.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" (Controller Characteristics) is included in the "Symbol" column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" (System Requirement) is included in the "Symbol" column.

The electrical parameters shown in this document are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate.

Classification tag	Tag description
P	Those parameters are guaranteed during production testing on each individual device.
C	Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.
T	Those parameters are achieved by design validation on a small sample size from typical devices.
D	Those parameters are derived mainly from simulations.

Classification tag	Tag description

4.2 Absolute maximum ratings

Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device.

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
VDD_LV	SR	D	Core voltage operating life range(1)	—	–0.3	—	1.4
VDD_HV_IO_MAIN VDD_HV_IO_ETH VDD_HV_OSC VDD_HV_FLA	SR	D	I/O supply voltage(2)	—	–0.3	—	6.0
VSS_HV_ADV	SR	D	ADC ground<br

Table 4. Absolute maximum ratings
-----------------------------------

Symbol			Parameter		Value
		C		Conditions	Min
TSTG	SR	T	Maximum non operating Storage temperature range	—	–55
TPAS	SR	C	Maximum nonoperating temperature during passive lifetime	—	–55
TSTORAGE	SR	—	Maximum storage time, assembled part programmed in ECU	No supply; storage temperature in range –40 °C to 60 °C	—
TSDR	SR	T	Maximum solder temperature Pb free packaged(8)	—	—
MSL	SR	T	Moisture sensitivity level(9)	—	—
TXRAY dose	SR	T	Maximum cumulated XRAY dose	Typical range for X-rays source during inspection:80 ÷ 130 KV; 20 ÷ 50 A	—

		Table 4. Absolute maximum ratings

2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions.

• 1. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations.
• 1. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
• 1. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time.
• 1. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications.
• 1. 175 °C are allowed for limited time. Mission profile with passive lifetime temperature >150 °C have to be evaluated by ST to confirm that are granted by product qualification.
• 1. Solder profile per IPC/JEDEC J-STD-020D.

1. Moisture sensitivity per JDEC test method A112.

4.3 Operating conditions

Table 5 describes the operating conditions for the device, and for which all the specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.

Symbol	C	P	Parameter	Conditions	Min	Typ	Max	Unit
FSYS	SR	P	Operating system clock frequency(2)	—	—	—	120	MHz
TA_125 Grade(3)	SR	D	Operating Ambient temperature	—	–40	—	125	°C
TJ_125 Grade(3)	SR	P	Junction temperature under bias	TA<br

			Table 5. Operating conditions
--	--	--	-------------------------------

						Unit
Symbol		C	Parameter	Conditions	Min	Typ
VSS_HV_ADR_S VSS_HV_ADV	SR	D	VSS_HV_ADR_S differential voltage	—	–25	—
VRAMP_HV	SR	D	Slew rate on HV power supply	—	—	—
VIN	SR	P	I/O input voltage range	—	0	—
IINJ1	SR	T	Injection current (per pin) without performance degradation(7) (8) (9)	Digital pins and analog pins	–3.0	—
IINJ2	SR	D	Dynamic Injection current (per pin) with performance degradation(9) (10)	Digital pins and analog pins	–10	—

Table 5. Operating conditions (continued)

1. The ranges in this table are design targets and actual data may vary in the given range.

2. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.

• 3. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to Section 5.5: Package thermal characteristics.
• 1. Core voltage as measured on device pin to guarantee published silicon performance.
• 1. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that HVD134_C monitor reset is disabled.
• 1. 1.260 V 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to 1.236 V at the given temperature profile.
• 1. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements.
• 1. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
• 9. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications.
• 1. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).

4.3.1 Power domains and power up/down sequencing

The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting 'ok'. This limitation is valid during power-up and power-down phases, as well as during normal device operation.

		Supply2
		VDD_LV
Supply1	VDD_HV_IO_ETH	ok
	VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC	ok
	VDD_HV_ADV	ok
	VDD_HV_ADR	ok

Table 6. Device supply relation during power-up/power-down sequence

During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document.

4.4 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device:

• All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

• Device failure is defined as: "If after exposure to ESD pulses, the device does not meet the device specification requirements, which include the complete DC parametric and functional testing at room temperature and hot temperature, maximum DC parametric variation within 10 % of maximum specification".

• Parameter

• ESD for Human Body Model (HBM)(1)

• ESD for field induced Charged Device Model (CDM)(2)

1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.

2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.

4.5 Electromagnetic compatibility characteristics

EMC measurements at IC-level IEC standards are available from STMicroelectronics on request.

4.6 Temperature profile

The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL 1,000 h and HTDR 1,000 hrs, TJ = 150 °C.

4.7 Device consumption

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
				Value$^{(1)}$
				Min	Typ	Max	Unit
IDD_LKG$^{(2),(3)}$	CC	Leakage current on the V$_{DD_LV}$ supply	T$_{J}$ = 40 °C	—	—	7	mA
			T$_{J}$ = 25 °C	—	1.5	5	mA
			T$_{J}$ = 55 °C	—	—	10	mA

Table 8. Device consumption

| Symbol | C | Parameter | Conditions | Value(1) | Unit | |---|---|---|---|:---:|:---:|:---:|---| | | | | | Min | Typ | Max | | | IDD_LKG$^{(2),(3)}$ | CC | C | Leakage current on the V${DD_LV}$ supply | T${J}$ = 40 °C | — | — | 7 | mA | | | | D | | T${J}$ = 25 °C | — | 1.5 | 5 | mA | | | | D | | T${J}$ = 55 °C | — | — | 10 | mA | | | |

		Table 8. Device consumption (continued)
--	--	-----------------------------------------

1. The ranges in this table are design targets and actual data may vary in the given range.

• 1. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic IDD_LV and IDD_HV parameters.
• 3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production are verifying that the total consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used.
• 4. Use case: 1 x e200Z4 @120 MHz, HSM @60 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, all SARADC in continuous conversion, DMA continuously triggered by ADC conversion, 2 DSPI / 8 CAN / 2 LINFlex transmitting, RTC and STM running, 1 x EMIOS running (4 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are available separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature.
• 5. Gateway use case: One core running at 120 MHz, HSM 40 MHz, DMA, PLL, FLASH read only 25%, 8xCAN, 1xSARADC.
• 6. BCM use case: One Core running at 80 MHz, HSM 40 MHz, DMA, PLL, FLASH read only 25%, 1xCAN, 3xSARADC.
• 1. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code Book crypto algorithm on 1 block of 16 byte of shared RAM.
• 1. Flash in Low Power. Sysclk at 120 MHz, HSM 60 MHz, PLL0_PHI at 400 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off. FlexCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON (configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.
• 1. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode.
• 10. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.

• 1. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature.
• 1. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature.

4.8 I/O pad specification

The following table describes the different pad type configurations.

Pad type	Description
Weak configuration	Provides a good compromise between transition time and low electromagnetic emission.
Medium configuration	Provides transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission.
Strong configuration	Provides fast transition speed; used for fast interface.
Very strong configuration	Provides maximum speed and controlled symmetric behavior for rise and fall transition. Used for fast interface including Ethernet interface requiring fine control of rising/falling edge jitter.
Differential configuration	A few pads provide differential capability providing very fast interface together with good EMC performances.
Input only pads	These low input leakage pads are associated with the ADC channels.
Standby pads	These pads (LP pads) are active during STANDBY. They are configured in CMOS level logic and this configuration cannot be changed. Moreover, when the device enters the STANDBY mode, the pad-keeper feature is activated for LP pads. It means that: – if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor is automatically enabled – if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor is automatically enabled. For the pad-keeper high/low thresholds, consider(VDD_HV_IO_MAIN / 2) +/-20 %.

				Table 9. I/O pad specification descriptions
--	--	--	--	---------------------------------------------

Note: Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin. PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for each IO segment.

Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be configured as CMOS also in running mode in order to prevent device wrong behavior in STANDBY.

4.8.1 I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in Figure 3.

		Figure 3. I/O input electrical characteristics

• TTL
• Vihttl
• Vilttl
• Vhysttl
• CMOS
• Vihcmos
• Vilcmos
• Vhyscmos
• COMMON
• ILKG
• ILKG
• ILKG

Symbol			Parameter Conditions
		C
CP1	CC	D	Pad capacitance
Vdrift	CC	D	Input Vil/Vih temperature drift
WFI	SR	C	Wakeup input filtered pulse(1)
WNFI	SR	C	Wakeup input not filtered pulse(1)

Table 10. I/O input electrical characteristics (continued)

1. In the range from WFI (max) to WNFI (min), pulses can be filtered or not filtered, according to operating temperature and voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature.

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
IWPU	CC	T	Weak pull-up current absolute value	VIN = 1.1 V(1)	—	—	130
	CC	P		VIN = 0.69 * VDD_HV_IO(2)	15	—	—
RWPU	CC	D	Weak Pull-up resistance	VDD_HV_IO = 5.0 V ± 10%	33	—	93
RW

Table 11. I/O pull-up/pull-down electrical characteristics

1. Maximum current when forcing a change in the pin level opposite to the pull configuration.

2. Minimum current when keeping the same pin level state than the pull configuration.

Note: When the device enters into standby mode, the LP pads have the input buffer switched-on. As a consequence, if the pad input voltage VIN is VSS<VIN<VDD_HV, an additional consumption can be measured in the VDD_HV domain. The highest consumption can be seen around mid-range (VIN ~=VDD_HV/2), 2-3 mA depending on process, voltage and temperature.

This situation may occur if the PAD is used as a ADC input channel, and VSS<VIN<VDD_HV. The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid the extra consumption. Refer to the device pinout IO definition excel file to identify the lowpower pads which also have an ADC function.

4.8.2 I/O output DC characteristics

Figure 4 provides description of output DC electrical characteristics.

Figure 4. I/O output DC electrical characteristics definition

The following tables provide DC characteristics for bidirectional pads:

• Table 12 provides output driver characteristics for I/O pads when in WEAK/SLOW configuration.
• Table 13 provides output driver characteristics for I/O pads when in MEDIUM configuration.
• Table 14 provides output driver characteristics for I/O pads when in STRONG/FAST configuration.
• Table 15 provides output driver characteristics for I/O pads when in VERY STRONG/VERY FAST configuration.

Note: 10 %/90 % is the default condition for any parameter if not explicitly mentioned differently.

Symbol	C		Parameter	Conditions	Min	Typ	Max	Unit
Vol_W	CC	D	Output low voltage for Weak type PADs	Iol = 0.5 mA VDD = 5.0 V ± 10 % VDD = 3.3 V ± 10 %	—	—	0.1*VDD	V
Voh_W	CC	D	Output high voltage for Weak type PADs	Ioh = 0.5 mA VDD

| Table 12. WEAK/SLOW I/O output characteristics | |---|---|---|---|---|---|---|---| | Symbol | C | Parameter | Conditions | Min | Typ | Max | Unit | | V_{ol_W} | CC | D | Output low voltage for Weak type PADs | I_ol = 0.5 mA
V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | — | — | 0.1*V_DD | V | | V_{oh_W} | CC | D | Output high voltage for Weak type PADs | I_oh = 0.5 mA
V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | 0.9*V_DD | — | — | V | | R_W | CC | P | Output impedance for Weak type PADs | V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | 380
250 | — | 1040
700 | Ω | | F_{max_W} | CC | T | Maximum output frequency for Weak type PADs | CL = 25 pF
V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | — | — | 2 | MHz | | | | | CL = 50 pF
V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | — | — | 1 | MHz | | t_{TR_W} | CC | T | Transition time output pin weak configuration, 10%-90% | CL = 25 pF
V_DD = 5.0 V + 10 %
V_DD = 3.3 V + 10 % | 25 | — | 120 | ns | | | | | CL = 50 pF
V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | 50 | — | 240 | ns | | t_{SKEW_W} | CC | T | Difference between rise and fall time, 90%-10% | — | — | 25 | % | | I_{DCMAX_W} | CC | D | Maximum DC current | V_DD = 5.0 V ± 10 %
V_DD = 3.3 V ± 10 % | — | — | 0.5 | mA |

Table 13. MEDIUM I/O output characteristics

Symbol		C	Parameter	Conditions	Value
					Min
Vol_M	CC	D	Output low voltage for Medium type PADs	Iol = 2.0 mA VDD =5.0 V ± 10 % VDD =3.3 V ± 10 %	—
Voh_M	CC	D	Output high voltage for Medium type PADs	Ioh=2.0 mA VDD = 5.0 V ± 10 % VDD = 3.3 V ± 10 %	0.9*VDD

Symbol		C	Parameter	Conditions	Value
					Min
			Output impedance for Medium type PADs	VDD = 5.0 V ± 10 %	90
R_M	CC	P		VDD = 3.3 V ± 10 %	60
Fmax_M	CC		Maximum output frequency for Medium type PADs	CL = 25 pF VDD = 5.0 V ± 10 % VDD = 3.3 V ± 10 %	—
		T		CL = 50 pF VDD = 5.0 V ± 10 % VDD = 3.3 V ± 10 %	—
tTR_M	CC
tSKEW_M	CC	T	Difference between rise and fall time, 90%-10%	—	—
IDCMAX_M	CC	D	Maximum DC current	VDD = 5.0 V ± 10 % VDD = 3.3 V ± 10 %	—
Table 13. MEDIUM I/O output characteristics (continued)
---------------------------------------------------------	--
---------------------------------------------------------	--

Table 14. STRONG/FAST I/O output characteristics

Symbol		C		Parameter	Conditions	Value			Unit
					Min	Typ	Max
Vol_S		CC	D	Output low voltage for Strong type PADs	Iol = 8.0 mA VDD = 5.0 V ± 10 %	—	—	0.1*VDD	V
					Iol = 5.5 mA VDD = 3.3 V ± 10 %	—	—	0.15*VDD	V
Voh_S		CC	D	Output high voltage for Strong type PADs	Ioh = 8.0 mA VDD = 5.0 V ± 10 %	0.9*VDD	—	—	V
					Ioh = 5.5 mA VDD = 3.3 V ± 10 %	0.85*VDD	—	—	V
R_S		CC	P	Output impedance for Strong type PADs	VDD = 5.0 V ± 10 %	20	—	65
					VDD = 3.3 V ± 10 %	28	—	90	Ω

Symbol		C	Parameter	Conditions	Value
					Min
Fmax_S	CC		Maximum output frequency for Strong type PADs	CL = 25 pF VDD=5.0 V ± 10 %	—
		T		CL = 50 pF VDD=5.0 V ± 10 %	—
				CL = 25 pF VDD = 3.3 V ± 10 %	—
				CL = 50 pF VDD = 3.3 V ± 10 %	—
tTR_S	CC	T	Transition time output pin STRONG configuration, 10%-90%	CL = 25 pF VDD = 5.0 V ± 10 %	3
				CL = 50 pF VDD = 5.0 V ± 10 %	5
				CL = 25 pF VDD = 3.3 V ± 10 %	1.5
				CL = 50 pF VDD = 3.3 V ± 10 %	2.5
IDCMAX_S	CC	D	Maximum DC current	VDD = 5 V ± 10 %	—
				VDD = 3.3 V ± 10 %	—
tSKEW_S	CC	T	Difference between rise and fall time, 90 %-10 %	—	—

Table 15. VERY STRONG/VERY FAST I/O output characteristics

Symbol		C	Parameter	Conditions	Value
					Min
Vol_V CC			Output low voltage for Very Strong type PADs	Iol = 9.0 mA VDD =5.0 V ± 10 %	—
		D		Iol = 9.0 mA VDD =3.3 V ± 10 %	—
Voh_V		CC D	Output high voltage for Very	Ioh = 9.0 mA VDD = 5.0 V ± 10 %	0.9*VDD
					Strong type PADs
R_V	CC	P	Output impedance for Very Strong type PADs	VDD = 5.0 V ± 10 %	20
				VDD = 3.3 V ± 10 %	18

					Value
Symbol		C	Parameter	Conditions	Min
Fmax_V CC			Maximum output frequency for Very Strong type PADs	CL = 25 pF VDD = 5.0 V ± 10 %	—
		T		CL = 50 pF VDD = 5.0 V ± 10 %	—
				CL = 25 pF VDD = 3.3 V ± 10 %	—
				CL = 50 pF VDD = 3.3 V ± 10 %	—
			10–90% threshold transition time output pin VERY STRONG configuration	CL = 25 pF VDD = 5.0 V ± 10 %	1
	CC	T		CL = 50 pF VDD = 5.0 V ± 10 %	3
tTR_V				CL = 25 pF VDD = 3.3 V ± 10 %	1.5
				CL = 50 pF VDD = 3.3 V ± 10 %	3
		T	20–80% threshold transition time	CL = 25 pF VDD = 5.0 V ± 10 %	0.8
tTR20-80_V	CC				output pin VERY STRONG configuration
tTRTTL_V	CC	T	TTL threshold transition time for output pin in VERY STRONG configuration (Ethernet standard)	CL = 25 pF VDD = 3.3 V ± 10 %	0.88
tTR20-80_V		T	Sum of transition time 20–80% output pin VERY STRONG configuration	CL = 25 pF VDD = 5.0 V ± 10 %	—
	CC			CL = 15 pF VDD = 3.3 V ± 10 %	—
tSKEW_V	CC	T	Difference between rise and fall delay	CL = 25 pF VDD = 5.0 V ± 10 %	0
IDCMAX_V	CC	D	Maximum DC current	VDD = 5.0 V±10 % VDD = 3.3 V ± 10 %	—

Table 15. VERY STRONG/VERY FAST I/O output characteristics (continued)

4.8.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in the device pinout Microsoft Excel file attached to the IO_Definition document.

Table 16 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IRMSSEG maximum value.

In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value.

Pad mapping on each segment can be optimized using the pad usage information provided on the I/O Signal Description table.

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
		Average consumption(2)
IRMSSEG	SR	D	Sum of all the DC I/O current within a supply segment	—	—	80	mA
IRMS_W	CC	D	RMS I/O current for WEAK configuration	CL = 25 pF, 2 MHz, VDD = 5.0 V ± 10 %	—	—	1.1
				CL = 50 pF, 1 MHz, VDD = 5

Table 16. I/O consumption

Symbol	C	D	Parameter	Conditions	Min	Typ	Max	Unit
Average consumption(2)
IRMSSEG	SR	D	Sum of all the DC I/O current within a supply segment	—	—	—	80	mA
IRMS_W	CC	D	RMS I/O current for WEAK configuration	CL = 25 pF, 2 MHz, VDD = 5.0 V ± 10 %	—	—	1.1	mA
				CL = 50 pF, 1

Table 16. I/O consumption (continued)

Electrical characteristics SPC584Bx

Symbol	C	D	Parameter	Conditions	Value(1)			Unit
					Min	Typ	Max
Average consumption(2)
IRMSSEG	SR	D	Sum of all the DC I/O current within a supply segment	—	—	—	80	mA
IRMS_W	CC	D	RMS I/O current for WEAK configuration	CL = 25 pF, 2 MHz, VDD = 5.0 V ± 10 %	—	—	1.1	mA

Table 16. I/O consumption (continued)

1. I/O current consumption specifications for the 4.5 V VDD_HV_IO 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and VSIO[VSIO_xx] = 0 for 3.0 V VDD_HV_IO 3.6 V.

2. Average consumption in one pad toggling cycle.

3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

4.9 Reset pad (PORST) electrical characteristics

The device implements dedicated bidirectional reset pins as below specified. PORST pin does not require active control. It is possible to implement an external pull-up to ensure correct reset exit sequence. Recommended value is 4.7 K.

Figure 5. Startup reset requirements

Figure 6 describes device behavior depending on supply signal on PORST:

• 1. PORST low pulse has too low amplitude: it is filtered by input buffer hysteresis. Device remains in current state.
• 1. PORST low pulse has too short duration: it is filtered by low pass filter. Device remains in current state.
• 1. PORST low pulse is generating a reset:
  • a) PORST low but initially filtered during at least WFRST. Device remains initially in current state.
  • b) PORST potentially filtered until WNFRST. Device state is unknown. It may either be reset or remains in current state depending on extra condition (temperature, voltage, device).
  • c) PORST asserted for longer than WNFRST. Device is under reset.

Figure 6. Noise filtering on reset signal

Table 17. Reset PAD electrical characteristics

Symbol		C	Parameter	Conditions	Value
					Min
VIHRES	SR	P	Input high level TTL	VDD_HV = 5.0 V ± 10 % VDD_HV = 3.3 V ± 10 %	2
VILRES	SR	P	Input low level	VDD_HV = 5.0 V ± 10 %	-0.3
			TTL	VDD_HV = 3.3 V ± 10 %	-0.3
VHYSRES	CC	C	Input hysteresis	VDD_HV = 5.0 V ± 10 %	0.3
			TTL	VDD_HV = 3.3 V ± 10 %	0.2
VDD_POR	CC	D	Minimum supply	VDD_HV = 5.0 V ± 10 %	—
			for strong pull down activation	VDD_HV = 3.3 V ± 10 %	—

Symbol	C	P	Parameter	Conditions	Min	Typ	Max	Unit
VIHRES	SR	P	Input high level TTL	VDD_HV = 5.0 V ± 10 % VDD_HV = 3.3 V ± 10 %	2	—	VDD_HV_IO +0.3	V
VILRES	SR	P	Input low level TTL	VDD_HV = 5.0 V ± 10 % VDD_HV = 3.3 V ± 10 %	-0.3	—	0.8 0.6	V
VHYSHRES	CC	C	Input hysteresis TTL	VDD_HV = 5.0 V ± 10 % VDD_HV = 3.3 V ± 10 %	0.3 0.2	—	—	V
VDD_POR	CC	D	Minimum supply for strong pull-down activation	VDD_HV = 5.0 V ± 10 % VDD_HV = 3.3 V ± 10 %	—	—	1.6 1.05	V

1. Iol_r applies to PORST: Strong Pull-down is active on PHASE0 for PORST. Refer to the device pinout IO definition excel file for details regarding pin usage.

2. Maximum current when forcing a change in the pin level opposite to the pull configuration.

1. Minimum current when keeping the same pin level state than the pull configuration.

Table 18. Reset PAD state during power-up and reset

PAD	POWER-UP State	RESET state	DEFAULT state(1)	STANDBY state
PORST	Strong pull-down	Weak pull-down	Weak pull-down	Weak pull-up

1. Before SW Configuration. Refer to the Device Reference Manual, Reset Generation Module (MC_RGM) Functional Description chapter for the details of the power-up phases.

4.10 PLLs

Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary clocks on the device.

Figure 7 depicts the integration of the two PLLs. Refer to device Reference Manual for more detailed schematic.

4.10.1 PLL0

Table 19. PLL0 electrical characteristics

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
fPLL0IN	SR	—	PLL0 input clock(1)	8	—	44	MHz
PLL0IN	SR	—	PLL0 input clock duty cycle(1)	40	—	60	%
fINFIN	SR	—	PLL0 PFD (Phase Frequency Detector) input clock frequency	8	—	20	MHz
fPLL0VCO	CC	P	PLL0 VCO frequency	600	—

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
fPLL0IN	SR	—	PLL0 input clock(1)	8	—	44	MHz
ΔPLL0IN	SR	—	PLL0 input clock duty cycle(1)	40	—	60	%
fINFIN	SR	—	PLL0 PFD (Phase Frequency Detector) input clock frequency	8	—	20	MHz
fPLL0VCO	CC	P	PLL0 VCO frequency	600	—	1400	MHz

Table 19. PLL0 electrical characteristics (continued)

1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode.

1. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency limit set for PLL1 (87.5 MHz, according to Table 20).

3. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin.

4. VDD_LV noise due to application in the range VDD_LV = 1.20 V±5 %, with frequency below PLL bandwidth (40 kHz) will be filtered.

4.10.2 PLL1

PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG) support.

Symbol					Value			Unit
		C	Parameter	Conditions	Min	Typ	Max
fPLL1IN	SR	—	PLL1 input clock(1)	—	37.5	—	87.5	MHz
PLL1IN	SR	—	PLL1 input clock duty cycle(1)	—	35	—	65	%
fINFIN	SR	—	PLL1 PFD (Phase Frequency Detector) input clock frequency	—	37.5	—	87.5	MHz
fPLL1VCO	CC	P	PLL1 VCO frequency	—	600	—	1400	MHz
fPLL1PHI0	CC	D	PLL1 output clock PHI0	—	4.762	—	FSYS(2)	MHz
tPLL1LOCK	CC	P	PLL1 lock time	—	—	—	50	μs
fPLL1MOD	CC	T	PLL1 modulation frequency	—	—	—	250	kHz
PLL1MOD	CC	T	PLL1 modulation depth (when enabled)	Center spread(3)	0.25	—	2	%
				Down spread	0.5	—	4	%
PLL1PHI0SPJ (4)	CC	T	PLL1_PHI0 single period peak to peak jitter	fPLL1PHI0 = 200 MHz, 6-sigma	—	—	500(5)	ps
IPLL1	CC	D	PLL1 consumption	FINE LOCK state	—	—	5	mA

			Table 20. PLL1 electrical characteristics
--	--	--	-------------------------------------------

1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when using internal PPL0 or external oscillator is used in functional mode.

2. Refer to Section 4.3: Operating conditions for the maximum operating frequency.

3. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected, the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD %). Refer to the Reference Manual for the PLL programming details.

4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin.

5. 1.25 V±5 %, application noise below 40 kHz at VDD_LV pin - no frequency modulation.

4.11 Oscillators

4.11.1 Crystal oscillator 40 MHz

Table 21. External 40 MHz oscillator electrical specifications

Symbol	C	Type	Parameter	Conditions	Min	Max	Unit
fXTAL	CC	D	Crystal Frequency Range(1)	—	4(2)	8	MHz
					>8	20
					>20	40
tcst	CC	T	Crystal start-up time (3),(4)	TJ = 150 °C	—	5	ms
trec	CC	D	Crystal recovery time(5)	—	—	0.5	ms
VIHEXT	CC	D

Symbol	C	Type	Parameter	Conditions	Min	Max	Unit
fXTAL	CC	D	Crystal Frequency Range(1)	—	4(2)	8	MHz
					>8	20
					>20	40
tcst	CC	T	Crystal start-up time (3),(4)	TJ = 150 °C	—	5	ms
trec	CC	D	Crystal recovery time(5)	—	—	0.5	ms
VIHEXT	CC

Table 21. External 40 MHz oscillator electrical specifications (continued)

1. The range is selectable by UTEST miscellaneous DCF client XOSC_FREQ_SEL.

2. The XTAL frequency, if used to feed the PPL0 (or PLL1), shall obey the minimum input frequency limit set for PLL0 (or PLL1).

3. This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided.

• 1. Proper PC board layout procedures must be followed to achieve specifications.
• 1. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value.
• 6. Applies to an external clock input and not to crystal mode.
• 7. See crystal manufacturer's specification for recommended load capacitor (CL) values.The external oscillator requires external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL) and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load capacitor value is selected via S/W to match the crystal manufacturer's specification, while accounting for on-chip and PCB capacitance.
• 8. Amplitude on the EXTAL pin after startup is determined by the ALC block, that is the Automatic Level Control Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions.
• 1. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator.

4.11.2 Crystal Oscillator 32 kHz

• fsxosc
• gmsxosc
• Vsxosc
• Isxoosc
• Tsxosc

Table 22. 32 kHz external slow oscillator electrical specifications

4.11.3 RC oscillator 16 MHz

		Table 23. Internal RC oscillator electrical specifications
------------	----	---
Symbol		C
fTarget	CC	D
fvar_noT	CC	P
fvar_T	CC	T
fvar_SW		T
Tstart_noT	CC	T
Tstart_T	CC	T
IFIRC	CC	T

4.11.4 Low power RC oscillator

Symbol			Parameter	Conditions
		C
Fsirc	CC	T	Slow Internal RC oscillator frequency	—
fvar_T	CC	P	Frequency variation across temperature	–40 °C < T < 150 °C
fvar_V	CC	P	Frequency variation across voltage	–40 °C < T < 150 °C
Isirc	CC	T	Slow Internal RC oscillator current	T = 55 °C
Tsirc	CC	T	Start up time, after switching ON the internal regulator.	—

Table 24. 1024 kHz internal RC oscillator electrical characteristics

4.12 ADC system

4.12.1 ADC input description

Figure 8 shows the input equivalent circuit for SARn and SARB channels.

Figure 8. Input equivalent circuit (Fast SARn and SARB channels)

All specifications in the following table valid for the full input voltage range for the analog inputs.

Symbol	C	D	Parameter	Conditions	Min	Max	Unit
R20K	CC	D	Internal voltage reference source impedance.	—	16	30	K
ILKG	CC	—	Input leakage current, two ADC channels on input-only pin.	See IO chapter Table 10: I/O input electrical characteristics, parameter ILKG.
IINJ1	SR	—	Injection current on analog input preserving functionality at full or degraded performances.	See Operating Conditions chapter Table 5: Operating conditions, IINJ1 parameter.
CHV_ADC	SR	D	VDD_HV_ADV external capacitance.	See Power Management chapter Table 33: External components integration, CADC parameter.
CP1	CC	D	Pad capacitance	See IO chapter Table 10: I/O input

Table 25. ADC pin specification

Symbol	C	Parameter	Conditions	Value	Unit
				Min	Max
R20KΩ	CC	Internal voltage reference source impedance.	—	16	30
ILKG	CC	Input leakage current, two ADC channels on input-only pin.	See IO chapter Table 10: I/O input electrical characteristics, parameter ILKG.
IINJ1	SR	Injection current on analog input preserving functionality at full or degraded performances.	See Operating Conditions chapter Table 5: Operating conditions, IINJ1 parameter.
CHV_ADC	SR	VDD_HV_ADV external capacitance.	See Power Management chapter Table 33: External components integration, CADC parameter.
CP1	CC	Pad capacitance	See IO chapter Table 10: I/O input electrical characteristics, parameter CP1.

1. It enables discharge of up to 100 nF from 5 V every 300 ms. Refer to the device pinout Microsoft Excel file attached to the IO_Definition document for the pads supporting it.

4.12.2 SAR ADC 12 bit electrical specification

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

Note: The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device.

Symbol	C	Parameter	Conditions	Min	Max	Unit
CP2	CC	Internal routing capacitance	SARB channels	—	2	pF
			SARn 10bit channels	—	0.5	pF
			SARn 12bit channels	—	1	pF
CS	CC	SAR ADC sampling capacitance	SARn 12bit	—	5	pF
			SARn 10bit	—	2	pF
RSWn	CC	Analog switches resistance	SARB channels	0	1.8	kΩ
			SARn 10bit channels	0	0.8	kΩ
			SARn 12bit channels	0	1.8	kΩ
RAD	CC	ADC input analog switches resistance	SARn 12bit	—	0.8	kΩ
			SARn 10bit	—	3.2	kΩ
RCMSW	CC	Common mode switch resistance	Sum of the two resistances	—	9	kΩ
RCMRL	CC	Common mode resistive ladder		—	9	kΩ
RSAFEPD(1)	CC	Discharge resistance for ADC input-only pins (strong pull-down for safety)	VDD_HV_IO = 5.0 V ± 10 %	—	300	W
			VDD_HV_IO = 3.3 V ± 10 %	—	500	W
ABGAP	CC	ADC digital bandgap accuracy		-1.5	+1.5	%
CEXT	SR	External capacitance at the pad input pin	To preserve the accuracy of the ADC, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be

Table 26. SARn ADC electrical specification
---------------------------------------------

Symbol	C	P	Parameter	Conditions	Value Min	Value Max	Unit
fADCK	SR	P	Clock frequency	Standard frequency mode	7.5	13.33	MHz
		T		High frequency mode	>13.33	16.0
tADCINIT	SR	-	ADC initialization time	-	1.5	-	µs
tADCBISINIT	SR	-	ADC BIAS initialization time	-	5	-	µs
tADCPRECH	SR	T	ADC decharge time	Fast SAR	1/fADCK	-	µs
				Slow SAR (SARDAC_B)	2/fADCK	-
ΔVPRECH	SR	D	Decharge voltage precision	TJ < 150 °C	0	0.25	V
R20KΩ	CC	D	Internal voltage reference source impedance	-	16	30	KΩ
ΔVINTREF	CC	P	Internal reference voltage precision	Applies to all internal reference points (VSS_HV_ADR, 1/3 * VDD_HV_ADR, 2/3 * VDD_HV_ADR, VDD_HV_ADR)	-0.20	0.20	V

Symbol	C	Parameter	Conditions	Min	Max	Unit
fADCK	SR	Clock frequency	Standard frequency mode	7.5	13.33	MHz
			High frequency mode	>13.33	16.0
tADCINIT	SR	ADC initialization time	—	1.5	—	μs
tADCBISINIT	SR	ADC BIAS initialization time	—	5	—	μs
tADCPRECH	SR	ADC decharge time	Fast SAR	1/fADCK	—	μs
			Slow SAR (SARDAC_B)	2/fADCK	—
ΔVPRECH	SR	Decharge voltage precision	TJ < 150 °C	0	0.25	V
R20KΩ	CC	Internal voltage reference source impedance	—	16	30	KΩ
ΔVINTREF	CC	Internal reference voltage precision	Applies to all internal reference points (VSS_HV_ADR, 1/3 * VDD_HV_ADR, 2/3 * VDD_HV_ADR, VDD_HV_ADR)	-0.20	0.20	V

Symbol	C	Parameter	Conditions	Value		Unit
				Min	Max
fADCK	SR	P	Clock frequency
			Standard frequency mode	7.5	13.33	MHz
		T	High frequency mode	>13.33	16.0
tADCINIT	SR	—	ADC initialization time	—	1.5	µs
tADCBISINIT	SR	—	ADC BIAS initialization time	—	5	µs
tADCPRECH

| Table 26. SARn ADC electrical specification | | :------- | :-- | :-------------------------------------- | :------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.

3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.

4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.

1. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

6. Current parameter values are for a single ADC.

• 7. TUE is granted with injection current within the range defined in Table 25, for parameters classified as T and D.
• 1. DNL is granted with injection current within the range defined in Table 25, for parameters classified as T and D.

4.12.3 SAR ADC 10 bit electrical specification

The ADC comparators are 10-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

Note: The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device.

Symbol	C	P	Parameter	Conditions	Min	Max	Unit
					Value
					Min	Max
fADCK	SR	P	Clock frequency	Standard frequency mode	7.5	13.33	MHz
		T		High frequency mode	>13.33	16.0
tADCINIT	SR	—	ADC initialization time	—	1.5	—	μs
tADCBIASINIT	SR	—	ADC BIAS initialization time	—	5

Symbol	C	Parameter	Conditions	Value Min	Value Max	Unit
fADCK	SR	Clock frequency	Standard frequency mode	7.5	13.33	MHz
	P		High frequency mode	>13.33	16.0
	T
tADCINIT	SR	ADC initialization time	—	1.5	—	μs
tADCBIA SINIT	SR	ADC BIAS initialization time	—	5	—	μs
tADCINITSBY	SR	ADC initialization time in standby

Table 27. ADC-Comparator electrical specification (continued)

Symbol	C	Parameter	Conditions	Min	Max	Unit
fADCK	SR	P	Clock frequency	7.5	13.33	MHz
		T	High frequency mode	>13.33	16.0
tADCINIT	SR	—	ADC initialization time	1.5	—	µs
tADCBASINIT	SR	—	ADC BIAS initialization time	5	—	µs
tADCINITSBY	SR	—	ADC initialization time in standby	8	—	µs
tADCPRECH
Table 27. ADC-Comparator electrical specification (continued)

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

2. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

3. Current parameter values are for a single ADC.

4. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection.

1. TUE is granted with injection current within the range defined in Table 25, for parameters classified as T and D.

2. DNL is granted with injection current within the range defined in Table 25, for parameters classified as T and D.

4.13 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

| | | | | | Value | Unit | |---|---|---|---|---|---|---|---| | Symbol | | C | Parameter | Conditions | Min | Typ | Max | Unit | | — | CC | — | Temperature monitoring range | — | –40 | — | 150 | °C | | TSENS | CC | T | Sensitivity | — | — | 5.18 | — | mV/°C | | TACC | CC | P | Accuracy | TJ < 150 °C | –3 | — | 3 | °C |

Table 28. Temperature sensor electrical characteristics

4.14 LFAST pad electrical characteristics

The LFAST(LVDS Fast Asynchronous Serial Transmission) pad electrical characteristics apply to high-speed debug serial interfaces on the device.

4.14.1 LFAST interface timing diagrams

Figure 9. LFAST LVDS timing definition

Figure 11. Rise/fall time

4.14.2 LFAST LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Table 29. LVDS pad startup and receiver electrical characteristics(1),(2)
---------------------------------------------------------------------------

		C	Parameter		Value
Symbol	STARTUP(3),(4)			Conditions	Min
tSTRT_BIAS	CC	T	Bias current reference startup time(5)	—	—
tPD2NM_TX	CC	T	Transmitter startup time (power down to normal mode)(6)	—	—

58/142 DS11701 Rev 4

</tj<>

					Value
Symbol		C	Parameter Conditions
					Min
tSM2NM_TX	CC	T	Transmitter startup time (sleep mode to normal mode)(7)	Not applicable to the MSC/DSPI LVDS pad	—
tPD2NM_RX	CC	T	Receiver startup time (power down to normal mode)(8)	—	—
tPD2SM_RX	CC	T	Receiver startup time (power down to sleep mode)(9)	Not applicable to the MSC/DSPI LVDS pad	—
ILVDS_BIAS	CC	D	LVDS bias current consumption TRANSMISSION LINE CHARACTERISTICS (PCB Track)	Tx or Rx enabled	—
Z0	SR	D	Transmission line characteristic impedance	—	47.5
ZDIFF	SR	D	Transmission line differential impedance	—	95
RECEIVER
VICOM	SR	T	Common mode voltage	—	0.15 (10)
VI	SR	T	Differential input voltage(12)	—	100
VHYS	CC	T	Input hysteresis	—	25
RIN	CC	D	Terminating resistance	VDD_HV_IO = 5.0 V ± 10 % -40 °C <tj< 150="" td="" °c<="">	80	—	150		80
				VDD_HV_IO = 3.3 V ± 10 % -40 °C <tj < 150 °C</tj	80
CIN	CC	D	Differential input capacitance(13)	—	—
ILVDS_RX	CC	C	Receiver DC current consumption	Enabled	—
IPIN_RX	CC	D	Maximum consumption on receiver input pin	VI = 400 mV, RIN = 80 	—
Table 29. LVDS pad startup and receiver electrical characteristics(1),(2) (continued)
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------

1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug (HSD) LVDS pad.

2. All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD modules don't take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding SIUL2 MSCR ODC field.

4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables.

5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled.

6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock periods.

7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode.

Electrical characteristics SPC584Bx

• 1. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.
• 1. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode.
• 1. Absolute min = 0.15 V (285 mV/2) = 0 V
• 1. Absolute max = 1.6 V + (285 mV/2) = 1.743 V
• 1. Value valid for LFAST mode. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive timing.
• 1. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

Symbol			Parameter	Conditions	Value
		C			Min
fDATA	SR	D	Data rate	—	—
VOS	CC	P	Common mode voltage	—	1.08
VOD	CC	P	Differential output voltage swing (terminated)(4),(5)	—	110
tTR	CC	T	Rise time from - VOD(min) to + VOD(min) . Fall time from + VOD(min) to - VOD(min)	—	0.26
CL SR			D	External lumped differential load	VDD_HV_IO = 4.5 V
ILVDS_TX	CC	C	Transmitter DC current consumption	Enabled	—
IPIN_TX	CC	D	Transmitter DC current sourced through output pin	—	1.1

Table 30. LFAST transmitter electrical characteristics(1),(2),(3)

1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101).

2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values shown in Figure 12.

3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

4. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in Figure 12.

1. Valid for maximum external load CL.

4.14.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
fRF_REF	SR	D	PLL reference clock frequency (CLKIN)	—	10(2)	—	30
ERRREF	CC	D	PLL reference clock frequency error	—	-1	—	1
DCREF	CC	D	PLL reference clock duty cycle (CLKIN)	—	30	—	70
PN	CC	D	Integrated phase noise (single side band)	fRF_REF = 20 MHz	—	—	-58
fVCO	CC	P	PLL VCO frequency	—	312	—	320(3)
tLOCK	CC	D	PLL phase lock	—	—	—	150(4)

		Table 31. LFAST PLL electrical characteristics(1)
--	--	---------------------------------------------------

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
fRF_REF	SR	D PLL reference clock frequency (CLKIN)	—	10$^{(2)}$	—	30	MHz
ERRREF	CC	D PLL reference clock frequency error	—	-1	—	1	%
DCREF	CC	D PLL reference clock duty cycle (CLKIN)	—	30	—	70	%
PN	CC	D Integrated phase noise (single side band)	fRF_REF = 20 MHz	—	—	-58	dBc
fVCO	CC	P PLL VCO frequency	—	312	—	320$^{(3)}$	MHz
tLOCK	CC	D PLL phase lock	—	—	—	150$^{(4)}$	µs

Table 31. LFAST PLL electrical characteristics(1) (continued)

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.

3. The 320 MHz frequency is achieved with a 20 MHz reference clock.

4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device (to set the PLL enable bit).

5. Measured at the transmitter output across a 100 termination resistor on a device evaluation board. See Figure 12.

4.15 Power management

The power management module monitors the different power supplies as well as it generates the required internal supplies. The device can operate in the following configurations:

Device	External regulator	Internal SMPS regulator	Internal linear regulator external ballast	Internal linear regulator internal ballast	Auxiliary regulator	Clamp regulator	Internal standby regulator(1)
SPC584Bx	—	—	X(2)	X	X	X	X

1. Standby regulator is automatically activated when the device enters standby mode.

2. For compatibility purpose with SPC584Cx/SPC58ECx, or for the optimization of the power dissipation, the operability of the device with external ballast can be used. The external ballast option is available only on specific devices, contact the local sales.

4.15.1 Power management integration

Use the integration schemes provided below to ensure the proper device function, according to the selected regulator configuration.

The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate VDD_LV supply.

Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH.

It is recommended to use the internal regulators only to supply the device itself.

Figure 13. Internal regulator with external ballast mode

Figure 14. Internal regulator with internal ballast mode

Figure 15. Standby regulator with external ballast mode

	Figure 16. Standby regulator with internal ballast mode
Symbol
-------------------	----
Common Components
CE	SR
RE	SR
CLVn	SR
RLVn	SR
CBV	SR
CHVn	SR

Table 33. External components integration

Symbol	C	Parameter	Conditions(1)	Min	Typ	Max	Unit
Common Components
CE	SR	D	Internal voltage regulator stability external capacitance(2) (3)	1.1	2.2	3.0	µF
RE	SR	D	Stability capacitor equivalent serial resistance	Total resistance including board track	—	—	50
CLVn	SR	D	Internal voltage regulator decoupling external capacitance(3) (4) (5)	Each VDD_LV/VSS pair	—	47	—
RLVn	SR	D	Stability capacitor equivalent serial resistance	—	—	—	50
CBV	SR	D	Bulk capacitance for HV supply(3)	on one VDD_HV_IO_MAIN/ VSS pair	—	4.7	—
CHVn	SR	D	Decoupling capacitance for ballast and IOs(3)	on all VDD_HV_IO/VSS and VDD_HV_ADV/VSS pairs	—	100	—

Table 33. External components integration (continued)

1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TJ = –40 / 150 °C, unless otherwise specified.

2. Recommended X7R or X5R ceramic –50 % / +35 % variation across process, temperature, voltage and after aging.

3. CE capacitance is required both in internal and external regulator mode.

4. For noise filtering, add a high frequency bypass capacitance of 10 nF.

1. For applications it is recommended to implement at least 5 CLV capacitances.

2. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF.

3. CB capacitance is required if only the external ballast is implemented.

4.15.2 Voltage regulators

Symbol			C Parameter		Value
				Conditions	Min
VMREG	CC	P		Power-up, before trimming, no load	1.14
	CC	P	Main regulator output voltage	After trimming, maximum load	1.09
			Main regulator current provided to	Internal ballast	—
IDDMREG	CC	T	VDD_LV domain The maximum current supported is the sum of the Main Regulator and the Auxiliary Regulator maximum current both regulators are working in parallel.	External ballast	—
IDDCLAMP	CC	D	Main regulator rush current sinked from VDD_HV_IO_MAIN domain during VDD_LV domain loading	Power-up condition	—
IDDMREG	CC	T	Main regulator output current variation	20 μs observation window	-100
		D	Main regulator current	IMREG = max	—
IMREGINT		CC	D	consumption	IMREG = 0 mA

Table 34. Linear regulator specifications

Table 35. Auxiliary regulator specifications

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
VAUX	CC P	Aux regulator output voltage	After trimming, internal regulator mode	1.09	1.19	1.22	V
IDDAUX	CC T	Aux regulator current provided to VDD_LV domain	—	—	—	150	mA
IDDAUX	CC T	Aux regulator current variation	20 μs observation window	-100	—	100	mA
IAUXINT	CC D	Aux regulator current consumption	IMREG = max	—	—	1.1	mA
	D		IMREG = 0 mA	—	—	1.1	mA

Electrical characteristics SPC584Bx

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
VAUX	CC	P	Aux regulator output voltage	After trimming, internal regulator mode	1.09	1.19	1.22
IDDAUX	CC	T	Aux regulator current provided to VDD_LV domain	—	—	150	mA
ΔIDDAUX	CC	T	Aux regulator current variation	20 μs observation window	-100	—	100
IAUXINT	CC	D	Aux regulator current consumption	IMREG = max	—

Table 36. Clamp regulator specifications

Table 37. Standby regulator specifications

Symbol	C		Parameter	Conditions	Min	Typ	Max	Unit
					Min	Typ	Max
VSBY	CC	P	Standby regulator output voltage	After trimming, maximum load	1.02	1.06	1.26	V
IDDSBY	CC	T	Standby regulator current provided to VDD_LV domain	External Ballast	—	—	50	mA
				Internal Ballast	—	—	10	mA

4.15.3 Voltage monitors

The monitors and their associated levels for the device are given in Table 38. Figure 17 illustrates the workings of voltage monitoring threshold.

Symbol	C	Supply/Parameter(1)	Conditions	Min	Typ	Max	Unit
		PowerOn Reset HV
VPOR200_C	CC	P	VDD_HV_IO_MAIN	—	1.80	2.18	2.40
		Minimum Voltage Detectors HV
VMVD270_C	CC	P	VDD_HV_IO_MAIN	—	2.71	2.76	2.80
VMVD270

		Table 38. Voltage monitor electrical characteristics

Symbol	C	Supply/Parameter(1)	Conditions	Min	Typ	Max	Unit
PowerOn Reset HV
VPOR200_C	CC	P	VDD_HV_IO_MAIN	—	1.80	2.18	2.40
Minimum Voltage Detectors HV
VMVD270_C	CC	P	VDD_HV_IO_MAIN	—	2.71	2.76	2.80
VMVD270_F	CC	P	VDD_HV_FLA	—	2.71	2.76	2.80
VMVD270_SBY	CC	P	VDD_HV_IO_MAIN (in Standby)	—	2.71	2.76	2.80
Low Voltage Detectors HV
VLVD290_C	CC	P	VDD_HV_IO_MAIN	—	2.89	2.94	2.99
VLVD290_F	CC	P	VDD_HV_FLA	—	2.89	2.94	2.99
VLVD290_AS	CC	P	VDD_HV_ADV (ADCSAR pad)	—	2.89	2.94	2.99
VLVD290_IF	CC	P	VDD_HV_IO_ETH	—	2.89	2.94	2.99
VLVD400_AS	CC

1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented. For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing the limitations provided in Section 4.2: Absolute maximum ratings.

2. The values reported are Trimmed values, where applicable.

3. See Figure 17. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations.

4.16 Flash

The following table shows the Wait state configuration.

APC	RWSC	Frequency range (MHz)
000(1)	0	f ≤ 30
	1	f ≤ 60
	2	f ≤ 90
	3	f ≤ 120
100(2)	0	f ≤ 30
	1	f ≤ 60
	2	f ≤ 90
	3	f ≤ 120
001(3)	2	55 < f ≤ 80
	3	55 < f ≤ 120

1. STD pipelined, no address anticipation.

2. No pipeline (STD + 1 Tck).

3. Pipeline with 1 Tck address anticipation.

The following table shows the Program/Erase characteristics.

Table 40. Flash memory program and erase specifications
---------------------------------------------------------

		Value
Symbol	Characteristics(1)(2)	Typ(3)
tdwprogram	Double Word (64 bits) program time [Packaged part]	43
tpprogram	Page (256 bits) program time	72
tpprogrameep	Page (256 bits) program time Data Flash - EEPROM (partition 1) [Packaged part]	83
tqprogram	Quad Page (1024 bits) program time	220
tqprogrameep	Quad Page (1024 bits) program time Data Flash - EEPROM (partition 1) [Packaged part]	245

	Table 40. Flash memory program and erase specifications (continued)
----------------	---------------------------------------------------------------------------
Symbol	Characteristics(1)(2)
t16kpperase	16 KB block pre-program and erase time
t32kpperase	32 KB block pre-program and erase time
t64kpperase	64 KB block pre-program and erase time
t128kpperase	128 KB block pre-program and erase time
t256kpperase	256 KB block pre-program and erase time
t16kprogram	16 KB block program time
t32kprogram	32 KB block program time
t64kprogram	64 KB block program time
t128kprogram	128 KB block program time
t256kprogram	256 KB block program time
t16kprogrameep	Program 16 KB Data Flash - EEPROM (partition 1) [Packaged part]
t16keraseeep	Erase 16 KB Data Flash - EEPROM (partition 1) [Packaged part]
t16kprogrameep	Program 16 KB HSM Data Flash - EEPROM (partition 1) [Packaged part]
t16keraseeep	Erase 16 KB HSM Data Flash - EEPROM (partition 1) [Packaged part]
tprr	Program rate(8)
tpr	Erase rate(8)
ttprfm	Program rate Factory Mode(8)
terfm	Erase rate Factory Mode(8)
tffprogram	Full flash programming time(9)

		Value
Symbol	Characteristics(1)(2)	Typ(3)
tfferase	Full flash erasing time(9)	9.9
tESRT	Erase suspend request rate(10)
tPSRT	Program suspend request rate(10)	30
tAMRT	Array Integrity Check - Margin Read suspend request rate	15
tPSUS	Program suspend latency(11)	—
tESUS	Erase suspend latency(11)	—
tAIC0S	Array Integrity Check (2.0 MB, sequential)(12)	12.8
tAIC256KS	Array Integrity Check (256 KB, sequential)(12)	1.5
tAIC0P	Array Integrity Check (2.0 MB, proprietary)(12)	4.0
tMR0S	Margin Read (2.0 MB, sequential)(12)	35
tMR256KS	Margin Read (256 KB, sequential)(12)	4.0

Table 40. Flash memory program and erase specifications (continued)
---------------------------------------------------------------------

1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.

2. Actual hardware operation times; this does not include software overhead.

3. Typical program and erase times assume nominal supply values and operation at 25 °C.

• 1. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but not tested.
• 1. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
• 1. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5 %) supply voltages.
• 1. Initial maximum "All temp" program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5 %) supply voltages.
• 8. Rate computed based on 256 KB sectors.
• 9. Only code sectors, not including EEPROM.
• 10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.
• 11. Timings guaranteed by design.
• 12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the table is calculated at max frequency.

All the Flash operations require the presence of the system clock for internal synchronization. About 50 synchronization cycles are needed: this means that the timings of the previous table can be longer if a low frequency system clock is used.

	Characteristics(1) (2)
Symbol
NCER16K	16 KB CODE Flash endurance
NCER32K	32 KB CODE Flash endurance
NCER64K	64 KB CODE Flash endurance
NCER128K	128 KB CODE Flash endurance
256 KB CODE Flash endurance
NCER256K	256 KB CODE Flash endurance(3)
NDER16K	16 KB DATA EEPROM Flash endurance
NDER16K	16 KB HSM DATA EEPROM Flash endurance
tDR1k	Minimum data retention Blocks with 0 - 1,000 P/E cycles
tDR10k	Minimum data retention Blocks with 1,001 - 10,000 P/E cycles
tDR100k	Minimum data retention Blocks with 10,001 - 100,000 P/E cycles
tDR250k	Minimum data retention Blocks with 100,001 - 250,000 P/E cycles

				Table 41. Flash memory life specification
--	--	--	--	-------------------------------------------

1. Program and erase cycles supported across specified temperature specifications.

2. It is recommended that the application enables the core cache memory.

3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time are possible.

4.17 AC specifications

All AC timing specifications are valid up to 150 °C, except where explicitly noted.

4.17.1 Debug and calibration interface timing

4.17.1.1 JTAG interface timing

	Symbol				Value(1),(2)		Unit
#			C	Characteristic	Min	Max
1	tJCYC	CC	D	TCK cycle time	100	—	ns
2	tJDC	CC	T	TCK clock pulse width	40	60	%
3	tTCKRISE	CC	D	TCK rise and fall times (40 %–70 %)	—	3	ns
4	tTMSS, tTDIS	CC	D	TMS, TDI data setup time	5	—	ns
5	tTMSH, tTDIH	CC	D	TMS, TDI data hold time	5	—	ns
6	tTDOV	CC	D	TCK low to TDO data valid	—	15(3)	ns
7	tTDOI	CC	D	TCK low to TDO data invalid	0	—	ns
8	tTDOHZ	CC	D	TCK low to TDO high impedance	—	15	ns
9	tJCMPPW	CC	D	JCOMP assertion time	100	—	ns
10	tJCMPS	CC	D	JCOMP setup time to TCK low	40	—	ns
11	tBSDV	CC	D	TCK falling edge to output valid	—	600(4)	ns
12	tBSDVZ	CC	D	TCK falling edge to output valid out of high impedance	—	600	ns
13	tBSDHZ CC D			TCK falling edge to output high impedance	—	600	ns
14	tBSDST CC D Boundary scan input valid to TCK rising edge			15	—	ns
15	tBSDHT	CC	D	TCK rising edge to boundary scan input invalid	15	—	ns

Table 42. JTAG pin AC electrical characteristics

1. These specifications apply to JTAG boundary scan only. See Table 43 for functional specifications.

2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the datasheet.

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Figure 21. JTAG boundary scan timing

DS11701 Rev 4 79/142

4.17.1.2 Nexus interface timing

	Symbol		C	Characteristic		Value(1)
#						Max
7	tEVTIPW	CC	D	EVTI pulse width	4	—
8	tEVTOPW	CC	D	EVTO pulse width	40	—
9	tTCYC			TCK cycle time	2(3),(4)	—
		CC	D	Absolute minimum TCK cycle time(5) (TDO sampled on posedge of TCK) Absolute minimum TCK cycle time(7) (TDO sampled on negedge of TCK)	40(6) 20(6)	—
11	tNTDIS	CC	D	TDI data setup time	5	—
12	tNTDIH	CC	D	TDI data hold time	5	—
13	tNTMSS	CC	D	TMS data setup time	5	—
14	tNTMSH	CC	D	TMS data hold time	5	—
15	—	CC	D	TDO propagation delay from falling edge of TCK(8)	—	16
16	—	CC	D	TDO hold time with respect to TCK falling edge (minimum TDO propagation delay)	2.25	—

Table 43. Nexus debug port timing

1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O section of the data sheet.

• 2. tCYC is system clock period.
• 1. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here.
• 1. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification.
• 1. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.
• 6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.
• 1. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge.
• 1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

Figure 23. Nexus event trigger and test clock timings

4.17.1.3 External interrupt timing (IRQ pin)

Table 44. External interrupt timing

Characteristic	Symbol	Min	Max	Unit
IRQ Pulse Width Low	tIPWL	3	—	tcyc
IRQ Pulse Width High	tIPWH	3	—	tcyc
IRQ Edge to Edge Time(1)	tICYC	6	—	tcyc

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

4.17.2 DSPI timing with CMOS pads

DSPI channel frequency support is shown in Table 45. Timing specifications are shown in the tables below.

	Max usable frequency (MHz)(2),(3)
	Full duplex – Classic timing (Table 46)
	Full duplex – Modified timing (Table 47)
CMOS (Master
mode)	Output only mode (SCK/SOUT/PCS) (Table 46 and Table 47)
	Output only mode TSB mode (SCK/SOUT/PCS)
	CMOS (Slave mode Full duplex) (Table 48)

1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum performance with every possible combination of pins.

2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

3. Maximum usable frequency does not take into account external device propagation delay.

4.17.2.1 DSPI master mode full duplex timing with CMOS pads

4.17.2.1.1 DSPI CMOS master mode – classic timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Table 46. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1

#	Symbol			Characteristic	Condition		Value(1)
			C		Pad drive(2)	Load (CL)	Min
1	tSCK			D SCK cycle time	SCK drive strength
		CC			Very strong	25 pF	59.0
					Strong	50 pF	80.0 Medium

						Condition		Value(1)
#	Symbol		C	Characteristic	Pad drive(2) SCK and PCS drive strength	Load (CL)	Min	Max
				D PCS to SCK	Very strong	25 pF	(N(3) × tSYS(4)) – 16	—
2		CC			Strong	50 pF	(N(3) × tSYS(4)) – 16	—
	tCSC			delay	Medium PCS medium and SCK strong SCK and PCS drive strength	50 pF PCS = 50 pF SCK = 50 pF	(N(3) × tSYS(4)) – 16 (N(3) × tSYS(4)) – 29	— —
	tASC CC				Very strong	PCS = 0 pF SCK = 50 pF	(M(5) × tSYS(4)) – 35	—
3		CC		D After SCK delay D SCK duty	Strong Medium	PCS = 0 pF SCK = 50 pF PCS = 0 pF SCK = 50 pF SCK drive strength	(M(5) × tSYS(4)) – 35 (M(5) × tSYS(4)) – 35 PCS medium and SCK strong	— — PCS = 0 pF SCK = 50 pF
					Very strong	0 pF	1/2tSCK – 2	1/2tSCK + 2
4	tSDC			cycle(6)	Strong	0 pF PCS strobe timing	1/2tSCK – 2	1/2tSCK + 2
5	tPCSC	CC		D PCSx to PCSS	PCS and PCSS drive strength
6	tPASC	CC		D PCSS to PCSx	PCS and PCSS drive strength
				time(7)	Strong SCK drive strength	25 pF SIN setup time	16.0	—
7	tSUI	CC	D SIN setup time to SCK(8)		Very strong	25 pF	25.0	—
					Strong	50 pF	31.0	—

Table 46. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1 (continued)

Table 46. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1 (continued)

	Symbol					Condition		Value(1)
#			C	Characteristic D SIN hold time from SCK(8)	Pad drive(2) SCK drive strength	Load (CL) SIN hold time	Min	Max
					Very strong	0 pF	–1.0	—
8	tHI SOUT data valid time (after SCK edge) tSUO	CC			Strong SOUT and SCK drive strength	0 pF	–1.0 Medium	— 0 pF
9		CC		D SOUT data valid	Very strong	25 pF	—	7.0
				time from SCK(9) D SOUT data hold	Strong SOUT and SCK drive strength	50 pF SOUT data hold time (after SCK edge)	—	8.0
10		CC			Very strong	25 pF	–7.7	—
	tHO			time after SCK(9)	Strong Medium	50 pF 50 pF	–11.0 –15.0	— —

1. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

1. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10 % – 90 %) and uses TTL voltage thresholds.

9. SOUT Data valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 27. DSPI CMOS master mode — classic timing, CPHA = 0

Figure 29. DSPI PCS strobe (PCSS) timing (master mode)

4.17.2.1.2 DSPI CMOS master mode — modified timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Table 47. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1

	Symbol				Condition		Value(1)
#			C	Characteristic	Pad drive(2) SCK drive strength	Load (CL)	Min
		CC		D SCK cycle time	Very strong	25 pF	33.0
1	tSCK				Strong	50 pF	80.0
					Medium SCK and PCS drive strength	50 pF	200.0
	tCSC			D PCS to SCK delay	Very strong	25 pF	(N(3) × tSYS(4)) – 16
2		CC			Strong	50 pF	(N(3) × tSYS(4)) – 16
					Medium	50 pF	(N(3) × tSYS(4)) – 16
	tASC				CC
3							D After SCK delay
					PCS medium and SCK strong	PCS = 0 pF SCK = 50 pF	(M(5) × tSYS(4)) – 35

				C Characteristic		Condition	Value(1)
#		Symbol			Pad drive(2) SCK drive strength	Load (CL)	Min
4				D SCK duty cycle(6)	Very strong	0 pF	1/2tSCK – 2
	tSDC	CC			Strong	0 pF	1/2tSCK – 2
					Medium	0 pF PCS strobe timing	1/2tSCK – 5
5	tPCSC CC			D PCSx to PCSS time(7)	PCS and PCSS drive strength
					Strong	25 pF	16.0
6	tPASC	CC
	SIN setup time			SIN setup time to SCK CPHA = 0(8)	SCK drive strength		Strong
					Very strong	25 pF	25 – (P(9) × tSYS(4))
					Strong	50 pF	(9) × tSYS(4)) 31 – (P
7	tSUI	CC	D		Medium SCK drive strength	50 pF	52 – (P(9) × tSYS(4))
					SCK	SIN setup time to	Very strong
					Medium SCK drive strength	50 pF SIN hold time	52.0
					SIN hold time from SCK	Very strong	0 pF
				CPHA = 0(8)	Strong	0 pF	(9) × tSYS(3)) –1 + (P
8	tHI	CC	D		Medium SCK drive strength	0 pF	–1 + (P(9) × tSYS(3))
				SIN hold time from SCK	Very strong	0 pF	–1.0
				CPHA = 1(8)	Strong	0 pF	–1.0
							Medium

Table 47. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1 (continued)

					Condition		Value(1)
#	Symbol		C	Characteristic	Pad drive(2) SOUT and SCK drive strength	Load (CL) SOUT data valid time (after SCK edge)	Min
				SOUT data valid time from SCK	Very strong	25 pF	—
				CPHA = 0, (10)	Strong	50 pF	—
					Medium	50 pF	—
9	tSUO	CC	D		SOUT and SCK drive strength
				SOUT data valid time from SCK CPHA = 1(10)	Very strong	25 pF	—
					Strong	50 pF	—
					SOUT and SCK drive strength	SOUT data hold time (after SCK edge)	Medium
			D
						CPHA = 0(10)	Strong
					Medium	50 pF	–15.0 + tSYS(4)
10	tHO	CC				SOUT and SCK drive strength
					SOUT data hold time after SCK	Very strong	25 pF
				CPHA = 1(10)	Strong	50 pF	–11.0
					Medium	50 pF	–15.0

Table 47. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1 (continued)

1. All timing values for output signals in this table are measured to 50 % of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

• 3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).
• 4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns).
• 5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).
• 1. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
• 7. PCSx and PCSS using same pad configuration.
• 8. Input timing assumes an input slew rate of 1 ns (10 % – 90 %) and uses TTL voltage thresholds.
• 9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_ MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1.

10. SOUT Data valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 30. DSPI CMOS master mode — modified timing, CPHA = 0

Figure 31. DSPI CMOS master mode — modified timing, CPHA = 1

Figure 32. DSPI PCS strobe (PCSS) timing (master mode)

4.17.2.2 Slave mode timing

Table 48. DSPI CMOS slave timing — full duplex — normal and modified transfer formats (MTFE = 0/1)

	Symbol			Characteristic	Condition
#			C		Pad Drive
1	tSCK	CC	D	SCK Cycle Time(1)	—
2	tCSC	SR	D	SS to SCK Delay(1)	—
3	tASC	SR	D	SCK to SS Delay(1)	—
4	tSDC	CC	D	SCK Duty Cycle(1)	—
				Slave Access Time(1) (2) (3) (SS active to SOUT driven)	Very strong
5	tA	CC	D		Strong
					Medium
		CC	D	Slave SOUT Disable Time(1) (2) (3) (SS inactive to SOUT High Z or invalid)	Very strong
6	tDIS				Strong
					Medium
9	tSUI	CC	D	Data Setup Time for Inputs(1)	—
10	tHI	CC	D	Data Hold Time for Inputs(1)	—
11	tSUO	CC
			D	(after SCK edge)	Strong
					Medium
		CC
12	tHO		D	(after SCK edge)	Strong

2. All timing values for output signals in this table, are measured to 50 % of the output voltage.

3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Figure 33. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0

4.17.3 Ethernet timing

The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. Check the device pinout details to review the packages supporting MII and RMII.

4.17.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1 %. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.

Note: In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

Symbol		C	Characteristic	Value		Unit
				Min	Max
M1	CC		D RXD[3:0], RX_DV, RX_ER to RX_CLK setup	5	—	ns
M2	CC		D RX_CLK to RXD[3:0], RX_DV, RX_ER hold	5	—	ns
M3	CC		D RX_CLK pulse width high	35 %	65 %	RX_CLK period
M4	CC		D RX_CLK pulse width low	35 %	65 %	RX_CLK period

	Table 49. MII receive signal timing

4.17.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1 %. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This option allows the use of non-compliant MII PHYs.

Refer to the SPC584Bx 32-bit Power Architecture microcontroller reference manual's Ethernet chapter for details of this option and how to enable it.

Note: In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

Symbol		C	Characteristic		Value(1)	Unit
				Min	Max
M5	CC		D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid	5	—	ns
M6	CC		D TX_CLK to TXD[3:0], TX_EN, TX_ER valid	—	25	ns
M7	CC		D TX_CLK pulse width high	35 %	65 %	TX_CLK period
M8	CC		D TX_CLK pulse width low	35 %	65 %	TX_CLK period

Table 50. MII transmit signal timing

1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value

Figure 36. MII transmit signal timing diagram

4.17.3.3 MII async inputs signal timing (CRS and COL)

Table 51. MII async inputs signal timing

Symbol		C			Value	Unit
			Characteristic	Min	Max
M9 CC			D CRS, COL minimum pulse width	1.5	—	TX_CLK period

Figure 37. MII async inputs timing diagram

4.17.3.4 MII and RMII serial management channel timing (MDIO and MDC)

The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.

Figure 38. MII serial management channel timing diagram

4.17.3.5 MII and RMII serial management channel timing (MDIO and MDC)

The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.

Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50 % to 2.2 V/3.5 V input and output levels.

Symbol		C	Characteristic		Value	Unit
				Min	Max
M10	CC		D MDC falling edge to MDIO output invalid (minimum propagation delay)	0	—	ns
M11	CC		D MDC falling edge to MDIO output valid (maximum propagation delay)	—	25	ns
M12	CC		D MDIO (input) to MDC rising edge setup	10	—	ns
M13	CC		D MDIO (input) to MDC rising edge hold	0	—	ns
M14	CC		D MDC pulse width high	40 %	60 %	MDC period
M15	CC		D MDC pulse width low	40 %	60 %	MDC period

Table 52. MII serial management channel timing
------------------------------------------------

Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50 % to 2.2 V/3.5 V input and output levels.

Symbol		C	Characteristic	Value		Unit
				Min	Max
M10	CC		D MDC falling edge to MDIO output invalid (minimum propagation delay)	0	—	ns
M11	CC		D MDC falling edge to MDIO output valid (maximum propagation delay)	—	25	ns
M12	CC		D MDIO (input) to MDC rising edge setup	10	—	ns
M13	CC		D MDIO (input) to MDC rising edge hold	0	—	ns
M14	CC		D MDC pulse width high	40 %	60 %	MDC period
M15	CC		D MDC pulse width low	40 %	60 %	MDC period

Table 53. RMII serial management channel timing

Figure 39. MII serial management channel timing diagram

4.17.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1 %. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency.

Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

Symbol		C	Characteristic	Value		Unit
				Min	Max
R1	CC		D RXD[1:0], CRS_DV to REF_CLK setup	4	—	ns
R2	CC		D REF_CLK to RXD[1:0], CRS_DV hold	2	—	ns
R3	CC		D REF_CLK pulse width high	35 %	65 %	REF_CLK period
R4	CC		D REF_CLK pulse width low	35 %	65 %	REF_CLK period

Figure 40. RMII receive signal timing diagram

4.17.3.7 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1 %. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This option allows the use of non-compliant RMII PHYs.

Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on the pad as 1ns.

					Value
Symbol		C	Characteristic	Min	Max
R5	CC		D REF_CLK to TXD[1:0], TX_EN invalid	2	—
R6	CC		D REF_CLK to TXD[1:0], TX_EN valid	—	14
R7	CC		D REF_CLK pulse width high	35 %	65 %
R8	CC		D REF_CLK pulse width low	35 %	65 %

Figure 41. RMII transmit signal timing diagram

4.17.4 CAN timing

The following table describes the CAN timing.

Symbol			Parameter		Value
		C		Condition	Min
	CC	D	CAN controller propagation delay time standard pads	Medium type pads 25 pF load	—
	CC	D		Medium type pads 50 pF load	—
tP(RX:TX)	CC	D		STRONG, VERY STRONG type pads 25 pF load	—
	CC	D		STRONG, VERY STRONG type pads 50 pF load	—
	CC	D	CAN controller propagation delay time low power pads	Medium type pads 25 pF load	—
	CC	D		Medium type pads 50 pF load	—
tPLP(RX:TX)	CC	D		STRONG, VERY STRONG type pads 25 pF load	—
	CC	D		STRONG, VERY STRONG type pads 50 pF load	—

Table 56. CAN timing

4.17.5 UART timing

UART channel frequency support is shown in the following table.

LINFlexD clock frequency LIN_CLK (MHz)	Oversampling rate	Voting scheme	Max usable frequency (Mbaud)
	16	3:1 majority voting	5
	8		10
80	6	Limited voting on one	13.33
	5	sample with configurable	16
	4	sampling point	20
	16	3:1 majority voting	6.25
	8		12.5
100	6	Limited voting on one	16.67
	5	sample with configurable	20
	4	sampling point	25

Table 57. UART frequency support

4.17.6 I2C timing

The I2C AC timing specifications are provided in the following tables.

Note: In the following table, I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1 ns (10 % – 90 %).

	No. Symbol		C	Parameter	Value		Unit
					Min	Max
1	—	CC		D Start condition hold time	2	—	PER_CLK Cycle(1)
2	—	CC		D Clock low time	8	—	PER_CLK Cycle
3	—	CC		D Bus free time between Start and Stop condition	4.7	—	μs
4	—	CC		D Data hold time	0.0	—	ns
5	—	CC		D Clock high time	4	—	PER_CLK Cycle
6	—	CC		D Data setup time	0.0	—	ns
7	—	CC		D Start condition setup time (for repeated start condition only)	2	—	PER_CLK Cycle
8	—	CC		D Stop condition setup time	2	—	PER_CLK Cycle

		Table 58. I2C input timing specifications – SCL and SDA
--	--	---------------------------------------------------------

1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail.

Note: In the following table:

• All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

• Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

• Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

• Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.

	No. Symbol		C		Value
				Parameter	Min
1	—	CC	D	Start condition hold time	6
2	—	CC	D	Clock low time	10
3	—	CC	D	Bus free time between Start and Stop condition	4.7
4	—	CC	D	Data hold time	7
5	—	CC	D	Clock high time	10
6	—	CC	D	Data setup time	2
7	—	CC	D	Start condition setup time (for repeated start condition only)	20
8	—	CC	D	Stop condition setup time	10

Table 59. I2C output timing specifications — SCL and SDA

1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail.

Figure 42. I2C input/output timing

DS11701 Rev 4 101/142

Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device.

Symbol	C	Parameter	Conditions	Min	Typ	Max	Unit
VDD_LV	SR	D	Core voltage operating life range(1)	—	–0.3	—	1.4
VDD_HV_IO_MAIN VDD_HV_IO_ETH VDD_HV_OSC VDD_HV_FLA	SR	D	I/O supply voltage(2)	—	–0.3	—	6.0
VSS_HV_ADV	SR	D	ADC ground<br

Table 4. Absolute maximum ratings
-----------------------------------

Symbol			Parameter		Value
		C		Conditions	Min
TSTG	SR	T	Maximum non operating Storage temperature range	—	–55
TPAS	SR	C	Maximum nonoperating temperature during passive lifetime	—	–55
TSTORAGE	SR	—	Maximum storage time, assembled part programmed in ECU	No supply; storage temperature in range –40 °C to 60 °C	—
TSDR	SR	T	Maximum solder temperature Pb free packaged(8)	—	—
MSL	SR	T	Moisture sensitivity level(9)	—	—
TXRAY dose	SR	T	Maximum cumulated XRAY dose	Typical range for X-rays source during inspection:80 ÷ 130 KV; 20 ÷ 50 A	—

		Table 4. Absolute maximum ratings

2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions.

• 1. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations.
• 1. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
• 1. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time.
• 1. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 4.8.3: I/O pad current specifications.
• 1. 175 °C are allowed for limited time. Mission profile with passive lifetime temperature >150 °C have to be evaluated by ST to confirm that are granted by product qualification.
• 1. Solder profile per IPC/JEDEC J-STD-020D.

1. Moisture sensitivity per JDEC test method A112.

The following tables describe the thermal characteristics of the device. The parameters in this chapter have been evaluated by considering the device consumption configuration reported in the Section 4.7: Device consumption.

5.5.1 eTQFP64

Symbol		C	Parameter(1)	Conditions	Value	Unit
RJA	CC	D	Junction-to-Ambient, Natural Convection(2)	Four layer board (2s2p)	30.8	°C/W
RJMA	CC	D	Junction-to-Moving-Air, Ambient(2)	at 200 ft./min., four layer board (2s2p)	24.4	°C/W
RJB	CC	D	Junction-to-board(3)	—	12.1	°C/W
RJCtop	CC	D	Junction-to-case top(4)	—	15.2	°C/W
RJCbottom	CC	D	Junction-to-case bottom(5)	—	4.5	°C/W
JT	CC	D	Junction-to-package top(6)	Natural convection	3.7	°C/W

Table 69. Thermal characteristics for 64 exposed pad eTQFP package

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

• 1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
• 1. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance.
• 1. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.