MAX11162

Part: MAX11156 — Maxim Integrated

Type: 18-bit SAR ADC

Description: 18-bit, 500ksps SAR ADC with a ±5V bipolar input range, 5V analog supply, internal 4.096V reference and buffer, 94.6dB SNR (typ) and ±2.8 LSB INL (typ), with an SPI-compatible serial interface.

Operating Conditions:

• Analog supply voltage (VDD): 4.75–5.25 V
• Interface supply voltage (OVDD): 2.3–5.25 V
• Operating temperature: -40 to +85 °C
• Sample rate: 0.01–500 ksps

Absolute Maximum Ratings:

• VDD to GND: -0.3 to +6 V
• OVDD to GND: -0.3 V to the lower of (VDD + 0.3 V) and +6 V
• Maximum current into any pin: 50 mA
• Junction temperature: +150 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Resolution: 18 bits, no missing codes (18 bits guaranteed)
• INL: ±2.8 LSB typ (±6 LSB max); DNL: ±0.5 LSB typ (±0.9 LSB max)
• Offset error: ±2.8 LSB typ (±15 LSB max); gain error: ±3.1 LSB typ (±10 LSB max)
• SNR: 94.6 dB typ (93 dB min), VREF = 4.096 V, reference mode 3, 10 kHz input
• THD: -102 dB typ (-97 dB max); SFDR: 103.1 dB typ (97 dB min)
• Transition noise: 1.6 LSB RMS
• Input voltage range: ±K × VREF (K = 5.0/4.096), i.e. ±5 V with VREF = 4.096 V
• Internal reference: 4.096 V (±4 mV), ±7.5 ppm/°C typ on REF output (reference mode 0)
• Analog supply current: 3.6 mA typ (reference modes 2, 3); 6.0 mA typ (reference modes 0, 1)
• Power dissipation: 25.8 mW typ (reference modes 2, 3); 37.8 mW typ (reference modes 0, 1), VDD = 5 V, OVDD = 3.3 V
• Conversion time: 1.35–1.5 μs
• VDD shutdown current: 6.3 μA typ (10 μA max)

Features:

• 500ksps throughput without pipeline delay
• ±5V bipolar pseudodifferential analog input
• Internal reference and reference buffer, with external reference option
• SPI/QSPI/MICROWIRE/DSP-compatible serial interface with daisy-chain and busy indicator options
• Patented charge-pump architecture for direct sampling of high-impedance sources
• Input clamp protection current of ±20 mA
• Shutdown mode

Applications:

• Data acquisition systems
• Industrial control systems/process control
• Medical instrumentation
• Automatic test equipment

Package:

• 12-pin TDFN, 3mm x 3mm

• High DC/AC Accuracy Improves Measurementuality
• 18-Bit Resolution with No Missing Codes
• 500ksps Throughput Rate Without Pipeline Delay/ Latency
• 94.6dB SNR and -101.4dB THD at 10kHz
• 1.6 LSB RMS Transition Noise
• ±0.5 LSB DNL (typ) and ±2.8 LSB INL (typ)
• Highly Integrated ADC Saves Cost and Space
• 6ppm/°C (typ) Internal Reference
• Internal Reference Buffer
• ±5V Bipolar Analog Input Range
• Wide Supply Range and Low Power Simplify Power-Supply Design
• 5V Analog Supply
• 2.3V to 5V Digital Supply
• 25.8mW Power Consumption at 500ksps
• 10μA in Shutdown Mode
• Multi-Industry Standard Serial Interface and Small Package Reduce Size
• SPI/QSPI™/MICROWIRE ® /DSP-Compatible Serial Interface
• 3mm x 3mm Tiny 12-Pin TDFN Package

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corporation.

• Data Acquisition Systems
• Industrial Control Systems/Process Control
• Medical Instrumentation
• Automatic Test Equipment

Selector Guide and Ordering Information appear at end of data sheet.

(V DD = 4.75V to 5.25V, V OVDD = 2.3V to 5.25V, f SAMPLE = 500ksps, V REF = 4.096V, Reference Mode 3; T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25 N C.) (Note 2)

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
ANALOG INPUT (Note 3)	ANALOG INPUT (Note 3)	ANALOG INPUT (Note 3)	ANALOG INPUT (Note 3)	ANALOG INPUT (Note 3)	ANALOG INPUT (Note 3)	ANALOG INPUT (Note 3)
Input Voltage Range		AIN+ to AIN-, K = 5.0/4.096	-K x V REF		+K x V REF	V
Absolute Input Voltage Range		AIN+ to GND	-(V DD + 0.1)		+(V DD + 0.1)	V
Absolute Input Voltage Range		AIN- to GND	-0.1		+0.1	V
Input Leakage Current		Acquisition phase	-10	+0.001	+10	μA
Input Capacitance			16	16	16	pF
Input-Clamp Protection Current		Both inputs	-20		+20	mA
DC ACCURACY (Note 4)	DC ACCURACY (Note 4)	DC ACCURACY (Note 4)	DC ACCURACY (Note 4)	DC ACCURACY (Note 4)	DC ACCURACY (Note 4)	DC ACCURACY (Note 4)
Resolution	N		18			Bits
No Missing Codes			18			Bits
Offset Error			-15	±2.8	+15	LSB
Offset Temperature Coefficient			±0.002	±0.002	±0.002	LSB/°C
Gain Error			-10	±3.1	+10	LSB
Gain Error Temperature Coefficient				±0.023		LSB/°C
Integral Nonlinearity			-6	±2.8	+6	LSB
Differential Nonlinearity	DNL	Guaranteed by design	-0.9	±0.5	+0.9	LSB
Positive Full-Scale Error			-17		+17	LSB
Negative Full-Scale Error			-15		+15	LSB

(V DD = 4.75V to 5.25V, V OVDD = 2.3V to 5.25V, f SAMPLE = 500ksps, V REF = 4.096V, Reference Mode 3; T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25 N C.) (Note 2)

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
Analog Input CMRR	CMRR			-3.7		LSB/V
Power-Supply Rejection (Note 5)	PSR			-17.8		LSB/V
Transition Noise				1.6		LSB RMS
REFERENCE (Note 7)
REF Output Initial Accuracy	V REF	Reference mode 0	4.092	4.096	4.100	V
REF Output Temperature Coefficient	TC REF	Reference mode 0	-17	±7.5	+17	ppm/°C
REFIO Output Initial Accuracy	V REFIO	Reference modes 0 and 2	4.092	4.096	4.100	V
REFIO Output Temperature Coefficient	TCREFIO	Reference modes 0 and 2	-15	±6	+15	ppm/°C
REFIO Output Impedance		Reference modes 0 and 2		10		kΩ
REFIO Input Voltage Range		Reference mode 1	3	4.096	4.25	V
Reference Buffer Initial Offset		Reference mode 0	-500		+500	μV
Reference Buffer Temperature Coefficient		Reference mode 1	-10	±6	+10	μV/°C
External Compensation Capacitor	C EXT	Required for reference modes 0 and 1, recommended for reference modes 2 and 3	10			μF
REF Voltage Input Range	V REF	Reference modes 2 and 3	2.5		4.25	V
REF Input Capacitance		Reference modes 2 and 3		20		pF
REF Load Current		V REF = 4.096V, Reference modes 2 and 3		144		μA
AC ACCURACY (Note 6)
Signal-to-Noise Ratio (Note 7)	SNR	V REF = 4.096V, reference mode 3	93	94.6		dB
Signal-to-Noise Ratio (Note 7)	SNR	V REF = 4.096V, reference mode 1		94.0		dB
Signal-to-Noise Ratio (Note 7)	SNR	V REF = 2.5V, reference mode 3		90.2		dB
Signal-to-Noise Ratio (Note 7)	SNR	Internal reference, reference mode 0		94.3		dB
Signal-to-Noise Plus Distortion (Note 7)	SINAD	V REF = 4.096V, reference mode 3	91.9	93.9		dB
Signal-to-Noise Plus Distortion (Note 7)	SINAD	V REF = 4.096V, reference mode 1		93.2		dB
Signal-to-Noise Plus Distortion (Note 7)	SINAD	V REF = 2.5V, reference mode 3		89.7		dB
Signal-to-Noise Plus Distortion (Note 7)	SINAD	Internal reference, reference mode 0		93.3		dB

(V DD = 4.75V to 5.25V, V OVDD = 2.3V to 5.25V, f SAMPLE = 500ksps, V REF = 4.096V, Reference Mode 3; T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25 N C.) (Note 2)

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
Spurious-Free Dynamic Range	SFDR		97	103.1		dB
Total Harmonic Distortion	THD			-102	-97	dB
Intermodulation Distortion (Note 8)	IMD			-119.7		dBFS
SAMPLING DYNAMICS
Throughput Sample Rate			0.01		500	ksps
Transient Response		Full-scale step			400	ns
Full-Power Bandwidth		-3dB point		6		MHz
Full-Power Bandwidth		-0.1dB point		> 0.2
Aperture Delay				2.5		ns
Aperture Jitter				50		ps RMS
POWER SUPPLIES
Analog Supply Voltage	V DD		4.75		5.25	V
Interface Supply Voltage	V OVDD		2.3		5.25	V
Analog Supply Current	I VDD	Reference mode = 0, 1	5.0	6.0	7.5	mA
		Reference mode = 2, 3	3.0	3.6	4.0	mA
V DD Shutdown Current				6.3	10	μA
Interface Supply Current	I OVDD	V OVDD = 2.3V V OVDD = 5.25V		1.7 4.4	2.0 5.0	mA
OVDD Shutdown Current				0.9	10	μA
Power Dissipation		V DD = 5V, V OVDD = 3.3V, Reference mode = 2, 3		25.8		mW
Power Dissipation		V DD = 5V, V OVDD = 3.3V, Reference Mode = 0, 1		37.8		mW
DIGITAL INPUTS (DIN, SCLK, CNVST)	DIGITAL INPUTS (DIN, SCLK, CNVST)
Input Voltage High	V IH		0.7 x V OVDD			V
Input Voltage Low	V IL				0.3 x V OVDD	V
Input Hysteresis	V HYS			±0.05 x V OVDD		V
Input Capacitance	C IN			10		pF
Input Current	I IN	V IN = 0V or V OVDD	-10		+10	μA
DIGITAL OUTPUT (DOUT)	DIGITAL OUTPUT (DOUT)	DIGITAL OUTPUT (DOUT)	DIGITAL OUTPUT (DOUT)	DIGITAL OUTPUT (DOUT)	DIGITAL OUTPUT (DOUT)	DIGITAL OUTPUT (DOUT)
Output Voltage High	V OH	I SOURCE = 2mA	V OVDD - 0.4			V

(V DD = 4.75V to 5.25V, V OVDD = 2.3V to 5.25V, f SAMPLE = 500ksps, V REF = 4.096V, Reference Mode 3; T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25 N C.) (Note 2)

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
Output Voltage Low	V OL	I SINK = 2mA			0.4	V
Three-State Leakage Current			-10		+10	μA
Three-State Output Capacitance				15		pF
TIMING (Note 9)
Time Between Conversions	t CYC		2		100000	μs
Conversion Time	t CONV	CNVST rising to data available	1.35		1.5	μs
Acquisition Time	t ACQ	t ACQ = t CYC - t CONV	0.5			μs
CNVST Pulse Width	t CNVPW	CS mode	5			ns
SCLK Period ( CS Mode)	t SCLK	V OVDD > 4.5V	14			ns
	t SCLK	V OVDD > 2.7V	20			ns
	t SCLK	V OVDD > 2.3V	26			ns
SCLK Period (Daisy-Chain Mode)	t SCLK	V OVDD > 4.5V	16			ns
	t SCLK	V OVDD > 2.7V	24			ns
	t SCLK	V OVDD > 2.3V	30			ns
SCLK Low Time	t SCLKL		5			ns
SCLK High Time	t SCLKH		5			ns
SCLK Falling Edge to Data Valid Delay	t DDO	V OVDD > 4.5V			12	ns
	t DDO	V OVDD > 2.7V			18	ns
	t DDO	V OVDD > 2.3V			23	ns
CNVST Low to DOUT D15 MSB Valid ( CS Mode)	t EN	V OVDD > 2.7V			14	ns
CNVST Low to DOUT D15 MSB Valid ( CS Mode)	t EN	V OVDD < 2.7V			17	ns
CNVST High or Last SCLK Falling Edge to DOUT High Impedance	t DIS	CS Mode			20	ns
DIN Valid Setup Time from SCLK Falling Edge	t SDINSCK	V OVDD > 4.5V	3			ns
DIN Valid Setup Time from SCLK Falling Edge	t SDINSCK	V OVDD > 2.7V	5			ns
DIN Valid Setup Time from SCLK Falling Edge	t SDINSCK	V OVDD > 2.3V	6			ns
DIN Valid Hold Time from SCLK Falling Edge	t HDINSCK		0			ns
SCLK Valid Setup Time to CNVST Falling Edge	t SSCKCNF		3			ns
SCLK Valid Hold Time to CNVST Falling Edge	t HSCKCNF		6			ns

(V DD = 4.75V to 5.25V, V OVDD = 2.3V to 5.25V, f SAMPLE = 500Ksps, V REF = 4.096V, Reference Mode 3; T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25 N C.) (Note 2)

Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C. Limits over the operating range are guaranteed by design and device characterization

Note 3: See the Analog Inputs and Overvoltage Input Clamps sections.

Note 4: Static performance limits are guaranteed by design and device characterization. For definitions, see the Definitions section.

Note 5: Defined as the change in positive full-scale code transition caused by a Q 5% variation in the V DD supply voltage.

Note 6: 10kHz sine wave input, -0.1dB below full scale.

Note 7: See Table 4 for definition of the reference modes.

Note 8: f IN1 = 9.4kHz, f IN2 = 10.7kHz, Each tone at -6.1dB below full scale.

Note 9: CLOAD = 65pF on DOUT.

Parameter	Limit
V DD to GND	-0.3V to +6V
OVDD to GND	-0.3V to the lower of (V DD + 0.3V) and +6V
AIN+ to GND	Q 7V
AIN-, REF, REFIO, AGNDS
to GND	-0.3V to the lower of (V DD + 0.3V) and +6V
SCLK, DIN, DOUT, CNVST
to GND	-0.3V to the lower of (V DD + 0.3V) and +6V
Maximum Current into Any Pin	50mA

Parameter	Limit
Continuous Power Dissipation (T A = +70 N C) TDFN (derate 18.2mW/ N C above +70 N C)	1349mW
Operating Temperature Range	-40 N C to +85 N C
Junction Temperature	+150 N C
Storage Temperature Range	-65 N C to +150 N C
Lead Temperature (soldering, 10s)	+300 N C
Soldering Temperature (reflow)	+260 N C

Stresses beyond those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . Note that a '+', '#', or '-' in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE	PACKAGE CODE	OUTLINE NO.	LAND PATTERN NO.
12 TDFN-EP	TD1233+1	21-0664	90-0397