LTM4678I

Part: LTM4678 — Analog Devices (formerly Linear Technology)

Type: Dual 25A or Single 50A Step-Down μModule (Power Module) DC/DC Regulator

Description: The LTM4678 is a dual 25A or single 50A step-down μModule DC/DC regulator with a wide input voltage range of 4.5V to 16V, an output voltage range of 0.5V to 3.4V, and a PMBus-compliant I2C serial interface for remote configurability and telemetry monitoring.

Operating Conditions:

• Supply voltage: 4.5V to 16V
• Operating temperature: -40°C to 125°C
• Output voltage range: 0.5V to 3.4V
• Switching frequency: 350kHz (typical, factory default)

Absolute Maximum Ratings:

• Max supply voltage: 16V (V IN n, SV IN, I IN+, I IN-)
• Max continuous current: 25A (per channel)
• Max internal operating temperature: 125°C
• Storage temperature range: -55°C to 150°C

Key Specs:

• Input DC Voltage (V IN n, SV IN): 4.5V (min) to 16V (max)
• Output Voltage Range (V OUT n): 0.5V (min) to 3.4V (max)
• Output Continuous Current Range (I OUT n): 0A to 25A
• Output Voltage, Total Variation with Line and Load (V OUT n (DC)): ±0.5% (max, Digital Servo Engaged)
• Line Regulation Accuracy (∆V OUT n (LINE) / V OUT n): ±0.2 %/V (max, Digital Servo Engaged)
• Load Regulation Accuracy (∆V OUT n (LOAD) / V OUT n): 0.5% (max, Digital Servo Disengaged)
• Output Voltage Ripple (V OUT n (AC)): 10 mV P-P (typical)
• Input Supply Bias Current (I Q(SVIN)): 25 mA (typical, Forced Continuous Mode)

Features:

• Dual Digitally Adjustable Analog Loops with Digital Interface for Control and Monitoring
• PMBus-Compliant I2C Serial Interface (400kHz)
• Integrated 16-Bit ∆Σ ADC
• Sub-Milliohm DCR Current Sensing
• Integrated Input Current Sense Amplifier
• Parallel and Current Share Up to 250A
• Onboard EEPROM Fault Log Record
• Supports Telemetry Polling Rates up to 125Hz

Applications:

• System Optimization, Characterization and Data Mining in Prototype, Production and Field Environments

Package:

• 16mm × 16mm × 5.86mm CoP-BGA Package

• n Dual Digitally Adjustable Analog Loops with Digital Interface for Control and Monitoring
• n Wide Input Voltage Range: 4.5V to 16V
• n Output Voltage Range: 0.5V to 3.4V
• n ±0.5% Maximum DC Output Error Over Temperature
• n ±3.5% Current Readback Accuracy, -20°C to 125°C
• n Sub-Milliohm DCR Current Sensing
• n Integrated Input Current Sense Amplifier
• n 400kHz PMBus-Compliant I 2 C Serial Interface
• n Supports Telemetry Polling Rates up to 125Hz
• n Integrated 16-Bit ∆ Σ ADC
• n Constant Frequency Current Mode Control
• n Parallel and Current Share Up to 250A
• n 16mm × 16mm × 5.86mm CoP-BGA Package

• n System Optimization, Characterization and Data Mining in Prototype, Production and Field Environments

The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). n is specified as each individual output channel (Note 4). T A = 25°C, V IN = 12V, RUN n = 3.3V, EXTV CC = 0, FREQUENCY_SWITCH = 350kHz and V OUT n commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

Rev. A

The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). n is specified as each individual output channel (Note 4). T A = 25°C, V IN = 12V, RUN n = 3.3V, EXTV CC = 0, FREQUENCY_SWITCH = 350kHz and V OUT n commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). n is specified as each individual output channel (Note 4). T A = 25°C, V IN = 12V, RUN n = 3.3V, EXTV CC = 0, FREQUENCY_SWITCH = 350kHz and V OUT n commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). n is specified as each individual output channel (Note 4). T A = 25°C, V IN = 12V, RUN n = 3.3V, EXTV CC = 0, FREQUENCY_SWITCH = 350kHz and V OUT n commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

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The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). n is specified as each individual output channel (Note 4). T A = 25°C, V IN = 12V, RUN n = 3.3V, EXTV CC = 0, FREQUENCY_SWITCH = 575kHz and V OUT n commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LTM4678 is tested under pulsed-load conditions such that T J ≈ T A . The LTM4678E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the -40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4678I is guaranteed to meet specifications over the full -40°C to 125°C internal operating temperature range. T J is calculated from

the ambient temperature T A and the power dissipation PD according the formula:

Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.

Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified

Note 4: The two power inputs-V IN0 and V IN1 -and their respective power outputs-V OUT0 and V OUT1 -are tested independently in production. A shorthand notation is used in this document that allows these parameters to be referred to by 'V IN n ' and 'V OUT n ', where n is permitted to take on a value of 0 or 1. This italicized, subscripted ' n ' notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_COMMAND n refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to channel 0 (V OUT0 ) and channel 1 (V OUT1 ). Registers containing non-page-specific data, i.e., whose data is 'global' to the module or applies to both of the module's channels lack the italicized, subscripted ' n ', e.g., FREQUENCY_SWITCH.

Note 5: V OUT n (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODE n [6] = 0b) and low V OUT n range selected MFR_PWM_MODE n [1] = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODE n [6] = 1b), but convergence of the output voltage to its final settling value is not necessarily observed in final test-due to potentially long time constants involved-and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section.

Note 6: See output current derating curves for different V IN , V OUT , and T A , located in the Applications Information section.

Note 7: Even though V OUT0 and V OUT1 are specified for 6V absolute maximum, the maximum recommended command voltage to regulate output channels 0 and 1 is 3.6V with V OUT range-setting bit set using MFR_PWM_MODE[1] = 0b.

Note 8: Minimum on-time is tested at wafer sort.

Note 9: The data conversion is done by default in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4678 can do fast data conversion with only 8ms to 10ms. See section PMBus Command for details.

Note 10: The following telemetry parameters are formatted in PMBusdefined 'Linear Data Format', in which each register contains a word comprised of 5 most significant bits-representing a signed exponent, to be raised to the power of 2-and 11 least significant bits-representing a signed mantissa: input voltage (on SV IN ), accessed via the READ_VIN command code; output currents (I OUT n ), accessed via the READ_IOUT n command codes; module input current (I VIN0 + I VIN1 + I SVIN ), accessed via the READ_IIN command code; channel input currents (I VIN n + 1/2 · I SVIN ), accessed via the MFR_READ_IIN n command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the READ_DUTY_CYCLE n command codes. This data format limits the resolution of telemetry readback data to 10 bits even though the internal ADC is 16 bits and the LTM4678's internal calculations use 32-bit words.

Note 11: The absolute maximum rating for the SV IN pin is 18V. Input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the SV IN pin.

Note 12: These typical parameters are based on bench measurements and are not production tested. Improved output current readback can be achieved by evaluating the system using the LTM4678. Measurements of the ambient temperature and the module inductor temperature for each channel with airflow can be compared with the GUI readback temperature. Once this temperature difference is known, then MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET parameters can be adjusted to further improve output current readback accuracy.

Note 13: EEPROM endurance and retention are guaranteed by wafer-level testing for data retention. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification, and whose EEPROM data was written to at 0°C ≤ T J ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over the entire operating temperature range and does not influence EEPROM characteristics.

Note 14: Channel 0 OV/UV comparator threshold accuracy for MFR_PWM_MODE n [1] = 1b tested in ATE at V VOSNS0 + - V VOSNS0 -= 0.5V and 3.6V. 1V condition tested at IC-Level, only. Channel 1 OV/UV comparator threshold accuracy for MFR_PWM_MODE n [1] = 1b tested in ATE with V VOSNS1 + - V VOSNS1 -= 0.5V and 3.6V. 1.5V condition tested at IC-level, only. MFR_PWM_MODE n [1] = 1b is the Low Range.

Note 15: Tested at IC-level ATE.

Note 16: The LTM4678 quiescent current (I Q ) equals the I Q of V IN plus the I Q of INTV CC .

Note 17: The LTM4678's EEPROM temperature range for valid write commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention, execution of the 'STORE_USER_ALL' command-i.e., uploading RAM contents to NVM-outside this temperature range is not recommended. However, as long as the LTM4678's EEPROM temperature is less than 130°C, the LTM4678 will obey the STORE_USER_ALL command. Only when EEPROM temperature exceeds 130°C, the LTM4678 will not act on any STORE_USER_ALL transactions: instead, the LTM4678 NACKs the serial command and asserts its relevant CML (communications, memory, logic) fault bits. EEPROM temperature can be queried prior to commanding STORE_USER_ALL; see the Applications Information section.

Note 18: The LTM4678 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

Note 19: The maximum programmable output voltage is 3.6V, therefore, any of the overvoltage margining commands will be limited as the output voltage is programmed up to 3.6V.

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4678 F01

Figure 1. Programmable R COMP

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The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a μModule package mounted to a hardware test board defined by JESD51-9 ('Test Boards for Area Array Surface Mount Package Thermal Measurements'). The motivation for providing these thermal coefficients is found in JESD51-12 ('Guidelines for Reporting and Using Electronic Package Thermal Information').

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the μModule regulator's thermal performance in their appli-

cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one's application-usage, and can be adapted to correlate thermal performance to one's own application.

The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:

1. θ JA , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as 'still air' although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition.
2. θ JCbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical μModule regulator , the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing pack-
3. ages but the test conditions don't generally match the user's application.
4. θ JCtop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom , this value may be useful for comparing packages but the test conditions don't generally match the user's application.
5. 4 θ JB , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9.

A graphical representation of the aforementioned thermal resistances is given in Figure 34; blue resistances are contained within the μModule regulator , whereas green resistances are external to the μModule package.

As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the

Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients

Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients

Pin Configuration section replicates or conveys normal operating conditions of a μModule regulator . For example, in normal board-mounted applications, never does 100% of the device's total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the μModule package-as the standard defines for θ JCtop and θ JCbottom , respectively. In practice, power loss is thermally dissipated in both directions away from the package-granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.

Within the LTM4678, be aware there are multiple power devices and components dissipating power , with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity-but also, not ignoring practical realities-an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4678 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4678 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with

well-correlated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet.

The 5V, 8V and 12V power loss curves in Figure 35, Figure 36 and Figure 37 respectively can be used in coordination with the load current derating curves in Figure 38 to Figure 43 for calculating an approximate θ JA thermal resistance for the LTM4678 with airflow conditions. These thermal resistances represent demonstrated performance of the LTM4678 on hardware; a 6-layer FR4 PCB measuring 99mm × 130mm × 1.6mm using 2oz copper on all layers. The power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with the LTM4678's paralleled outputs initially sourcing up to 50A and the ambient temperature at 25°C. The output voltages are 0.9V and 1.8V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow.

The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 125°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 40, the load current is derated to ~35A at ~73°C ambient with no air or heat sink and the room temperature (25°C) power loss for this 12V IN to 0.9V OUT at 35A OUT condition is ~4W. A 5.4W loss is calculated by multiplying the ~4W room temperature loss from the 12V IN to 0.9V OUT power loss curve at 35A (Figure 35), with the 1.35 multiplying factor . If the 73°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of

52°C divided by 5.4W yields a thermal resistance, θ JA , of 9.6°C/W-in good agreement with Table 10. Table 10 and Table 11 provide equivalent thermal resistances for 0.9V and 1.8V outputs with and without airflow. The derived thermal resistances in Table 10 and Table 11 for the various conditions can be multiplied by the calculated power loss

Dual 25A μModule Regulator with Digital Interface for Control and Monitoring*

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