Part: LTM4678 — Analog Devices (formerly Linear Technology)

Type: Dual 25A or Single 50A Step-Down μModule (Power Module) DC/DC Regulator

Description: The LTM4678 is a dual 25A or single 50A step-down μModule DC/DC regulator with a wide input voltage range of 4.5V to 16V, an output voltage range of 0.5V to 3.4V, and a PMBus-compliant I2C serial interface for remote configurability and telemetry monitoring.

Operating Conditions:

• Supply voltage: 4.5V to 16V
• Operating temperature: -40°C to 125°C
• Output voltage range: 0.5V to 3.4V
• Switching frequency: 350kHz (typical, factory default)

Absolute Maximum Ratings:

• Max supply voltage: 16V (V IN n, SV IN, I IN+, I IN-)
• Max continuous current: 25A (per channel)
• Max internal operating temperature: 125°C
• Storage temperature range: -55°C to 150°C

Key Specs:

• Input DC Voltage (V IN n, SV IN): 4.5V (min) to 16V (max)
• Output Voltage Range (V OUT n): 0.5V (min) to 3.4V (max)
• Output Continuous Current Range (I OUT n): 0A to 25A
• Output Voltage, Total Variation with Line and Load (V OUT n (DC)): ±0.5% (max, Digital Servo Engaged)
• Line Regulation Accuracy (∆V OUT n (LINE) / V OUT n): ±0.2 %/V (max, Digital Servo Engaged)
• Load Regulation Accuracy (∆V OUT n (LOAD) / V OUT n): 0.5% (max, Digital Servo Disengaged)
• Output Voltage Ripple (V OUT n (AC)): 10 mV P-P (typical)
• Input Supply Bias Current (I Q(SVIN)): 25 mA (typical, Forced Continuous Mode)

Features:

• Dual Digitally Adjustable Analog Loops with Digital Interface for Control and Monitoring
• PMBus-Compliant I2C Serial Interface (400kHz)
• Integrated 16-Bit ∆Σ ADC
• Sub-Milliohm DCR Current Sensing
• Integrated Input Current Sense Amplifier
• Parallel and Current Share Up to 250A
• Onboard EEPROM Fault Log Record
• Supports Telemetry Polling Rates up to 125Hz

Applications:

• System Optimization, Characterization and Data Mining in Prototype, Production and Field Environments

Package:

• 16mm × 16mm × 5.86mm CoP-BGA Package

• n Dual Digitally Adjustable Analog Loops with Digital Interface for Control and Monitoring
• n Wide Input Voltage Range: 4.5V to 16V
• n Output Voltage Range: 0.5V to 3.4V
• n ±0.5% Maximum DC Output Error Over Temperature
• n ±3.5% Current Readback Accuracy, -20°C to 125°C
• n Sub-Milliohm DCR Current Sensing
• n Integrated Input Current Sense Amplifier
• n 400kHz PMBus-Compliant I 2 C Serial Interface
• n Supports Telemetry Polling Rates up to 125Hz
• n Integrated 16-Bit ∆ Σ ADC
• n Constant Frequency Current Mode Control
• n Parallel and Current Share Up to 250A
• n 16mm × 16mm × 5.86mm CoP-BGA Package

• n System Optimization, Characterization and Data Mining in Prototype, Production and Field Environments

LTM4678 Pinout — BGA-144 (16mm × 16mm)

Notes

• BGA-144 package: 16mm × 16mm, 0.5mm pitch
• Thermal specifications: TJMAX = 125°C; θJA = 2.5°C/W; θJC = 2°C/W; θJB = 7°C/W
• Multiple GND pins: Extensive ground distribution throughout the package for low impedance
• Open-Drain outputs: SDA, SCL, FAULT0, FAULT1, PGOOD0, PGOOD1, RUN0, RUN1, ALERT, SHARE_CLK require external pull-up resistors
• Dual-channel design: Channels 0 and 1 are independently controlled with separate VIN, VOUT, feedback, and control pins
• Pin diagram is authoritative: All pin numbers extracted directly from the BGA top-view diagram provided

The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a μModule package mounted to a hardware test board defined by JESD51-9 ('Test Boards for Area Array Surface Mount Package Thermal Measurements'). The motivation for providing these thermal coefficients is found in JESD51-12 ('Guidelines for Reporting and Using Electronic Package Thermal Information').

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the μModule regulator's thermal performance in their appli-

cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one's application-usage, and can be adapted to correlate thermal performance to one's own application.

The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:

1. θ JA , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as 'still air' although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition.
2. θ JCbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical μModule regulator , the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing pack-
3. ages but the test conditions don't generally match the user's application.
4. θ JCtop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom , this value may be useful for comparing packages but the test conditions don't generally match the user's application.
5. 4 θ JB , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9.

A graphical representation of the aforementioned thermal resistances is given in Figure 34; blue resistances are contained within the μModule regulator , whereas green resistances are external to the μModule package.

As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the

Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients

Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients

Pin Configuration section replicates or conveys normal operating conditions of a μModule regulator . For example, in normal board-mounted applications, never does 100% of the device's total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the μModule package-as the standard defines for θ JCtop and θ JCbottom , respectively. In practice, power loss is thermally dissipated in both directions away from the package-granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.

Within the LTM4678, be aware there are multiple power devices and components dissipating power , with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity-but also, not ignoring practical realities-an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4678 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4678 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with

well-correlated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet.

The 5V, 8V and 12V power loss curves in Figure 35, Figure 36 and Figure 37 respectively can be used in coordination with the load current derating curves in Figure 38 to Figure 43 for calculating an approximate θ JA thermal resistance for the LTM4678 with airflow conditions. These thermal resistances represent demonstrated performance of the LTM4678 on hardware; a 6-layer FR4 PCB measuring 99mm × 130mm × 1.6mm using 2oz copper on all layers. The power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with the LTM4678's paralleled outputs initially sourcing up to 50A and the ambient temperature at 25°C. The output voltages are 0.9V and 1.8V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow.

The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 125°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 40, the load current is derated to ~35A at ~73°C ambient with no air or heat sink and the room temperature (25°C) power loss for this 12V IN to 0.9V OUT at 35A OUT condition is ~4W. A 5.4W loss is calculated by multiplying the ~4W room temperature loss from the 12V IN to 0.9V OUT power loss curve at 35A (Figure 35), with the 1.35 multiplying factor . If the 73°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of

52°C divided by 5.4W yields a thermal resistance, θ JA , of 9.6°C/W-in good agreement with Table 10. Table 10 and Table 11 provide equivalent thermal resistances for 0.9V and 1.8V outputs with and without airflow. The derived thermal resistances in Table 10 and Table 11 for the various conditions can be multiplied by the calculated power loss

Dual 25A μModule Regulator with Digital Interface for Control and Monitoring*

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