Part: LPC55S6x — NXP

Type: ARM Cortex-M33 Microcontroller

Description: Dual-core ARM Cortex-M33 microcontroller running at up to 150 MHz, featuring TrustZone, PowerQuad DSP accelerator, CASPER crypto engine, up to 640 KB flash, 320 KB SRAM, USB HS/FS, and extensive serial and analog peripherals.

Operating Conditions:

• Supply voltage: 1.8 V to 3.6 V
• Operating temperature: -40 °C to +105 °C
• Max CPU frequency: 150 MHz

Key Specs:

• CPU Core: Dual ARM Cortex-M33 (one with FPU/MPU/TrustZone, one without)
• Max CPU Frequency: 150 MHz
• Flash Memory: Up to 640 KB
• SRAM: Up to 320 KB
• ADC: 16-bit, 1.0 MSamples/sec, 5 differential/10 single-ended channels
• GPIO: Up to 64 pins
• Serial Interfaces: Up to 9 Flexcomm (USART, SPI, I2C, I2S)
• USB: USB 2.0 Full-Speed and High-Speed host/device
• Security: TrustZone, AES-256, SHA2, PUF, TRNG, Secure Boot

Features:

• ARM Cortex-M33 core (CPU0) with TrustZone, FPU, MPU, DSP, ETM
• ARM Cortex-M33 co-processor (CPU1)
• CASPER Crypto co-processor for asymmetric cryptographic algorithms
• PowerQuad hardware accelerator for CMSIS DSP functions
• PRINCE module for on-the-fly flash encryption/decryption
• On-chip ROM bootloader with ISP support (USB, UART, SPI, I2C)
• Secure Boot support with RSA-2048/4096 signature verification
• Up to nine Flexcomm Interfaces configurable as USART, SPI, I2C, or I2S
• I2C-bus interfaces support Fast-mode, Fast-mode Plus (1 Mbit/s), and High-speed Mode (3.4 Mbit/s) as slave
• USB 2.0 full-speed host/device controller with on-chip PHY and crystal-less operation
• USB 2.0 high-speed host/device controller with on-chip high-speed PHY
• Two DMA controllers (23 channels and 10 channels)
• Secured digital input/output (SD/MMC and SDIO) card interface
• CRC engine block
• Programmable Logic Unit (PLU)
• AES-256 encryption/decryption engine
• Secure Hash Algorithm (SHA2) module
• Physical Unclonable Function (PUF)
• True Random Number Generator (TRNG)
• 128-bit unique device serial number (UUID)
• Five 32-bit general purpose timers/counters
• One SCTimer/PWM
• 32-bit Real-time clock (RTC)
• Multiple-channel multi-rate 24-bit timer (MRT)
• Windowed Watchdog Timer (WWDT)
• Integrated temperature sensor
• Comparator with five input pins
• Internal Free Running Oscillators (FRO) at 96 MHz, 12 MHz, 32 kHz, 1 MHz
• Crystal oscillators for 12-32 MHz and 32.768 KHz
• PLL0 and PLL1
• Power Management Unit (PMU) with Sleep, Deep-sleep, Power-down, Deep power-down modes
• Power-On Reset (POR) and Brown-Out Detectors (BOD)
• JTAG boundary scan supported

Package:

• HLQFP100 (100 leads, 14 x 14 x 0.5mm pitch)
• VFBGA98 (98 balls, 7 x 7 x 0.5 mm)
• HTQFP64 (64 leads, 10 x 10 x 0.5mm pitch)

• ARM Cortex-M33 core (CPU0, r0p3):
• Running at a frequency of up to 150 MHz (device revision 1B only).
• TrustZone®, Floating Point Unit (FPU) and Memory Protection Unit (MPU).
• ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
• Non-maskable Interrupt (NMI) input with a selection of sources.
• Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities.
• System tick timer.
• The configuration of this instance includes MPU, FPU, DSP, ETM, and Trustzone.
• ARM Cortex-M33 co-processor (CPU1, r0p3):
• Running at a CPU frequency of up to 150 MHz (device revision 1B only).
• The configuration of this instance does not include MPU, FPU, DSP, ETM, and Trustzone.
• System tick timer.

• CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC).
• PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP functions with support of SDK software API faster execution of ARM CMSIS instruction set.
• On-chip memory:
• Up to 640 KB on-chip flash program memory with flash accelerator and 512 byte page erase and write.
• Up to 320 KB total SRAM consisting of 32 KB SRAM on Code Bus, 272 KB SRAM on System Bus (272 KB is contiguous), and additional 16 KB USB SRAM on System Bus which can be used by the USB interface or for general purpose use.
• PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection, such as securing application code, and enabling secure flash update.
• On-chip ROM bootloader supports:
• Booting of images from on-chip flash
• Supports CRC32 image integrity checking.
• Supports flash programming through In System Programming (ISP) commands over following interfaces: USB0/1 interfaces using HID Class device, UART interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9) using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)
• ROM API functions: Flash programming API, Power control API, and Secure firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).
• Supports booting of images from PRINCE encrypted flash regions.
• Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096).
• Supports setting a sealed part to Fault Analysis mode through Debug authentication.
• Secure Boot support:
• Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification.
• Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).
• Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).
• Uses x509 certificate format to validate image public keys.
• Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust establishment by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR).
• Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates revocations using Serial Number field in x509 certificate.
• Serial interfaces:
• Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7 and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which is dedicated for high-speed SPI) can be selected by software to be a USART, SPI, I 2 C, and I 2 S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I 2 S. A variety of clocking options are available to each Flexcomm Interface, including a shared fractional baud-rate generator, and time-out feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I 2 S.

• I 2 C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I 2 C pads also support high-speed Mode (3.4 Mbit/s) as a slave.
• USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library example in technical note (TN00063).
• USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
• Digital peripherals:
• DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals.
• DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and DMA-capable peripherals.
• Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. SDIO with support for up to two cards. Supported card types are MMC, SDIO, and CE-ATA. Supports SD2.0, and SDR25 (52MHz).
• CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support.
• Up to 64 General-Purpose Input/Output (GPIO) pins.
• GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports.
• Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges.
• Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states.
• I/O pin configuration with support for up to 16 function options.
• Programmable Logic Unit (PLU) to create small combinatorial and/or sequential logic networks including state machines.
• Security Features:
• ARM TrustZone® enabled.
• AES-256 encryption/decryption engine with keys fed directly from PUF or a software supplied key
• Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA controller.
• Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes hardware for key extraction.
• True Random Number Generator (TRNG).
• 128 bit unique device serial number for identification (UUID).
• Secure GPIO.
• Timers:
• Five 32-bit standard general purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests.
• One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and match registers). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 captures/matches, 16 events, and 32 states.

• 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. Another timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. The RTC is clocked by the 32 kHz FRO or 32.768 kHz external crystal.
• Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.
• Windowed Watchdog Timer (WWDT) with FRO 1 MHz as clock source.
• The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up the device from sleep and deep-sleep modes. Includes 4 capture registers with pin inputs.
• 42-bit free running OS Timer as continuous time-base for the system, available in any reduced power modes. It runs on 32kHz clock source, allowing a count period of more than 4 years.
• Analog peripherals:
• 16-bit ADC with five differential channel pair (or 10 single-ended channels), and with multiple internal and external trigger inputs and sample rates of up to 1.0 MSamples/sec. The ADC supports simultaneous conversions, on two ADC input channels belonging to a differential pair.
• Integrated temperature sensor connected to the ADC.
• Comparator with five input pins and external or internal reference voltage.

LPC55S69JBD100 – HLQFP100 Pinout

Notes:

• Pin numbers extracted from HLQFP100 package diagram.
• AI = Analog Input (when DIGIMODE=0 and ANAMODE=1 in IOCON register).
• PD = Pull-down enabled at reset; PU = Pull-up enabled at reset; Z = High-impedance at reset.
• SWCLK (PIO0_11, function 6) and SWDIO (PIO0_12, function 6) are Serial Wire Debug pins with default function after boot.
• PIO0_5 state at reset determines boot source (ISP vs. normal boot).
• Pins PIO0_13 and PIO0_14 are true open-drain pins.
• Table continues beyond PIO0_22 in source material; extraction limited to pins shown in provided datasheet section.

Table 38. 16-bit ADC static characteristics

Tamb = 40 C to +105 C; VDDA = 1.8 V to 3.6 V; ADC calibrated at T = 25 C.

• [3] fclk(ADC) = 24 MHz, STS = 3, Power select = 1, Average setting = 1, fs = 1 Msample/s

[4] Differential linear results assume offset 0.2% from VREFL and 0.2% from VREFH

• [5] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

[6] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors.

[7] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve.

• [8] The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve.
• [9] Input data is 1kHz sine wave, ADC conversion clock 24 MHz, Power Select = 3, Average setting = 4.
• [10] Value of ADC_CFG[PUDLY] * 4 * ADCclk must be > tADCSTUP.
• [11] To use temperature sensor, the maximum fclk(ADC) frequency is 6 MHz.

The average chip junction temperature, Tj ( C), can be calculated using the following equation:

• Tamb = ambient temperature ( C),
• Rth(j-a) = the package junction-to-ambient thermal resistance ( C/W)
• PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.

Table 12. Thermal resistance

Table 13. Maximum Junction Temperature

Table 42. USB1 High-speed VBUS threshold levels

Fig 28. HTQFP64 Package outline 2

No ordering information table or variants were found in the provided datasheet section.