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LPC55S69

Microcontroller

The LPC55S69 is a microcontroller from NXP Semiconductors. View the full LPC55S69 datasheet below including electrical characteristics.

Manufacturer

NXP Semiconductors

Category

Microcontroller

Overview

Part: LPC55S6x — NXP

Type: ARM Cortex-M33 Microcontroller

Description: Dual-core ARM Cortex-M33 microcontroller running at up to 150 MHz, featuring TrustZone, PowerQuad DSP accelerator, CASPER crypto engine, up to 640 KB flash, 320 KB SRAM, USB HS/FS, and extensive serial and analog peripherals.

Operating Conditions:

  • Supply voltage: 1.8 V to 3.6 V
  • Operating temperature: -40 °C to +105 °C
  • Max CPU frequency: 150 MHz

Key Specs:

  • CPU Core: Dual ARM Cortex-M33 (one with FPU/MPU/TrustZone, one without)
  • Max CPU Frequency: 150 MHz
  • Flash Memory: Up to 640 KB
  • SRAM: Up to 320 KB
  • ADC: 16-bit, 1.0 MSamples/sec, 5 differential/10 single-ended channels
  • GPIO: Up to 64 pins
  • Serial Interfaces: Up to 9 Flexcomm (USART, SPI, I2C, I2S)
  • USB: USB 2.0 Full-Speed and High-Speed host/device
  • Security: TrustZone, AES-256, SHA2, PUF, TRNG, Secure Boot

Features:

  • ARM Cortex-M33 core (CPU0) with TrustZone, FPU, MPU, DSP, ETM
  • ARM Cortex-M33 co-processor (CPU1)
  • CASPER Crypto co-processor for asymmetric cryptographic algorithms
  • PowerQuad hardware accelerator for CMSIS DSP functions
  • PRINCE module for on-the-fly flash encryption/decryption
  • On-chip ROM bootloader with ISP support (USB, UART, SPI, I2C)
  • Secure Boot support with RSA-2048/4096 signature verification
  • Up to nine Flexcomm Interfaces configurable as USART, SPI, I2C, or I2S
  • I2C-bus interfaces support Fast-mode, Fast-mode Plus (1 Mbit/s), and High-speed Mode (3.4 Mbit/s) as slave
  • USB 2.0 full-speed host/device controller with on-chip PHY and crystal-less operation
  • USB 2.0 high-speed host/device controller with on-chip high-speed PHY
  • Two DMA controllers (23 channels and 10 channels)
  • Secured digital input/output (SD/MMC and SDIO) card interface
  • CRC engine block
  • Programmable Logic Unit (PLU)
  • AES-256 encryption/decryption engine
  • Secure Hash Algorithm (SHA2) module
  • Physical Unclonable Function (PUF)
  • True Random Number Generator (TRNG)
  • 128-bit unique device serial number (UUID)
  • Five 32-bit general purpose timers/counters
  • One SCTimer/PWM
  • 32-bit Real-time clock (RTC)
  • Multiple-channel multi-rate 24-bit timer (MRT)
  • Windowed Watchdog Timer (WWDT)
  • Integrated temperature sensor
  • Comparator with five input pins
  • Internal Free Running Oscillators (FRO) at 96 MHz, 12 MHz, 32 kHz, 1 MHz
  • Crystal oscillators for 12-32 MHz and 32.768 KHz
  • PLL0 and PLL1
  • Power Management Unit (PMU) with Sleep, Deep-sleep, Power-down, Deep power-down modes
  • Power-On Reset (POR) and Brown-Out Detectors (BOD)
  • JTAG boundary scan supported

Package:

  • HLQFP100 (100 leads, 14 x 14 x 0.5mm pitch)
  • VFBGA98 (98 balls, 7 x 7 x 0.5 mm)
  • HTQFP64 (64 leads, 10 x 10 x 0.5mm pitch)

Features

  • ARM Cortex-M33 core (CPU0, r0p3):
  • Running at a frequency of up to 150 MHz (device revision 1B only).
  • TrustZone®, Floating Point Unit (FPU) and Memory Protection Unit (MPU).
  • ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
  • Non-maskable Interrupt (NMI) input with a selection of sources.
  • Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities.
  • System tick timer.
  • The configuration of this instance includes MPU, FPU, DSP, ETM, and Trustzone.
  • ARM Cortex-M33 co-processor (CPU1, r0p3):
  • Running at a CPU frequency of up to 150 MHz (device revision 1B only).
  • The configuration of this instance does not include MPU, FPU, DSP, ETM, and Trustzone.
  • System tick timer.

  • CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC).
  • PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP functions with support of SDK software API faster execution of ARM CMSIS instruction set.
  • On-chip memory:
  • Up to 640 KB on-chip flash program memory with flash accelerator and 512 byte page erase and write.
  • Up to 320 KB total SRAM consisting of 32 KB SRAM on Code Bus, 272 KB SRAM on System Bus (272 KB is contiguous), and additional 16 KB USB SRAM on System Bus which can be used by the USB interface or for general purpose use.
  • PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection, such as securing application code, and enabling secure flash update.
  • On-chip ROM bootloader supports:
  • Booting of images from on-chip flash
  • Supports CRC32 image integrity checking.
  • Supports flash programming through In System Programming (ISP) commands over following interfaces: USB0/1 interfaces using HID Class device, UART interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9) using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)
  • ROM API functions: Flash programming API, Power control API, and Secure firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).
  • Supports booting of images from PRINCE encrypted flash regions.
  • Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096).
  • Supports setting a sealed part to Fault Analysis mode through Debug authentication.
  • Secure Boot support:
  • Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification.
  • Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).
  • Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).
  • Uses x509 certificate format to validate image public keys.
  • Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust establishment by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR).
  • Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates revocations using Serial Number field in x509 certificate.
  • Serial interfaces:
  • Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7 and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which is dedicated for high-speed SPI) can be selected by software to be a USART, SPI, I 2 C, and I 2 S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I 2 S. A variety of clocking options are available to each Flexcomm Interface, including a shared fractional baud-rate generator, and time-out feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I 2 S.

  • I 2 C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I 2 C pads also support high-speed Mode (3.4 Mbit/s) as a slave.
  • USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library example in technical note (TN00063).
  • USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
  • Digital peripherals:
  • DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals.
  • DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and DMA-capable peripherals.
  • Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. SDIO with support for up to two cards. Supported card types are MMC, SDIO, and CE-ATA. Supports SD2.0, and SDR25 (52MHz).
  • CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support.
  • Up to 64 General-Purpose Input/Output (GPIO) pins.
  • GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports.
  • Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges.
  • Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states.
  • I/O pin configuration with support for up to 16 function options.
  • Programmable Logic Unit (PLU) to create small combinatorial and/or sequential logic networks including state machines.
  • Security Features:
  • ARM TrustZone® enabled.
  • AES-256 encryption/decryption engine with keys fed directly from PUF or a software supplied key
  • Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA controller.
  • Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes hardware for key extraction.
  • True Random Number Generator (TRNG).
  • 128 bit unique device serial number for identification (UUID).
  • Secure GPIO.
  • Timers:
  • Five 32-bit standard general purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests.
  • One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and match registers). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 captures/matches, 16 events, and 32 states.

  • 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. Another timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. The RTC is clocked by the 32 kHz FRO or 32.768 kHz external crystal.
  • Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.
  • Windowed Watchdog Timer (WWDT) with FRO 1 MHz as clock source.
  • The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up the device from sleep and deep-sleep modes. Includes 4 capture registers with pin inputs.
  • 42-bit free running OS Timer as continuous time-base for the system, available in any reduced power modes. It runs on 32kHz clock source, allowing a count period of more than 4 years.
  • Analog peripherals:
  • 16-bit ADC with five differential channel pair (or 10 single-ended channels), and with multiple internal and external trigger inputs and sample rates of up to 1.0 MSamples/sec. The ADC supports simultaneous conversions, on two ADC input channels belonging to a differential pair.
  • Integrated temperature sensor connected to the ADC.
  • Comparator with five input pins and external or internal reference voltage.

Pin Configuration

Table 4 shows the pin functions available on each pin, and for each package. These functions are selectable using the IOCON control registers.

Some functions, such as ADC or comparator inputs, are available only on specific pins when digital functions are disabled on those pins. By default, the GPIO function is selected except on pins PIO0_11 an PIO0_12, which are the serial wire debug pins. This allows debug to operate through reset.

All pins have all pull-ups, pull-downs, and inputs turned off at reset except PIO0_2, PIO0_5, PIO0_11, PIO0_12, PIO0_13 and PIO0_14 pins. This prevents power loss through pins prior to software configuration. Due to special pin functions, some pins have a different reset configuration. PIO0_5 and PIO0_12 pins have internal pull-up enabled by default, and PIO0_2 and PIO0_11 have internal pull-down enabled by default. PIO0_13 and PIO0_14 are true open drain pins. Refer to pin description table for default reset configuration.

The state of port pin PIO0_5 at Reset determines the boot source of the part or if the handler is invoked.

The external reset pin or 3 wake-up pins can trigger a wake-up from deep power-down mode. For the wake-up pins, do not assign any function to this pin if it will be used as a wake-up input when using deep power-down mode. If not in deep power-down mode, a function can be assigned to this pin. If the pin is used for wake-up, it should be pulled HIGH externally before entering deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit deep power-down mode wakes up the part.

The JTAG functions TRST, TCK, TMS, TDI, and TDO, are selected on pins PIO0_2 to PIO0_6 by hardware when the part is in boundary scan mode. The JTAG functions cannot be used for debug mode.

Table 3. Pin description

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_0/ ACMP0_A36L1254[4]ZI/O ; AI0PIO0_0/ACMP0_A- General-purpose digital input/output pin. Comparator 0, input Aif the DIGIMODE bit is set to 0 andANAMODE is set to 1 in the IOCON register for this pin.
PIO0_0/ ACMP0_A1R- Reserved.
PIO0_0/ ACMP0_AI/O2FC3_SCK- Flexcomm 3: USART, SPI, or I2S clock.
PIO0_0/ ACMP0_AO3CTIMER0_MAT0- 32-bit CTimer0 match output 0.
PIO0_0/ ACMP0_AI4SCT0_GPI0- Pin input 0 to SCTimer/PWM.
PIO0_0/ ACMP0_A5R- Reserved.
PIO0_0/ ACMP0_AI6 SD1_CARD_INT_N- SD/MMC 1 card interrupt.
PIO0_0/ ACMP0_A7R- Reserved.
PIO0_0/ ACMP0_A8 9R- Reserved.
PIO0_0/ ACMP0_AR- Reserved.
PIO0_12F57[2]ZI/O0 PIO0_1- General-purpose digital input/output pin.
PIO0_11R- Reserved.
PIO0_1I/O2FC3_CTS_SDA_SSEL0- Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_1I3CTIMER_INP0- Capture input to CTIMER input muxes.
PIO0_1I4SCT0_GPI1- Pin input 1 to SCTimer/PWM.
PIO0_15R- Reserved.
PIO0_1O6SD1_CLK- SD/MMC 1 card clock.
PIO0_1O7CMP0_OUT- Analog comparator 0 output.
PIO0_18R- Reserved.
PIO0_19R- Reserved.
PIO0_1I/O1 0SEC_PIO0_1- Secure GPIO pin.

Table 3. Pin description

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_2/ TRST52B1181[2][11]PDI/O0PIO0_2- General-purpose digital input/output pin. In boundary scan mode: TRST (Test Reset). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MISO function.
PIO0_2/ TRST52B1181[2][11]PDI/O1FC3_TXD_SCL_MISO_WS- Flexcomm 3: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_2/ TRST52B1181[2][11]PDI2CTIMER_INP1- Capture input to CTIMER input multiplexers.
PIO0_2/ TRST52B1181[2][11]PDO3SCT0_OUT0- SCTimer/PWM output 0.
PIO0_2/ TRST52B1181[2][11]PDI4SCT0_GPI2- Pin input 2 to SCTimer/PWM.
PIO0_2/ TRST52B1181[2][11]PD5R- Reserved.
PIO0_2/ TRST52B1181[2][11]PD6R- Reserved.
PIO0_2/ TRST52B1181[2][11]PD7R- Reserved.
PIO0_2/ TRST52B1181[2][11]PD8R- Reserved.
PIO0_2/ TRST52B1181[2][11]PD9R- Reserved.
PIO0_2/ TRST52B1181[2][11]PDI/O1 0 SEC_PIO0_2- Secure GPIO pin.
PIO0_3/ TCK53F883[2][11]ZI/O0PIO0_3- General-purpose digital input/output pin. In boundary scan mode: TCK (Test Clock In).
PIO0_3/ TCK53F883[2][11]ZI/O1FC3_RXD_SDA_MOSI_DATA- Flexcomm 3: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_3/ TCK53F883[2][11]ZO2CTIMER0_MAT1- 32-bit CTimer0 match output 1.
PIO0_3/ TCK53F883[2][11]ZO3SCT0_OUT1- SCTimer/PWM output 1.
PIO0_3/ TCK53F883[2][11]ZI4SCT0_GPI3- Pin input 3 to SCTimer/PWM.
PIO0_3/ TCK53F883[2][11]Z5R- Reserved.
PIO0_3/ TCK53F883[2][11]Z6 7R- Reserved. R- Reserved.
PIO0_3/ TCK53F883[2][11]Z8R- Reserved.
PIO0_3/ TCK53F883[2][11]Z9R- Reserved.
PIO0_3/ TCK53F883[2][11]ZI/O1 0SEC_PIO0_3- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_4/ TMS55E786[2][11]ZI/O0PIO0_4- General-purpose digital input/output pin. In boundary scan mode: TMS (Test Mode Select). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SSEL0 function.
PIO0_4/ TMS55E786[2][11]ZI/O1R- Reserved.
PIO0_4/ TMS55E786[2][11]ZI/O2FC4_SCK- Flexcomm 4: USART, SPI, or I2S clock.
PIO0_4/ TMS55E786[2][11]ZI3CTIMER_INP12- Capture input to CTIMER input multiplexers.
PIO0_4/ TMS55E786[2][11]ZI4SCT0_GPI4- Pin input 4 to SCTimer/PWM.
PIO0_4/ TMS55E786[2][11]Z5R- Reserved.
PIO0_4/ TMS55E786[2][11]Z6R- Reserved.
PIO0_4/ TMS55E786[2][11]Z7R- Reserved.
PIO0_4/ TMS55E786[2][11]ZI/O8FC3_CTS_SDA_SSEL0- Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_4/ TMS55E786[2][11]ZI/O1SEC_PIO0_4- Secure GPIO pin.
PIO0_5/ TDI56A788[2][11]PUI/O0PIO0_5- General-purpose digital input/output pin. In boundary scan mode: TDI (Test Data In).
PIO0_5/ TDI56A788[2][11]PUI/O1source for the part or if ISP handler is invoked. See the Boot Process chapter in UM11126 for more details.
PIO0_5/ TDI56A788[2][11]PUI/O2R- Reserved. FC4_RXD_SDA_MOSI_DATA- Flexcomm 4: USART
PIO0_5/ TDI56A788[2][11]PUO3CTIMER3_MAT0- 32-bit CTimer3 match output 0.
PIO0_5/ TDI56A788[2][11]PUI4SCT0_GPI5- Pin input 5 to SCTimer/PWM.
PIO0_5/ TDI56A788[2][11]PU5R- Reserved.
PIO0_5/ TDI56A788[2][11]PU6 7R- Reserved.
PIO0_5/ TDI56A788[2][11]PUI/O8R- Reserved. FC3_RTS_SCL_SSEL1- Flexcomm 3: USART
PIO0_5/ TDI56A788[2][11]PUI/OMCLK- MCLK input or output for I2S.
PIO0_5/ TDI56A788[2][11]PUI/O9 1SEC_PIO0_5- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_6/ TDO57B789[2][11]ZI/O0PIO0_6- General-purpose digital input/output pin. In boundary scan mode: TDO (Test Data Out). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SCK function.
PIO0_6/ TDOI/O 1FC3_SCK- Flexcomm 3: USART, SPI, or I2S clock.
PIO0_6/ TDOI2CTIMER_INP13- Capture input to CTIMER input multiplexers.
PIO0_6/ TDOO3 CTIMER4_MAT0- 32-bit CTimer4 match output 0.
PIO0_6/ TDOI4SCT0_GPI6- Pin input 6 to SCTimer/PWM.
PIO0_6/ TDO5R- Reserved.
PIO0_6/ TDO6R- Reserved.
PIO0_6/ TDO7R- Reserved.
PIO0_6/ TDO8R- Reserved.
PIO0_6/ TDO9R- Reserved.
PIO0_71G56[2]ZI/O0 PIO0_7- General-purpose digital input/output pin.
PIO0_7I/O1FC3_RTS_SCL_SSEL1- Flexcomm 3: USART request-to-send, I2C clock, SPI slave select 1.
PIO0_7O2SD0_CLK- SD/MMC 0 card clock.
PIO0_7I/O3 FC5_SCK- Flexcomm 5: USART, SPI, or I2S clock.
PIO0_7I/O4 FC1_SCK- Flexcomm 1: USART, SPI, or I2S clock.
PIO0_75R- Reserved.
PIO0_76R- Reserved.
PIO0_77R- Reserved.
PIO0_78R- Reserved.
PIO0_79R- Reserved.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]Type Function #Description
PIO0_817M226[2]ZI/O0 PIO0_8- General-purpose digital input/output pin.
PIO0_817M226[2]ZI/O 1FC3_SSEL3- Flexcomm 3: SPI slave select 3.
PIO0_817M226[2]ZI/O 2SD0_CMD- SD/MMC 0 card command I/O.
PIO0_817M226[2]ZI/O 3FC5_RXD_SDA_MOSI_DATA- Flexcomm 5: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_817M226[2]ZO 4SWO- Serial Wire Debug trace output.
PIO0_817M226[2]Z5R- Reserved.
PIO0_817M226[2]Z6R- Reserved.
PIO0_817M226[2]Z7R- Reserved.
PIO0_817M226[2]Z8R- Reserved.
PIO0_817M226[2]Z9R- Reserved.
PIO0_817M226[2]ZI/O1 0 SEC_PIO0_8- Secure GPIO pin.
PIO0_9/ ACMP0_B37L1355[4]ZI/O ; AI 0PIO0_9/ACMP0_B- General-purpose digital input/output pin. Comparator 0, input B if the DIGIMODE bit is set to 0 andANAMODE is set to 1 in the IOCON register for this pin.
PIO0_9/ ACMP0_B37L1355[4]ZI/O 1FC3_SSEL2- Flexcomm 3: SPI slave select 2.
PIO0_9/ ACMP0_B37L1355[4]ZO 2SD0_POW_EN- SD/MMC 0 card power enable.
PIO0_9/ ACMP0_B37L1355[4]ZI/O 3FC5_TXD_SCL_MISO_WS- Flexcomm 5: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_9/ ACMP0_B37L1355[4]Z4R- Reserved.
PIO0_9/ ACMP0_B37L1355[4]Z5R- Reserved.
PIO0_9/ ACMP0_B37L1355[4]Z6R- Reserved.
PIO0_9/ ACMP0_B37L1355[4]Z7R- Reserved.
PIO0_9/ ACMP0_B37L1355[4]Z8R- Reserved.
PIO0_9/ ACMP0_B37L1355[4]Z9R- Reserved.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_10/ ADC0_113F221[4]ZI/O ; AI0PIO0_10/ADC0_1- General-purpose digital input/output pin.ADC single ended input channel 1A - CH1A. Can optionally be paired with CH1B as the positive differential input on ADC1 channel 1.
PIO0_10/ ADC0_113F221[4]ZI/O1FC6_SCK- Flexcomm 6: USART, SPI, or I2S clock.
PIO0_10/ ADC0_113F221[4]ZI2CTIMER_INP10- Capture input to CTIMER input multiplexers.
PIO0_10/ ADC0_113F221[4]ZO3CTIMER2_MAT0- 32-bit CTimer2 match output 0.
PIO0_10/ ADC0_113F221[4]ZI/O4FC1_TXD_SCL_MISO_WS- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_10/ ADC0_113F221[4]ZO5SCT0_OUT2- SCTimer/PWM output 2.
PIO0_10/ ADC0_113F221[4]ZO6SWO- Serial Wire Debug trace output.
PIO0_10/ ADC0_113F221[4]Z7R- Reserved.
PIO0_10/ ADC0_113F221[4]Z8R- Reserved.
PIO0_10/ ADC0_113F221[4]Z9R- Reserved.
PIO0_11/ ADC0_96F113[4]PDI/O ; AI0PIO0_11/ADC0_9- General-purpose digital input/output pin.ADC single ended input channel 1B - CH1B. Can optionally be paired with CH1Aas the negative differential input on ADC1 channel 1.
PIO0_11/ ADC0_96F113[4]PDI/O1FC6_RXD_SDA_MOSI_DATA- Flexcomm 6: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_11/ ADC0_96F113[4]PDO2CTIMER2_MAT2- 32-bit CTimer2 match output 2.
PIO0_11/ ADC0_96F113[4]PDI3FREQME_GPIO_CLK_A- Frequency Measure pin clock input A.
PIO0_11/ ADC0_96F113[4]PD4R- Reserved.
PIO0_11/ ADC0_96F113[4]PDI6SWCLK- Serial Wire Debug clock. This is the default function after booting.
PIO0_11/ ADC0_96F113[4]PD7
PIO0_11/ ADC0_96F113[4]PDR- Reserved.
PIO0_11/ ADC0_96F113[4]PD8R- Reserved.
PIO0_11/ ADC0_96F113[4]PDI/O9 1R- Reserved. SEC_PIO0_11- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_12/ ADC0_105E212[4]PUI/O ; AI0PIO0_12/ADC0_10- General-purpose digital input/output pin.ADC single ended input channel 2B - CH2B. Can optionally be paired with CH2Aas the negative differential input on ADC1 channel 2.
PIO0_12/ ADC0_105E212[4]PUI/O1FC3_TXD_SCL_MISO_WS- Flexcomm 3: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_12/ ADC0_105E212[4]PUO2SD1_BACKEND_PWR- SD/MMC 1 back-end power supply for embedded device.
PIO0_12/ ADC0_105E212[4]PUI3FREQME_GPIO_CLK_B- Frequency Measure pin clock input B.
PIO0_12/ ADC0_105E212[4]PUI4SCT0_GPI7- Pin input 7 to SCTimer/PWM.
PIO0_12/ ADC0_105E212[4]PUO5SD0_POW_EN- SD/MMC 0 card power enable.
PIO0_12/ ADC0_105E212[4]PUI/O6SWDIO- Serial Wire Debug I/O. This is the default function after booting.
PIO0_12/ ADC0_105E212[4]PUI/O7FC6_TXD_SCL_MISO_WS- Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_12/ ADC0_105E212[4]PU8R- Reserved.
PIO0_12/ ADC0_105E212[4]PU9R- Reserved.
PIO0_1346C1271[3]ZI/O0PIO0_13- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SDA function.
PIO0_1346C1271[3]ZI/O1FC1_CTS_SDA_SSEL0- Flexcomm 1: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_1346C1271[3]ZI2UTICK_CAP0- Micro-tick timer capture input 0.
PIO0_1346C1271[3]ZI3CTIMER_INP0- Capture input to CTIMER input multiplexers.
PIO0_1346C1271[3]ZI4SCT0_GPI0- Pin input 0 to SCTimer/PWM.
PIO0_1346C1271[3]ZI/O 5FC1_RXD_SDA_MOSI_DATA- Flexcomm 1: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_1346C1271[3]Z6R- Reserved.
PIO0_1346C1271[3]Z7R- Reserved.
PIO0_1346C1271[3]ZI9PLU_INPUT0- PLU input 0.
PIO0_1346C1271[3]ZI/O1SEC_PIO0_13- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_1447C1372[3]ZI/O0PIO0_14- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SCL function.
PIO0_14I/O1FC1_RTS_SCL_SSEL1- Flexcomm 1: USART request-to-send, I2C clock, SPI slave select 1.
PIO0_14I2UTICK_CAP1- Micro-tick timer capture input 1.
PIO0_14I3CTIMER_INP1- Capture input to CTIMER input multiplexers.
PIO0_14I4SCT0_GPI1- Pin input 1 to SCTimer/PWM.
PIO0_145R- Reserved.
PIO0_14I/O6FC1_TXD_SCL_MISO_WS- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_147R- Reserved.
PIO0_148R- Reserved.
PIO0_14I9PLU_INPUT1- PLU input 1.
PIO0_14I/O1SEC_PIO0_14- Secure GPIO pin.
PIO0_15/ ADC0_214L222[4]ZI/O ; AI0PIO0_15/ADC0_2- General-purpose digital input/output pin.ADC single ended input channel 2A - CH2A. Can optionally be paired with CH2B as the positive differential input on ADC1 channel 2.
PIO0_15/ ADC0_2I/O1FC6_CTS_SDA_SSEL0- Flexcomm 6: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_15/ ADC0_2I2UTICK_CAP2- Micro-tick timer capture input 2.
PIO0_15/ ADC0_2I3CTIMER_INP16- Capture input to CTIMER input multiplexers.
PIO0_15/ ADC0_2O4SCT0_OUT2- SCTimer/PWM output 2.
PIO0_15/ ADC0_2I5SD0_WR_PRT- SD/MMC 0 write protect.
PIO0_15/ ADC0_26R- Reserved.
PIO0_15/ ADC0_27R- Reserved.
PIO0_15/ ADC0_28R- Reserved.
PIO0_15/ ADC0_29R- Reserved.
PIO0_15/ ADC0_2I/O1 0SEC_PIO0_15- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_16/ ADC0_87J214[4]ZI/O ; AI0PIO0_16/ADC0_8- General-purpose digital input/output pin.ADC single ended input channel 0B - CH0B. Can optionally be paired with CH0Aas the negative differential input on ADC1 channel 0.
PIO0_16/ ADC0_87J214[4]I/O1FC4_TXD_SCL_MISO_WS- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_16/ ADC0_87J214[4]O2CLKOUT- Output of the CLKOUT function.
PIO0_16/ ADC0_87J214[4]I3CTIMER_INP4- Capture input to CTIMER input multiplexers.
PIO0_16/ ADC0_87J214[4]4R- Reserved.
PIO0_16/ ADC0_87J214[4]5R- Reserved.
PIO0_16/ ADC0_87J214[4]6R- Reserved.
PIO0_16/ ADC0_87J214[4]7R- Reserved.
PIO0_16/ ADC0_87J214[4]8R- Reserved.
PIO0_16/ ADC0_87J214[4]9R- Reserved.
PIO0_16/ ADC0_87J214[4]I/O1SEC_PIO0_16- Secure GPIO pin.
PIO0_173G38[2]ZI/O0PIO0_17- General-purpose digital input/output pin.
3G38[2]I/O1FC4_SSEL2- Flexcomm 4: SPI slave select 2.
3G38[2]I2SD0_CARD_DET_N- SD/MMC 0 card detect (active low).
3G38[2]I3SCT0_GPI7- Pin input 7 to SCTimer/PWM.
3G38[2]O4SCT0_OUT0- SCTimer/PWM output 0.
3G38[2]5R- Reserved.
3G38[2]6R- Reserved.
3G38[2]7R- Reserved.
3G38[2]I8SD0_CARD_INT_N- SD/MMC 0 card interrupt.
3G38[2]I9PLU_INPUT2- PLU input 2.
3G38[2]I/O1 0SEC_PIO0_17- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_18/ ACMP0_C38H956[4]ZI/O ; AI0PIO0_18/ACMP0_C- General-purpose digital input/output pin. Comparator 0, input C if the DIGIMODE bit is set to 0 andANAMODE is set to 1 in the IOCON register for this pin.
PIO0_18/ ACMP0_C38H956[4]ZI/O1FC4_CTS_SDA_SSEL0- Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_18/ ACMP0_C38H956[4]ZI2SD0_WR_PRT- SD/MMC 0 write protect.
PIO0_18/ ACMP0_C38H956[4]ZO3CTIMER1_MAT0- 32-bit CTimer1 match output 0.
PIO0_18/ ACMP0_C38H956[4]ZO4SCT0_OUT1- SCTimer/PWM output 1.
PIO0_18/ ACMP0_C38H956[4]Z5R- Reserved.
PIO0_18/ ACMP0_C38H956[4]Z6R- Reserved.
PIO0_18/ ACMP0_C38H956[4]Z7R- Reserved.
PIO0_18/ ACMP0_C38H956[4]Z8R- Reserved.
PIO0_18/ ACMP0_C38H956[4]ZI9PLU_INPUT3- PLU input 3.
PIO0_18/ ACMP0_C38H956[4]ZI/O1SEC_PIO0_18- Secure GPIO pin.
PIO0_1958E690[2]ZI/O0PIO0_19- General-purpose digital input/output pin.
PIO0_1958E690[2]ZI/O1FC4_RTS_SCL_SSEL1- Flexcomm 4: USART request-to-send, I2C clock, SPI slave select 1.
PIO0_1958E690[2]ZI2UTICK_CAP0- Micro-tick timer capture input 0.
PIO0_1958E690[2]ZO3CTIMER0_MAT2- 32-bit CTimer0 match output 2.
PIO0_1958E690[2]ZO4SCT0_OUT2- SCTimer/PWM output 2.
PIO0_1958E690[2]Z5R- Reserved.
PIO0_1958E690[2]Z6R- Reserved.
PIO0_1958E690[2]ZI/O7FC7_TXD_SCL_MISO_WS- Flexcomm 7: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_1958E690[2]Z8R- Reserved.
PIO0_1958E690[2]ZI9 PLU_INPUT4- PLU input 4.
PIO0_1958E690[2]ZI/O1 0SEC_PIO0_19- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO0_2048B1274[2]ZI/O0PIO0_20- General-purpose digital input/output pin.
PIO0_2048B1274[2]ZI/O1FC3_CTS_SDA_SSEL0- Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_2048[2]ZO2CTIMER1_MAT1- 32-bit CTimer1 match output 1.
PIO0_2048[2]ZI3CTIMER_INP15- Capture input to CTIMER input multiplexers.
PIO0_2048[2]ZI4SCT0_GPI2- Pin input 2 to SCTimer/PWM.
PIO0_2048[2]Z5R- Reserved.
PIO0_2048[2]Z6R- Reserved.
PIO0_2048[2]ZI/O7FC7_RXD_SDA_MOSI_DATA- Flexcomm 7: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_2048[2]ZI/O8 HS_SPI_SSEL0- Slave Select 0 for high speed SPI.
PIO0_2048[2]ZI9PLU_INPUT5- PLU input 5.
PIO0_2048[2]ZI/O1SEC_PIO0_20- Secure GPIO pin.
PIO0_2048[2]ZI/O1 1FC4_TXD_SCL_MISO_WS- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_2149A1276[2]ZI/O0PIO0_21- General-purpose digital input/output pin.
PIO0_2149A1276[2]ZI/O1FC3_RTS_SCL_SSEL1- Flexcomm 3: USART request-to-send, I2C clock, SPI slave select 1.
PIO0_214976[2]ZI2UTICK_CAP3- Micro-tick timer capture input 3.
PIO0_214976[2]ZO3CTIMER3_MAT3- 32-bit CTimer3 match output 3.
PIO0_214976[2]ZI4SCT0_GPI3- Pin input 3 to SCTimer/PWM.
PIO0_214976[2]Z5R- Reserved.
PIO0_214976[2]Z6R- Reserved.
PIO0_214976[2]ZI/O 7FC7_SCK- Flexcomm 7: USART, SPI, or I2S clock.
PIO0_214976[2]ZI8 9R- Reserved. PLU_CLKIN- PLU clock input.
PIO0_214976[2]ZI/O1SEC_PIO0_21- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_2250E978[2][8]ZI/O0PIO0_22- General-purpose digital input/output pin.
PIO0_2250E978[2][8]ZI/O1FC6_TXD_SCL_MISO_WS- Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_2250E978[2][8]ZI2UTICK_CAP1- Micro-tick timer capture input 1.
PIO0_2250E978[2][8]ZI3CTIMER_INP15- Capture input to CTIMER input multiplexers.
PIO0_2250E978[2][8]ZO4SCT0_OUT3- SCTimer/PWM output 3.
PIO0_2250E978[2][8]Z5R- Reserved.
PIO0_2250E978[2][8]Z6R- Reserved.
PIO0_2250E978[2][8]ZI7USB0_VBUS- Monitors the presence of USB0 bus power.
PIO0_2250E978[2][8]ZI/O8SD1_D[0]- SD/MMC 1 data 0.
PIO0_2250E978[2][8]ZO9PLU_OUT7- PLU output 7.
PIO0_23/ ADC0_012J120[4]ZI/O ; AI0PIO0_23/ADC0_0- General-purpose digital input/output pin.ADC single ended input channel 0A - CH0A. Can optionally be paired with CH0B as the positive differential input on ADC1 channel 0.
PIO0_23/ ADC0_012J120[4]ZI/O1MCLK- MCLK input or output for I2S.
PIO0_23/ ADC0_012J120[4]ZO2CTIMER1_MAT2- 32-bit CTimer1 match output 2.
PIO0_23/ ADC0_012J120[4]ZO3CTIMER3_MAT3- 32-bit CTimer3 match output 3.
PIO0_23/ ADC0_012J120[4]ZO4SCT0_OUT4- SCTimer/PWM output 4.
PIO0_23/ ADC0_012J120[4]ZI/O5FC0_CTS_SDA_SSEL0- Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_23/ ADC0_012J120[4]Z6R- Reserved.
PIO0_23/ ADC0_012J120[4]Z7R- Reserved.
PIO0_23/ ADC0_012J120[4]ZI/O8 SD1_D[1]- SD/MMC 1 data 1.
PIO0_23/ ADC0_012J120[4]ZI/O9R- Reserved. 1 SEC_PIO0_23- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_2445E1270[2]ZI/O0PIO0_24- General-purpose digital input/output pin.
PIO0_2445E1270I/O1FC0_RXD_SDA_MOSI_DATA- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_244570I/O2SD0_D[0]- SD/MMC 0 data 0.
PIO0_244570I3CTIMER_INP8- Capture input to CTIMER input multiplexers.
PIO0_244570I4SCT0_GPI0- Pin input 0 to SCTimer/PWM.
PIO0_2445705R- Reserved.
PIO0_2445706R- Reserved.
PIO0_2445707R- Reserved.
PIO0_2445708R- Reserved.
PIO0_2445709R- Reserved.
PIO0_2551A1179[2]ZI/O0PIO0_25- General-purpose digital input/output pin.
PIO0_2551A1179[2]I/O1FC0_TXD_SCL_MISO_WS- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_255179[2]I/O2SD0_D[1]- SD/MMC 0 data 1.
PIO0_255179[2]I3CTIMER_INP9- Capture input to CTIMER input multiplexers.
PIO0_255179[2]I4SCT0_GPI1- Pin input 1 to SCTimer/PWM.
PIO0_255179[2]5R- Reserved.
PIO0_255179[2]6R- Reserved.
PIO0_255179[2]7R- Reserved.
PIO0_255179[2]8R- Reserved.
PIO0_255179[2]9R- Reserved.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_2640H1260[2][8]ZI/O0PIO0_26- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the HS SPI MOSI function (Flexcomm 8)
PIO0_26I/O1FC2_RXD_SDA_MOSI_DATA- Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_26O2CLKOUT- Output of the CLKOUT function.
PIO0_26I3CTIMER_INP14- Capture input to CTIMER input multiplexers.
PIO0_26O4SCT0_OUT5- SCTimer/PWM output 5.
PIO0_265R- Reserved.
PIO0_266R- Reserved.
PIO0_26I7USB0_IDVALUE- Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).
PIO0_26I/O8FC0_SCK- Flexcomm 0: USART, SPI, or I2S clock.
PIO0_26I/O9HS_SPI_MOSI- Master-out/slave-in data for high speed SPI.
PIO0_26I/O1SEC_PIO0_26- Secure GPIO pin.
PIO0_2718N227[2]ZI/O0PIO0_27- General-purpose digital input/output pin.
PIO0_27I/O1FC2_TXD_SCL_MISO_WS- Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_272R- Reserved.
PIO0_27O3CTIMER3_MAT2- 32-bit CTimer3 match output 2.
PIO0_27O4SCT0_OUT6- SCTimer/PWM output 6.
PIO0_275R- Reserved.
PIO0_276R- Reserved.
PIO0_27I/O7FC7_RXD_SDA_MOSI_DATA- Flexcomm 7: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO0_278R- Reserved.
PIO0_27O9PLU_OUT0- PLU output 0.
PIO0_27I/O1 0SEC_PIO0_27- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_28/ WAKEUP44F1366[2][8]ZI/O0PIO0_28- General-purpose digital input/output pin. This pin can trigger a wake-up from deep power-down mode. WAKEUP pin can be configured as rising or falling edge
PIO0_28/ WAKEUP44F1366[2][8]ZI/O1FC0_SCK- Flexcomm 0: USART, SPI, or I2S clock.
PIO0_28/ WAKEUP44F1366[2][8]ZI/O2SD1_CMD- SD/MMC 1 card command I/O.
PIO0_28/ WAKEUP44F1366[2][8]ZI3CTIMER_INP11- Capture input to CTIMER input multiplexers.
PIO0_28/ WAKEUP44F1366[2][8]ZO4SCT0_OUT7- SCTimer/PWM output 7.
PIO0_28/ WAKEUP44F1366[2][8]Z5R- Reserved.
PIO0_28/ WAKEUP44F1366[2][8]Z6R- Reserved.
PIO0_28/ WAKEUP44F1366[2][8]ZI7USB0_OVERCURRENTN- USB0 bus overcurrent indicator (active low).
PIO0_28/ WAKEUP44F1366[2][8]Z8R- Reserved.
PIO0_28/ WAKEUP44F1366[2][8]ZO9PLU_OUT1- PLU output 1.
PIO0_2959H892[2]ZI/O0PIO0_29- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 0 USART RXD function.
59H892[2]ZI/O1FC0_RXD_SDA_MOSI_DATA- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
59H892[2]ZI/O2SD1_D[2]- SD/MMC 1 data 2.
59H892[2]ZO3CTIMER2_MAT3- 32-bit CTimer2 match output 3.
59H892[2]ZO4SCT0_OUT8- SCTimer/PWM output 8.
59H892[2]Z5R- Reserved.
59H892[2]ZO7CMP0_OUT- Analog comparator 0 output.
59H892[2]ZO9PLU_OUT2- PLU output 2.
59H892[2]ZI/O1 0SEC_PIO0_29- Secure GPIO pin.
59H892[2]Z

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO0_3060E594[2]ZI/O0PIO0_30- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 0 USART TXD function.
PIO0_3060E594[2]ZI/O1FC0_TXD_SCL_MISO_WS- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO0_3060E594[2]ZI/O2SD1_D[3]- SD/MMC 1 data 3.
PIO0_3060E594[2]ZO3CTIMER0_MAT0- 32-bit CTimer0 match output 0.
PIO0_3060E594[2]ZO4SCT0_OUT9- SCTimer/PWM output 9.
PIO0_3060E594[2]Z5R- Reserved.
PIO0_3060E594[2]Z6R- Reserved.
PIO0_3060E594[2]Z7R- Reserved.
PIO0_3060E594[2]Z8R- Reserved.
PIO0_3060E594[2]Z9R- Reserved.
PIO0_3060E594[2]ZI/O1SEC_PIO0_30- Secure GPIO pin.
PIO0_31/ ADC0_315L123[4]ZI/O ; AI0PIO0_31/ADC0_3- General-purpose digital input/output pin.ADC single ended input channel 3A - CH3A. Can optionally be paired with CH3B as the positive differential input on ADC1 channel 3.
PIO0_31/ ADC0_315L123[4]ZI/O1FC0_CTS_SDA_SSEL0- Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO0_31/ ADC0_315L123[4]ZI/O2SD0_D[2]- SD/MMC 0 data 2.
PIO0_31/ ADC0_315L123[4]ZO3CTIMER0_MAT1- 32-bit CTimer0 match output 1.
PIO0_31/ ADC0_315L123[4]ZO4SCT0_OUT3- SCTimer/PWM output 3.
PIO0_31/ ADC0_315L123[4]Z6R- Reserved.
PIO0_31/ ADC0_315L123[4]Z7R- Reserved.
PIO0_31/ ADC0_315L123[4]Z8R- Reserved.
PIO0_31/ ADC0_315L123[4]Z9R- Reserved.
PIO0_31/ ADC0_315L123[4]ZI/O1 0SEC_PIO0_31- Secure GPIO pin.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]Type# Description
PIO1_0/ ADC0_114E111[4]ZI/O ; AIPIO1_0/ADC0_11- General-purpose digital input/output pin.ADC single ended input channel 3B - CH3B. Can optionally be paired with CH3Aas the negative differential input on ADC1 channel 3.
PIO1_0/ ADC0_114E111[4]ZI/OFC0_RTS_SCL_SSEL1- Flexcomm 0: USART request-to-send, I2C clock, SPI slave select 1.
PIO1_0/ ADC0_114E111[4]ZI/OSD0_D[3]- SD/MMC 0 data 3.
PIO1_0/ ADC0_114E111[4]ZICTIMER_INP2- Capture input to CTIMER input multiplexers.
PIO1_0/ ADC0_114E111[4]ZISCT0_GPI4- Pin input 4 to SCTimer/PWM.
PIO1_0/ ADC0_114E111[4]ZR- Reserved.
PIO1_0/ ADC0_114E111[4]ZR- Reserved.
PIO1_0/ ADC0_114E111[4]ZR- Reserved.
PIO1_0/ ADC0_114E111[4]ZR- Reserved.
PIO1_1/ WAKEUP39G1159[2][8]ZI/OPIO1_1- General-purpose digital input/output pin. This pin can trigger a wake-up from deep power-down mode. WAKEUP pin can be configured as rising or falling edge Remark: In ISP mode, this pin is set to the High Speed SPI SSEL1 function (Flexcomm 8)
PIO1_1/ WAKEUP39G1159[2][8]ZI/OFC3_RXD_SDA_MOSI_DATA- Flexcomm 3: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO1_1/ WAKEUP39G1159[2][8]ZR- Reserved.
PIO1_1/ WAKEUP39G1159[2][8]ZICTIMER_INP3- Capture input to CTIMER input multiplexers.
PIO1_1/ WAKEUP39G1159[2][8]ZISCT0_GPI5- Pin input 5 to SCTimer/PWM.
PIO1_1/ WAKEUP39G1159[2][8]ZI/OHS_SPI_SSEL1- Slave Select 1 for high speed SPI.
PIO1_1/ WAKEUP39G1159[2][8]ZR- Reserved.
PIO1_1/ WAKEUP39G1159[2][8]ZIUSB1_OVERCURRENTN- USB1 bus overcurrent indicator (active low).
PIO1_1/ WAKEUP39G1159[2][8]ZR- Reserved.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO1_241G1261[2][8]ZI/O0 PIO1_2- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the High Speed SPI SCK function (Flexcomm 8).
PIO1_241G1261[2][8]ZI/O1 R- Reserved.
PIO1_241G1261[2][8]ZI/O2 R- Reserved.
PIO1_241G1261[2][8]ZO3 CTIMER0_MAT3- 32-bit CTimer0 match output 3.
PIO1_241G1261[2][8]ZI4 SCT0_GPI6- Pin input 6 to SCTimer/PWM.
PIO1_241G1261[2][8]Z5 R- Reserved.
PIO1_241G1261[2][8]ZI/O6 HS_SPI_SCK- Clock for high speed SPI.
PIO1_241G1261[2][8]ZO7 USB1_PORTPWRN- USB1 VBUS drive indicator (Indicates VBUS must be driven).
PIO1_241G1261[2][8]Z8 R- Reserved.
PIO1_342G1362[2][8]ZI/O0 PIO1_3- General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the High Speed SPI MISO function (Flexcomm 8).
PIO1_342G1362[2][8]Z1 R- Reserved.
PIO1_342G1362[2][8]Z2 R- Reserved.
PIO1_342G1362[2][8]Z3 R- Reserved.
PIO1_342G1362[2][8]ZO4 SCT0_OUT4- SCTimer/PWM output 4.
PIO1_342G1362[2][8]Z5 R- Reserved.
PIO1_342G1362[2][8]ZI/O6 HS_SPI_MISO- Master-in/slave-out data for high speed SPI.
PIO1_342G1362[2][8]Z8 R- Reserved.
PIO1_342G1362[2][8]ZO9 PLU_OUT6- PLU output 6.
PIO1_4-B21[2]ZI/O0 PIO1_4- General-purpose digital input/output pin.
PIO1_4-B21[2]ZI/O1 FC0_SCK- Flexcomm 0: USART, SPI, or I2S clock.
PIO1_4-B21[2]ZI/O2 SD0_D[0]- SD/MMC 0 data 0.
PIO1_4-B21[2]ZO3 CTIMER2_MAT1- 32-bit CTimer2 match output 1.
PIO1_4-B21[2]ZO4 SCT0_OUT0- SCTimer/PWM output 0.
PIO1_4-B21[2]ZI5 FREQME_GPIO_CLK_A- Frequency Measure pin clock input A.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO1_5-M531[2]ZI/O0 PIO1_5- General-purpose digital input/output pin.
PIO1_5-M531[2]ZI/O1 FC0_RXD_SDA_MOSI_DATA- Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO1_5-M531[2]ZI/O2 SD0_D[2]- SD/MMC 0 data 2.
PIO1_5-M531[2]ZO3 CTIMER2_MAT0- 32-bit CTimer2 match output 0.
PIO1_6-H55[2]ZI/O0 PIO1_6- General-purpose digital input/output pin.
PIO1_6-H55[2]ZI/O1 FC0_TXD_SCL_MISO_WS- Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO1_6-H55[2]ZI/O2 SD0_D[3]- SD/MMC 0 data 3.
PIO1_6-H55[2]ZO3 CTIMER2_MAT1- 32-bit CTimer2 match output 1.
PIO1_7-J59[2]ZI/O0 PIO1_7- General-purpose digital input/output pin.
PIO1_7-J59[2]ZI/O1 FC0_RTS_SCL_SSEL1- Flexcomm 0: USART request-to-send, I2C clock, SPI slave select 1.
PIO1_7-J59[2]ZI/O2 SD0_D[1]- SD/MMC 0 data 1.
PIO1_7-J59[2]ZO3 CTIMER2_MAT2- 32-bit CTimer2 match output 2.
PIO1_8/ ADC0_4-A624[4]ZI/O ; AI0 PIO1_8/ADC0_4- General-purpose digital input/output pin.ADC single ended input channel 4A - CH4A. Can optionally be paired with CH4B as the positive differential input on ADC1 channel 4.
PIO1_8/ ADC0_4-A624[4]ZI/O1 FC0_CTS_SDA_SSEL0- Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO1_8/ ADC0_4-A624[4]ZO2 SD0_CLK- SD/MMC 0 card clock.
PIO1_8/ ADC0_4-A624[4]Z3 R- Reserved.
PIO1_8/ ADC0_4-A624[4]ZO4 SCT0_OUT1- SCTimer/PWM output 1.
PIO1_8/ ADC0_4-A624[4]ZI/O5 FC4_SSEL2- Flexcomm 4: SPI slave select 2.
PIO1_8/ ADC0_4-A624[4]Z

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO1_9/ ADC0_12-C110[4]ZI/O ; AI0PIO1_9/ADC0_12- General-purpose digital input/output pin.ADC single ended input channel 4B - CH4B. Can optionally be paired with CH4Aas the negative differential input on ADC1 channel 4.
PIO1_9/ ADC0_12-C110[4]Z1R- Reserved.
PIO1_9/ ADC0_12-C110[4]ZI/O2FC1_SCK- Flexcomm 1: USART, SPI, or I2S clock.
PIO1_9/ ADC0_12-C110[4]ZI3CTIMER_INP4- Capture input to CTIMER input multiplexers.
PIO1_9/ ADC0_12-C110[4]ZO4SCT0_OUT2- SCTimer/PWM output 2.
PIO1_9/ ADC0_12-C110[4]ZI/O5FC4_CTS_SDA_SSEL0- Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO1_9/ ADC0_12-C110[4]Z6R- Reserved.
PIO1_9/ ADC0_12-C110[4]Z7R- Reserved.
PIO1_10-J740[2]ZI/O0PIO1_10- General-purpose digital input/output pin.
-J740[2]Z1R- Reserved.
-J740[2]ZI/O2 FC1_RXD_SDA_MOSI_DATA- Flexcomm 1: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
-J740[2]ZO3CTIMER1_MAT0- 32-bit CTimer1 match output 0.
-J740[2]ZO4SCT0_OUT3- SCTimer/PWM output 3.
-J740[2]Z5R- Reserved.
-J740[2]Z6R- Reserved.
-J740[2]Z7R- Reserved.
-J740[2]Z8R- Reserved.
PIO1_11-G693[2][8]ZI/O0PIO1_11- General-purpose digital input/output pin.
PIO1_11-G693[2][8]ZI/O2FC1_TXD_SCL_MISO_WS- Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO1_11-G693[2][8]ZI3CTIMER_INP5- Capture input to CTIMER input multiplexers.
PIO1_11-G693[2][8]ZI4USB0_VBUS- Monitors the presence of USB0 bus power.
PIO1_11-G693[2][8]Z5R- Reserved.
PIO1_11-G693[2][8]Z6R- Reserved.
PIO1_11-G693[2][8]Z7R- Reserved.
PIO1_11-G693[2][8]Z

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO1_12-F1267[2][8]ZI/O0PIO1_12- General-purpose digital input/output pin.
PIO1_12-F1267[2][8]Z1R- Reserved.
PIO1_12-F1267[2][8]ZI/O2 3FC6_SCK- Flexcomm 6: USART, SPI, or I2S clock. CTIMER1_MAT1- 32-bit CTimer1 match output 1.
PIO1_12-F1267[2][8]ZO4USB0_PORTPWRN- USB0 VBUS drive indicator (Indicates VBUS must be driven).
PIO1_12-F1267[2][8]ZOI/O 5HS_SPI_SSEL2- Slave Select 2 for high speed SPI.
PIO1_13-B32[2][8]ZI/O0PIO1_13- General-purpose digital input/output pin.
-B32[2][8]ZI/O1 2R- Reserved. FC6_RXD_SDA_MOSI_DATA- Flexcomm 6: USART
-B32[2][8]ZI3CTIMER_INP6- Capture input to CTIMER input multiplexers.
-B32[2][8]ZI4USB0_OVERCURRENTN- USB0 bus overcurrent indicator (active low).
-B32[2][8]ZO5USB0_FRAME- USB0 frame toggle signal.
-B32[2][8]Z6 R- Reserved.
-B32[2][8]ZI7SD0_CARD_DET_N- SD/MMC 0 card detect (active low).
PIO1_14/ ACMP0_D-L757[4][8]ZI/O ; AI0PIO1_14/ACMP0_D- General-purpose digital input/output pin. Comparator 0, input D if the DIGIMODE bit is set to 0 andANAMODE is set to 1 in the IOCON register for this pin.
PIO1_14/ ACMP0_D-L757[4][8]Z1R- Reserved.
PIO1_14/ ACMP0_D-L757[4][8]ZI O2 3UTICK_CAP2- Micro-tick timer capture input 2.
PIO1_14/ ACMP0_D-L757[4][8]ZI/O4CTIMER1_MAT2- 32-bit CTimer1 match output 2. FC5_CTS_SDA_SSEL0- Flexcomm 5: USART
PIO1_14/ ACMP0_D-L757[4][8]ZO5USB0_LEDN- USB0-configured LED indicator (active
PIO1_14/ ACMP0_D-L757[4][8]Zlow).
PIO1_14/ ACMP0_D-L757[4][8]ZI/O6 R- Reserved. 7 SD1_CMD- SD/MMC 1 card command I/O.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]Type Function# Description
PIO1_15-B682[2]ZI/O 0PIO1_15- General-purpose digital input/output pin.
PIO1_15-B682[2]Z1R- Reserved.
PIO1_15-B682[2]ZI 2UTICK_CAP3- Micro-tick timer capture input 3.
PIO1_15-B682[2]ZI/O 4multiplexers. FC5_RTS_SCL_SSEL1- Flexcomm 5: USART
PIO1_15-B682[2]ZI/O 5request-to-send, I2C clock, SPI slave select 1. FC4_RTS_SCL_SSEL1- Flexcomm 4: USART
PIO1_15-B682[2]Z6R- Reserved.
PIO1_16-C787[2]ZI/O 0PIO1_16- General-purpose digital input/output pin.
PIO1_16-C787[2]Z1R- Reserved.
PIO1_16-C787[2]ZI/O2 FC6_TXD_SCL_MISO_WS- Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO1_16-C787[2]ZO 3CTIMER1_MAT3- 32-bit CTimer1 match output 3.
PIO1_16-C787[2]ZI/O 4SD0_CMD- SD/MMC 0 card command I/O.
PIO1_16-C787[2]Z6R- Reserved.
PIO1_16-C787[2]Z7R- Reserved.
PIO1_17-J943[2]ZI/O 0PIO1_17- General-purpose digital input/output pin.
PIO1_17-J9431R- Reserved.
PIO1_17-J9432R- Reserved.
PIO1_17-J943I/O 3FC6_RTS_SCL_SSEL1- Flexcomm 6: USART request-to-send, I2C clock, SPI slave select 1.
PIO1_17-J9435R- Reserved.
PIO1_17-J9436R- Reserved.
PIO1_17-J943I7 SD1_CARD_INT_N- SD/MMC 1 card interrupt.
PIO1_17-J9438 R- Reserved.
PIO1_17-J943I 9SD1_CARD_DET_N- SD/MMC 1 card detect (active low).

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO1_18/ WAKUP-G964[2]ZI/O0 PIO1_18- General-purpose digital input/output pin. This pin can trigger a wake-up from deep power-down mode.
PIO1_18/ WAKUP-G964[2]ZO1 SD1_POW_EN- SD/MMC 1 card power enable.
PIO1_18/ WAKUP-G964[2]Z2 R- Reserved.
PIO1_18/ WAKUP-G964[2]Z3 R- Reserved.
PIO1_18/ WAKUP-G964[2]ZO4 SCT0_OUT5- SCTimer/PWM output 5.
PIO1_18/ WAKUP-G964[2]Z5 R- Reserved.
PIO1_18/ WAKUP-G964[2]Z6 R- Reserved.
PIO1_18/ WAKUP-G964[2]ZO7 PLU_OUT0- PLU output 0.
PIO1_19/ ACMPV REF-H1358[4]ZI/O ; AI0 PIO1_19/ACMPV REF - General-purpose digital input/output pin. Alternate reference voltage for the analog comparator if the DIGIMODE bit is set to 0 andANAMODE is set to 1 in the IOCON register for this pin.
PIO1_19/ ACMPV REF-H1358[4]Z1 R- Reserved.
PIO1_19/ ACMPV REF-H1358[4]ZO2 SCT0_OUT7- SCTimer/PWM output 7.
PIO1_19/ ACMPV REF-H1358[4]ZO3 CTIMER3_MAT1- 32-bit CTimer3 match output 1.
PIO1_19/ ACMPV REF-H1358[4]ZI/O5 FC4_SCK- Flexcomm 4: USART, SPI, or I2S clock.
PIO1_19/ ACMPV REF-H1358[4]Z6 R- Reserved.
PIO1_19/ ACMPV REF-H1358[4]ZO7 PLU_OUT1- PLU output 1. 8 R- Reserved.
PIO1_20-C24[2]ZI/O0 PIO1_20- General-purpose digital input/output pin.
PIO1_20-C24[2]Z2 R- Reserved. input
PIO1_20-C24[2]ZI3 CTIMER_INP14- Capture input to CTIMER multiplexers.
PIO1_20-C24[2]ZI/O5 FC4_TXD_SCL_MISO_WS- Flexcomm 4: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S
PIO1_20-C24[2]Zword-select/frame. 6 R- Reserved.
PIO1_20-C24[2]ZO7 PLU_OUT2- PLU output 2.
PIO1_20-C24[2]Z

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO1_21-M730[2]ZI/O0 PIO1_21- General-purpose digital input/output pin.
PIO1_21-M730[2]ZI/O1 FC7_CTS_SDA_SSEL0- Flexcomm 7: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO1_21-M730[2]Z2 R- Reserved.
PIO1_21-M730[2]ZO3 CTIMER3_MAT2- 32-bit CTimer3 match output 2.
PIO1_21-M730[2]Z4 R- Reserved.
PIO1_21-M730[2]ZI/O5 FC4_RXD_SDA_MOSI_DATA- Flexcomm 4: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO1_21-M730[2]Z6 R- Reserved.
PIO1_21-M730[2]ZO7 PLU_OUT3- PLU output 3.
PIO1_22-M841[2]ZI/O0 PIO1_22- General-purpose digital input/output pin.
PIO1_22-M841[2]Z1 R- Reserved.
PIO1_22-M841[2]ZI/O2 SD0_CMD- SD/MMC 0 card command I/O.
PIO1_22-M841[2]ZO3 CTIMER2_MAT3- 32-bit CTimer2 match output 3.
PIO1_22-M841[2]ZI4 SCT0_GPI5- Pin input 5 to SCTimer/PWM.
PIO1_22-M841[2]ZI/O5 FC4_SSEL3- Flexcomm 4: SPI slave select 3.
PIO1_22-M841[2]Z6 R- Reserved.
PIO1_23-J842[2]ZI/O0 PIO1_23- General-purpose digital input/output pin.
PIO1_23-J842[2]ZI/O1 FC2_SCK- Flexcomm 2: USART, SPI, or I2S clock.
PIO1_23-J842[2]ZO2 SCT0_OUT0- SCTimer/PWM output 0.
PIO1_23-J842[2]ZI/O3 SD1_D[3]- SD/MMC 1 data 3.
PIO1_23-J842[2]Z4 R- Reserved.
PIO1_23-J842[2]ZI/O5 FC3_SSEL2- Flexcomm 3: SPI slave select 2.
PIO1_23-J842[2]Z6 R- Reserved.
PIO1_23-J842[2]Z8 R- Reserved.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO1_24-F63[2]ZI/O0 PIO1_24- General-purpose digital input/output pin.
PIO1_24-F63[2]ZI/O1 FC2_RXD_SDA_MOSI_DATA- Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO1_24-F63[2]ZO2 SCT0_OUT1- SCTimer/PWM output 1.
PIO1_24-F63[2]ZI/O3 SD1_D[1]- SD/MMC 1 data 1.
PIO1_24-F63[2]Z4 R- Reserved.
PIO1_24-F63[2]ZI/O5 FC3_SSEL3- Flexcomm 3: SPI slave select 3.
PIO1_24-F63[2]Z6 R- Reserved.
PIO1_24-F63[2]ZO7 PLU_OUT6- PLU output 6.
PIO1_24-F63[2]Z8 R- Reserved.
PIO1_25-B877[2]ZI/O0 PIO1_25- General-purpose digital input/output pin.
PIO1_25-B877[2]ZI/O1 FC2_TXD_SCL_MISO_WS- Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO1_25-B877[2]ZO2 SCT0_OUT2- SCTimer/PWM output 2.
PIO1_25-B877[2]ZI/O3 SD1_D[0]- SD/MMC 1 data 0.
PIO1_25-B877[2]ZI4 UTICK_CAP0- Micro-tick timer capture input 0.
PIO1_25-B877[2]Z5 R- Reserved.
PIO1_25-B877[2]Z6 R- Reserved.
PIO1_25-B877[2]ZI7 PLU_CLKIN- PLU clock input.
PIO1_26-E1368[2]ZI/O0 PIO1_26- General-purpose digital input/output pin.
PIO1_26-E1368[2]ZI/O1 FC2_CTS_SDA_SSEL0- Flexcomm 2: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
PIO1_26-E1368[2]ZO2 SCT0_OUT3- SCTimer/PWM output 3.
PIO1_26-E1368[2]ZI3 CTIMER_INP3- Capture input to CTIMER input multiplexers.
PIO1_26-E1368[2]ZI4 UTICK_CAP1- Micro-tick timer capture input 1.
PIO1_26-E1368[2]ZI/O5 HS_SPI_SSEL3- Slave Select 3 for high speed SPI.
PIO1_26-E1368[2]Z6 R- Reserved.
PIO1_26-E1368[2]ZI7 PLU_INPUT5- PLU input 5. 8 R- Reserved.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction # Description
PIO1_27-E885[2]ZI/O0 PIO1_27- General-purpose digital input/output pin.
PIO1_27-E885[2]ZI/O1 FC2_RTS_SCL_SSEL1- Flexcomm 2: USART request-to-send, I2C clock, SPI slave select 1.
PIO1_27-E885[2]ZI/O2 SD0_D[4]- SD/MMC 0 data 4.
PIO1_27-E885[2]ZO3 CTIMER0_MAT3- 32-bit CTimer0 match output 3.
PIO1_27-E885[2]ZO4 CLKOUT- Output of the CLKOUT function.
PIO1_27-E885[2]Z5 R- Reserved.
PIO1_27-E885[2]Z6 R- Reserved.
PIO1_27-E885[2]ZI7 PLU_INPUT4- PLU input 4.
PIO1_27-E885[2]Z8 R- Reserved.
PIO1_28-A873[2]ZI/O0 PIO1_28- General-purpose digital input/output pin.
PIO1_28-A873[2]ZI/O1 FC7_SCK- Flexcomm 7: USART, SPI, or I2S clock.
PIO1_28-A873[2]ZI/O2 SD0_D[5]- SD/MMC 0 data 5.
PIO1_28-A873[2]ZI3 CTIMER_INP2- Capture input to CTIMER input multiplexers.
PIO1_28-A873[2]Z4 R- Reserved.
PIO1_28-A873[2]Z5 R- Reserved.
PIO1_28-A873[2]Z6 R- Reserved.
PIO1_28-A873[2]ZI7 PLU_INPUT3- PLU input 3.
PIO1_28-A873[2]Z8 R- Reserved.
PIO1_29-G880[2][8]ZI/O0 PIO1_29- General-purpose digital input/output pin.
PIO1_29-G880[2][8]ZI/O1 FC7_RXD_SDA_MOSI_DATA- Flexcomm 7: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O.
PIO1_29-G880[2][8]ZI/O2 SD0_D[6]- SD/MMC 0 data 6.
PIO1_29-G880[2][8]ZI3 SCT0_GPI6- Pin input 6 to SCTimer/PWM.
PIO1_29-G880[2][8]ZO4 USB1_PORTPWRN- USB1 VBUS drive indicator (Indicates VBUS must be driven).
PIO1_29-G880[2][8]ZO5 USB1_FRAME- USB1 frame toggle signal.
PIO1_29-G880[2][8]Z6 R- Reserved.
PIO1_29-G880[2][8]ZI7 PLU_INPUT2- PLU input 2.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeFunction #Description
PIO1_30/ WAKEUP-F965[2][8]ZI/O0PIO1_30- General-purpose digital input/output pin. This pin can trigger a wake-up from deep power-down mode. WAKEUP pin can be configured as rising or falling edge.
PIO1_30/ WAKEUP-F965[2][8]ZI/O1FC7_TXD_SCL_MISO_WS- Flexcomm 7: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame.
PIO1_30/ WAKEUP-F965[2][8]ZI/O2SD0_D[7]- SD/MMC 0 data 7.
PIO1_30/ WAKEUP-F965[2][8]ZI3SCT0_GPI7- Pin input 7 to SCTimer/PWM.
PIO1_30/ WAKEUP-F965[2][8]ZI4USB1_OVERCURRENTN- USB1 bus overcurrent indicator (active low).
PIO1_30/ WAKEUP-F965[2][8]ZO5USB1_LEDN- USB1-configured LED indicator (active low).
PIO1_30/ WAKEUP-F965[2][8]Z6R- Reserved.
PIO1_31-H691[2]ZI/O0PIO1_31- General-purpose digital input/output pin.
PIO1_31-H691[2]ZI/O1MCLK- MCLK input or output for I2S.
PIO1_31-H691[2]ZO2SD1_CLK- SD/MMC 1 card clock.
PIO1_31-H691[2]ZO3CTIMER0_MAT2- 32-bit CTimer0 match output 2.
PIO1_31-H691[2]ZO4SCT0_OUT6- SCTimer/PWM output 6.
PIO1_31-H691[2]Z5 6R- Reserved. R- Reserved.
PIO1_31-H691[2]ZIPLU
PIO1_31-H691[2]Z7PLU_INPUT0- input 0.
PIO1_31-H691[2]Z8R- Reserved.
FB29 N945--Feedback node (regulated output) of DCDC converter.
LX31 N1148--DCDC converter power stage output.
RESETN21 J632[5]-IExternal reset input:ALOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and the boot code to execute. Wakes up the part from deep power-down mode.
USB0_3V361A396--USB0 analog 3.3 V supply.
USB0_DM63A198[6][8]I/OUSB0 bidirectional D- line.
USB0_DP62A297[6][8]I/OUSB0 bidirectional D+ line.
USB0_VSS64B199USB0 analog 3.3 V ground.
USB1_DM24N635[6][8]I/OUSB1 bidirectional D- line.
USB1_DP23 USB1_VBUSM634[6][8]I/OUSB1 bidirectional D+ line.
27N738[10]VBUS pin (power on USB cable).
USB1_3V325N836[6][8]-I -USB1 analog 3.3 V supply.
USB1_VSS22;26 N533; 37--USB1 analog 3.3 V ground.

Table 3. Pin description …continued

Table 3. Pin description …continued

Symbol64 pin HTQFP98 pin VFBGA100 pin HLQFPReset state [1]TypeDescription
VBAT_DCDC32N1349, 50[9]--Supply of DCDC output stage. DCDC core supply (references and regulation stages).
VBAT_ PMU33M1351[9]--Analog supply.
VDD8; 16; 43; 54M1; A5; A9; A1315; 25; 44; 63; 69;75; 84; 95; 100--Single 1.8 V to 3.6 V power supply powers I/Os.
VDD_PMU28M939--Core supply. For applications with DCDC converter, VDD_PMU and FB are tied at PCB level.
VDDA9G216--Analog supply voltage. At PCB level, has to be tied to main supply (VBAT_PMU, VBAT_DCDC)
VREFN-H118--ADC negative reference voltage.
VREFP10G117--ADC positive reference voltage.
VSSexposed padN1;B5; B9; B13exposed pad--Ground.
VSS_DCDC30N12, M1246, 47--Star ground connection is managed to PCB ground plane.
VSS_PMU-M11---Star ground connection is managed to PCB ground plane.
VSSA11H219--Analog ground.
XTAL32K_N35J1253[12]--RTC oscillator output.
XTAL32K_P34J1352[12]--RTC oscillator input.
XTAL32M_N19M328[7]--Main oscillator output. For USB HS ISP mode, 16 MHz crystal is required.
XTAL32M_P20N329[7]--Main oscillator input. For USB HS ISP mode, 16 MHz crystal is required.
  • [3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
  • [4] Pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled.

[5] Reset pad with glitch filter and hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to 20 ns (simulated value)

[6] Transparent analog pad.

[7] Optional bypass mode is supported, xtal32M_P can be driven by an external clock with restrictions in terms of drive level. See: Section 13 'Application information'.

  • [8] The corresponding VBUS must be connected to supply voltage when using the USB peripheral. USB0_VBUS is not 5 V tolerant pin. USB1_VBUS is 5 V tolerant pin.
  • [9] Main battery supply: Star connection at application level (PCB).
  • [10] If the USB1_3V3 pin is not using the same supply as the VBAT_PMU pin, the application should ensure the supply on USB1_3V3 does not drop below 2.8 V. If the USB1_3V3 pin is using separate supply and this voltage unexpectedly drops below 2.8 V, the USB PHY can go into unknown state causing USB transactions (R/W) to hang. In this case, the application can detect this event with a time-out and would have to recover by performing a USB reset..
  • [11] The JTAG functions TRST, TCK, TMS, TDI, and TDO are selected by hardware when the part is in boundary scan mode. The JTAG functions cannot be used for debug mode.
  • [12] Optional bypass mode is supported, xtal32K_P can be driven by an external clock with restrictions in terms of drive level See: Section 13 'Application information'.

Electrical Characteristics

Table 38. 16-bit ADC static characteristics

Tamb = 40 C to +105 C; VDDA = 1.8 V to 3.6 V; ADC calibrated at T = 25 C.

SymbolParameterConditionsMin [2]Typ [2]Max [2]Unit
V IAanalog input voltage0-V DDAV
CADINinput capacitance-45pF
f clk(ADC)ADC clock frequency[11]-24MHz
f ssampling frequency--1.0Msamples/s
E Ddifferential linearity error16-bit differential mode, CTYPE = 2[1][2][3][4][5]-0.99-2.6LSB
E Ddifferential linearity error16-bit single ended mode, CTYPE = 1[1][2][3][4][5]-1+9.5LSB
E L(adj)integral non-linearity16-bit differential mode, CTYPE = 2[1][2][3][4][6]-16-+16LSB
E L(adj)integral non-linearity16-bit single ended mode, CTYPE = 1[1][2][3][4][6]-12-+12LSB
E Ooffset erroruncalibrated[1][7]-2.3-mV
V err(FS)full-scale error voltageuncalibrated[1][8]-24-LSB
ENOB[L:] Effective number of bits16-bit differential mode, CTYPE = 2[9]-12.6-bits
ENOB[L:] Effective number of bits16-bit single ended mode, CTYPE = 1[9]-12.0-bits
THD[L:] Total Harmonic Distortion16-bit differential mode, CTYPE = 2[9]--85-dB
THD[L:] Total Harmonic Distortion16-bit single endedmode, CTYPE = 1[9]--85-dB
SFDR[L:] Spurious Free Dynamic Range16-bit differential mode, CTYPE = 2[9]-86-dB
SFDR[L:] Spurious Free Dynamic Range16-bit single ended mode, CTYPE = 1[9]-82-dB
tADCSTUPAnalog startup timeWait time after setting ADC_CTRL[ADCEN] [10][10]-5-us
  • [3] fclk(ADC) = 24 MHz, STS = 3, Power select = 1, Average setting = 1, fs = 1 Msample/s

[4] Differential linear results assume offset 0.2% from VREFL and 0.2% from VREFH

  • [5] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

[6] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors.

[7] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve.

  • [8] The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve.
  • [9] Input data is 1kHz sine wave, ADC conversion clock 24 MHz, Power Select = 3, Average setting = 4.
  • [10] Value of ADC_CFG[PUDLY] * 4 * ADCclk must be > tADCSTUP.
  • [11] To use temperature sensor, the maximum fclk(ADC) frequency is 6 MHz.

Thermal Information

The average chip junction temperature, Tj ( C), can be calculated using the following equation:

  • Tamb = ambient temperature ( C),
  • Rth(j-a) = the package junction-to-ambient thermal resistance ( C/W)
  • PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.

Table 12. Thermal resistance

SymbolParameterConditionsMax/MinUnit
HLQFP100 PackageHLQFP100 PackageHLQFP100 PackageHLQFP100 PackageHLQFP100 Package
R th(j-a)thermal resistance from junction to ambient [1]JESD51-9, 2s2p [2]27C/W
R th(j-c)thermal resistance from junction to case [3]JESD51-9 [2]2.0C/W
VFBGA98 PackageVFBGA98 PackageVFBGA98 PackageVFBGA98 PackageVFBGA98 Package
R th(j-a)thermal resistance from junction to ambient [1]JESD51-9, 2s2p [2]56C/W
R th(j-c)Junction-to-Top of Package Thermal Characterization Parameter [3]JESD51-9 [2]0.7C/W
HTQFP 64 PackageHTQFP 64 PackageHTQFP 64 PackageHTQFP 64 PackageHTQFP 64 Package
R th(j-a)thermal resistance from junction to ambient [1]JESD51-9, 2s2p [2]28C/W
R th(j-c)thermal resistance from junction to case [3]JESD51-9 [2]0.3C/W

Table 13. Maximum Junction Temperature

SymbolParameterConditionsMaxUnit
T jmaxmaximum junction temperature+ 107C

Package Information

Table 42. USB1 High-speed VBUS threshold levels

Fig 28. HTQFP64 Package outline 2

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
LPC55S66NXP Semiconductors—
LPC55S69JBD100NXP SemiconductorsHLQFP100
LPC55S69JBD64NXP Semiconductors—
LPC55S69JEV98NXP Semiconductors—
LPC55S6XNXP Semiconductors—
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