LPC1766FBD100

Part: LPC176x/5x — NXP Type: ARM Cortex-M3 Microcontroller Description: ARM Cortex-M3 based microcontroller with CPU frequencies up to 120 MHz, up to 512 kB Flash, up to 64 kB SRAM, Ethernet MAC, USB Host/Device/OTG, CAN, SSP, SPI, I2C, I2S, 12-bit ADC, 10-bit DAC, and a wide range of other peripherals.

Operating Conditions:

• Supply voltage: 2.4 V to 3.6 V
• Operating temperature: -40 °C to 85 °C
• Max CPU frequency: 120 MHz (high speed versions), 100 MHz (other versions)

Absolute Maximum Ratings:

Key Specs:

• CPU: ARM Cortex-M3
• Max CPU frequency: 120 MHz (LPC1769, LPC1759), 100 MHz (other versions)
• Flash memory: Up to 512 kB
• SRAM: Up to 64 kB
• ADC resolution: 12-bit
• DAC resolution: 10-bit
• GPIO pins: Up to 70 (100-pin package), 52 (80-pin package)
• Internal RC oscillator accuracy: 1%
• Crystal oscillator range: 1 MHz to 25 MHz

Features:

• Memory Protection Unit (MPU) supporting eight regions
• Nested Vectored Interrupt Controller (NVIC)
• In-System Programming (ISP) and In-Application Programming (IAP)
• Eight channel General Purpose DMA controller (GPDMA)
• Multilayer AHB matrix interconnect
• Ethernet MAC with RMII interface and dedicated DMA controller
• USB 2.0 full-speed controller (Device, Host, or OTG) with on-chip PHY
• Four UARTs with fractional baud rate generation, FIFO, IrDA, and DMA support
• Two-channel CAN controller
• Two SSP controllers with FIFO and multi-protocol capabilities
• SPI controller
• Three enhanced I2C-bus interfaces
• I2S (Inter-IC Sound) interface for digital audio
• Four general purpose timers/counters
• One motor control PWM
• Quadrature encoder interface
• Real-Time Clock (RTC) with separate power domain and battery-powered backup registers
• Watchdog Timer (WDT)
• Cortex-M3 system tick timer
• Repetitive interrupt timer
• JTAG, Serial Wire Debug, and Serial Wire Trace Port options
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down
• Brownout detect
• On-chip Power-On Reset (POR)
• On-chip crystal oscillator and 4 MHz internal RC oscillator
• Two on-chip PLLs (one for CPU, one for USB)
• Wake-up Interrupt Controller (WIC)

Applications:

• eMetering
• Lighting
• Industrial networking
• Alarm systems
• White goods
• Motor control

Package:

• LQFP100 (14 mm x 14 mm x 1.4 mm)
• TFBGA100 (9 mm x 9 mm x 0.7 mm)
• WLCSP100 (5.074 x 5.074 x 0.6 mm)
• LQFP80 (12 mm x 12 mm x 1.4 mm)

Refer to Section 1.4.1 for details of features on specific part numbers.

• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included.
• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash.
• Up to 64 kB on-chip SRAM includes:
• -Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
• -Up to two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose instruction and data storage.
• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I 2 S, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers.
• Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.
• Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.
• Serial interfaces:
• -Ethernet MAC with RMII interface and dedicated DMA controller.
• -USB 2.0 full-speed controller that can be configured for either device, Host, or OTG operation with an on-chip PHY for device and Host functions and a dedicated DMA controller.
• -Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support.
• -Two-channel CAN controller.
• -Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
• -SPI controller with synchronous, serial, full duplex communication and programmable data length. SPI is included as a legacy peripheral and can be used instead of SSP0.
• -Three enhanced I 2 C-bus interfaces, one with an open-drain output supporting the full I 2 C specification and Fast mode plus with data rates of 1Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.

• -I 2 S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I 2 S interface can be used with the GPDMA. The I 2 S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output.

• eMetering
• Lighting
• Industrial networking
• Alarm systems
• White goods
• Motor control

Table 6 shows pins that are associated with System Control block functions.

Table 6. Pin summary

Rev. 4. 1 - 19 December 2016

User manual