LMK04828BISQ/NOPB

Part: LMK0482x

Type: Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

Key Specs:

• RMS Jitter (12 kHz to 20 MHz): 88 fs
• Noise Floor at 245.76 MHz: –162.5 dBc/Hz
• Normalized [1 Hz] PLL Noise Floor: -227 dBc/Hz
• Maximum Clock Output Frequency: 3.1 GHz
• RMS Jitter (100 Hz to 20 MHz): 91 fs
• Operation Voltage: 3.15-V to 3.45-V
• Industrial Temperature Range: –40 to 85°C
• Supported PCB Temperature (Measured at Thermal Pad): 105°C

Features:

• JEDEC JESD204B Support
• Up to 14 Differential Device Clocks from PLL2
• Up to 7 SYSREF Clocks
• LVPECL, LVDS, HSDS, LCPECL JESD204B support
• Programmable Outputs from PLL2
• Precision Digital Delay, Dynamically Adjustable
• 25 ps Step Analog Delay
• Multi-mode: Dual PLL, single PLL, and Clock Distribution
• Ultra-Low RMS Jitter
• Up to 1 Buffered VCXO/Crystal Output from PLL1
• Dual Loop PLLatinum™ PLL Architecture
• Up to 3 Redundant Input Clocks (PLL1)
• Automatic and Manual Switch-Over Modes (PLL1)
• Hitless Switching and LOS ability (PLL1)
• Integrated Low-Noise Crystal Oscillator Circuit (PLL1)
• Holdover mode when Input Clocks are Lost (PLL1)

Applications:

• Wireless Infrastructure
• Networking, SONET/SDH, DSLAM
• Test and Measurement
• Data Converter Clocking
• Medical / Video / Military / Aerospace

Package:

• 64-Pin QFN: 9.0 mm x 9.0 mm x 0.8 mm

Tools & Software

• Ultra-Low RMS Jitter Data Converter Clocking

  • 91 fs RMS Jitter (100 Hz to 20 MHz) Medical / Video / Military / Aerospace

The LMK0482x family is the industry's highest – Maximum Clock Output Frequency 3.1 GHz performance clock conditioner with JEDEC

Programmable Outputs from PLL2 The ¹⁴ clock outputs from PLL2 can be configured to • Up to 1 Buffered VCXO/Crystal Output from PLL1 drive seven JESD204B converters or other logic – LVPECL, LVDS, 2xLVCMOS Programmable devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not • Dual Loop PLLatinum™ PLL Architecture limited to JESD204B applications, each of the 14 • PLL1 outputs can be individually configured as high – Up to 3 Redundant Input Clocks performance outputs for traditional clocking systems.

– Automatic and Manual Switch-Over Modes The high performance combined with features like the – Hitless Switching and LOS ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and – Integrated Low-Noise Crystal Oscillator Circuit glitchless analog delay make the LMK0482x family – Holdover mode when Input Clocks are Lost ideal for providing flexible high performance clocking

Tools & Software

• Ultra-Low RMS Jitter Data Converter Clocking

  • 91 fs RMS Jitter (100 Hz to 20 MHz) Medical / Video / Military / Aerospace

The LMK0482x family is the industry's highest – Maximum Clock Output Frequency 3.1 GHz performance clock conditioner with JEDEC

Programmable Outputs from PLL2 The ¹⁴ clock outputs from PLL2 can be configured to • Up to 1 Buffered VCXO/Crystal Output from PLL1 drive seven JESD204B converters or other logic – LVPECL, LVDS, 2xLVCMOS Programmable devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not • Dual Loop PLLatinum™ PLL Architecture limited to JESD204B applications, each of the 14 • PLL1 outputs can be individually configured as high – Up to 3 Redundant Input Clocks performance outputs for traditional clocking systems.

– Automatic and Manual Switch-Over Modes The high performance combined with features like the – Hitless Switching and LOS ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and – Integrated Low-Noise Crystal Oscillator Circuit glitchless analog delay make the LMK0482x family – Holdover mode when Input Clocks are Lost ideal for providing flexible high performance clocking

Pin Functions

• NO.
• 1, 2
• 3, 4
• 5
• 6
• 7, 8, 9
• 10
• 11
• 12
• 13, 14
• 15, 16
• 17
• 18
• 19

(1) See Pin Connection Recommendations for recommended connections.

(3.15 V < VCC < 3.45 V, –40 °C < T^A < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, T^A = 25 °C, at the Recommended Operating Conditions and are not assured.)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
ICC_PD	Power Down Supply Current			1	3	mA
ICC_CLKS	Supply Current(1)	14 HSDS 8 mA clocks enabled PLL1 and PLL2 locked.		565	665	mA
CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS

(2) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

• (3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
• (4) Assured by characterization. ATE tested at 2949.12 MHz.

(3.15 V < VCC < 3.45 V, –40 °C < T^A < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, T^A = 25 °C, at the Recommended Operating Conditions and are not assured.)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VFBCLKin/Fin	Single Ended Clock Input Voltage	AC coupled CLKinX_TYPE = 0 (Bipolar)	0.25		2.0	Vpp
SLEWFBCLKin/Fin	Slew Rate on CLKin (2)	AC coupled; 20% to 80%; (CLKinX_TYPE = 0)	0.15	0.5		V/ns
PLL1 SPECIFICATIONS
fPD1	PLL1 Phase Detector Frequency PLL1 Charge	VCPout1 = VCC/2, PLL1_CP_GAIN = 0 VCPout1 = VCC/2, PLL1_CP_GAIN = 1 VCPout1 = VCC/2, PLL1_CP_GAIN = 2		50 150 250	40	MHz
ICPout1SOURCE	Pump Source Current (5) PLL1 Charge	… VCPout1 = VCC/2, PLL1_CP_GAIN = 14 VCPout1 = VCC/2, PLL1_CP_GAIN = 15 VCPout1=VCC/2, PLL1_CP_GAIN = 0 VCPout1=VCC/2, PLL1_CP_GAIN = 1 VCPout1=VCC/2, PLL1_CP_GAIN = 2		… 1450 1550 –50 –150 –250		μA
ICPout1SINK	Pump Sink Current (5)	… VCPout1=VCC/2, PLL1_CP_GAIN = 14 VCPout1=VCC/2, PLL1_CP_GAIN = 15		… –1450 –1550		μA
ICPout1%MIS	Charge Pump Sink / Source Mismatch	VCPout1 = VCC/2, T = 25 °C		1%	10%
ICPout1VTUNE	Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage	0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C		4%
ICPout1%TEMP	Charge Pump Current vs. Temperature Variation			4%
ICPout1 TRI	Charge Pump TRI-STATE Leakage Current PLL 1/f Noise at 10 kHz offset.	0.5 V < VCPout < VCC - 0.5 V PLL1_CP_GAIN = 350 μA		–117	5	nA
PN10kHz	Normalized to 1 GHz Output Frequency	PLL1_CP_GAIN = 1550 μA		–118		dBc/Hz
PN1Hz	Normalized Phase Noise Contribution	PLL1_CP_GAIN = 350 μA PLL1_CP_GAIN = 1550 μA		–221.5 –223		dBc/Hz
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin	PLL2 Reference Input (6)				500	MHz
SLEWOSCin	PLL2 Reference Clock minimum slew rate on OSCin (2)	20% to 80%	0.15	0.5		V/ns
VOSCin	Input Voltage for OSCin or OSCin*	AC coupled; Single-ended (Unused pin AC coupled to GND)	0.2		2.4	Vpp
VIDOSCin	Differential voltage swing		0.2		1.55	V
V SSOSCin	Figure 8	AC coupled	0.4		3.1	Vpp
VOSCin-offset	DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX)	Each pin AC coupled		20		mV
fdoubler_max	Doubler input frequency (7)	(8); EN_PLL2_REF_2X = 1 OSCin Duty Cycle 40% to 60%			155	MHz

(6) FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.

(7) Assured by characterization. ATE tested at 122.88 MHz.

(8) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.

(3.15 V < VCC < 3.45 V, –40 °C < T^A < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, T^A = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
FXTAL	Crystal Frequency Range	Fundamental mode crystal ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz)	10		40	MHz
CIN	Input Capacitance of OSCin port PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	–40 to 85 °C		1		pF
fPD2	Phase Detector Frequency (7)	VCPout2=VCC/2, PLL2_CP_GAIN = 0		100	155	MHz
	PLL2 Charge Pump Source Current	VCPout2=VCC/2, PLL2_CP_GAIN = 1		400		μA
ICPoutSOURCE	(5) PLL2 Charge Pump Sink Current (5)	VCPout2=VCC/2, PLL2_CP_GAIN = 2 VCPout2=VCC/2, PLL2_CP_GAIN = 3 VCPout2=VCC/2, PLL2_CP_GAIN = 0 VCPout2=VCC/2, PLL2_CP_GAIN = 1		1600 3200 –100 –400
ICPoutSINK		VCPout2=VCC/2, PLL2_CP_GAIN = 2 VCPout2=VCC/2, PLL2_CP_GAIN = 3		–1600 –3200		μA
ICPout2%MIS	Charge Pump Sink/Source Mismatch	VCPout2=VCC/2, TA = 25 °C		1%	10%
ICPout2VTUNE	Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation	0.5 V < VCPout2 < VCC - 0.5 V TA = 25 °C		4%
ICPout2%TEMP	Charge Pump Current vs. Temperature Variation			4%
ICPout2TRI	Charge Pump Leakage	0.5 V < VCPout2 < VCC - 0.5 V			10	nA
PN10kHz	PLL 1/f Noise at 10 kHz offset (9) Normalized to 1 GHz Output Frequency	PLL2_CP_GAIN = 400 μA PLL2_CP_GAIN = 3200 μA		–118 –121		dBc/Hz
PN1Hz	Normalized Phase Noise Contribution (10)	PLL2_CP_GAIN = 400 μA PLL2_CP_GAIN = 3200 μA		–222.5 –227		dBc/Hz

(10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).

(3.15 V < VCC < 3.45 V, –40 °C < T^A < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, T^A = 25 °C, at the Recommended Operating Conditions and are not assured.)

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
INTERNAL VCO SPECIFICATIONS
fVCO	LMK04821 VCO Tuning Range	VCO0	1930	2075	MHz
		VCO1(11)	2920	3080	MHz
		VCO0	1840	1970	MHz
	LMK04826 VCO Tuning Range	VCO1	2440	2505	MHz
	LMK04828 VCO Tuning Range	VCO0	2370	2630	MHz
		VCO1	2920	3080	MHz
	LMK04821 Fine Tuning Sensitivity	LMK04821 VCO0	12 to 20		MHz/V
		LMK04821 VCO1	15 to 24		MHz/V
	LMK04826 Fine Tuning Sensitivity	LMK04826 VCO0	11 to 19		MHz/V
KVCO		LMK04826 VCO1	8 to 11		MHz/V
	LMK04828 Fine Tuning Sensitivity	LMK04828 VCO0 at 2457.6 MHz	17 to 27		MHz/V
		LMK04828 VCO1 at 2949.12 MHz	17 to 23		MHz/V
ΔTCL	Allowable Temperature Drift for Continuous Lock (12)	After programming for lock, no changes to output configuration are permitted to assure continuous lock		125	°C

(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40 °C to 85 °C without violating specifications.

over operating free-air temperature range (unless otherwise noted) (1)

		MIN	MAX	UNIT
VCC	Supply voltage (2)	–0.3	3.6	V
VIN	Input voltage	–0.3	(VCC + 0.3)	V
TL	Lead temperature (solder 4 seconds)		260	°C
TJ	Junction temperature		150	°C
IIN	Differential input current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*)		± 5	mA
MSL	Moisture sensitivity level		3
Tstg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Never to exceed 3.6 V.

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
TJ	Junction Temperature			125	°C
TA	Ambient Temperature	-40	25	85	°C
TPCB	PCB Temperature (measured at thermal pad)			105	°C
VCC	Supply Voltage	3.15	3.3	3.45	V

	THERMAL METRIC(1)	LMK0482x	UNIT
		NKD (WQFN)
		64 PINS
RθJA	Junction-to-ambient thermal resistance(2)	24.3	°C/W
RθJC(top)	Junction-to-case (top) thermal resistance(3)	6.1	°C/W
RθJB	Junction-to-board thermal resistance(4)	3.5	°C/W

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

⁽³⁾ The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

⁽⁴⁾ The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.