LM5166DRCT.A
TEXAS INSTRUMENTS
Manufacturer
Texas Instruments
Overview
Part: LM5166 from Texas Instruments
Type: Synchronous Buck Converter
Key Specs:
- Input Voltage Range: 3 V to 65 V
- Output Current: up to 500 mA
- No-Load Quiescent Current: 9.7 μA
- Junction Temperature Range: –40°C to 150°C
- Switching Frequency: up to 600 kHz
- Internal Voltage Reference: 1.223 V ±1.2%
Features:
- Fixed (3.3-V, 5-V) or Adjustable VOUT Options
- Meets EN55022 / CISPR 22 EMI Standards
- Integrated 1-Ω PFET Buck Switch (Supports 100% Duty Cycle for Low Dropout)
- Integrated 0.5-Ω NFET Synchronous Rectifier (Eliminates External Schottky Diode)
- Programmable Peak Current Limit Supports: 500-mA, 300-mA, or 200-mA Loads
- Selectable PFM or COT Mode Operation
- 900-μs Internal or Externally-Adjustable Soft Start
- Diode Emulation and Pulse Skipping for Ultra-High Light-Load Efficiency
- No Loop Compensation or Bootstrap Components
- Precision Enable and Input UVLO With Hysteresis
- Open-Drain Power Good Indicator
- Thermal Shutdown Protection With Hysteresis
- Pin-to-Pin Compatible With the LM5165
- Create a Custom Regulator Design Using WEBENCH® Power Designer
Applications:
- Factory and Building Automation
- Automotive and Battery-Powered Applications
- High Voltage LDO Replacement
- Low Power Bias Supplies
Package:
- VSON (10-Pin): 3-mm × 3-mm
Features
- 1 Wide Input Voltage Range of 3 V to 65 V
- 9.7-μA No-Load Quiescent Current
- –40°C to 150°C Junction Temperature Range
- Fixed (3.3-V, 5-V) or Adjustable VOUT Options
- Meets EN55022 / CISPR 22 EMI Standards
- Integrated 1-Ω PFET Buck Switch
- Supports 100% Duty Cycle for Low Dropout
- Integrated 0.5-Ω NFET Synchronous Rectifier
- Eliminates External Schottky Diode
- Programmable Peak Current Limit Supports:
- 500-mA, 300-mA, or 200-mA Loads
- Selectable PFM or COT Mode Operation
- 1.223-V ±1.2% Internal Voltage Reference
- Switching Frequency up to 600 kHz
- 900-μs Internal or Externally-Adjustable Soft Start
- Diode Emulation and Pulse Skipping for Ultra-High Light-Load Efficiency
- No Loop Compensation or Bootstrap Components
- Precision Enable and Input UVLO With Hysteresis
- Open-Drain Power Good Indicator
- Thermal Shutdown Protection With Hysteresis
- Pin-to-Pin Compatible With the LM5165
- 10-Pin, 3-mm × 3-mm VSON Package
- • Create a Custom Regulator Design Using WEBENCH® Power Designer
Applications
- Factory and Building Automation
- • Automotive and Battery-Powered Applications
- High Voltage LDO Replacement
- Low Power Bias Supplies
3 Description
The LM5166 is a compact, easy-to-use, 3-V to 65-V, ultra-low IQ synchronous buck converter with high efficiency over wide input voltage and load current ranges. With integrated high-side and low-side power MOSFETs, up to 500 mA of output current can be delivered at fixed output voltages of 3.3 V or 5 V, or an adjustable output. The converter is designed to simplify implementation while providing options to optimize the performance for the target application. Pulse frequency modulation (PFM) mode is selected for optimal light-load efficiency or constant on-time (COT) control for nearly constant operating frequency. Both control schemes do not require loop compensation while providing excellent line and load transient response and short PWM on-time for large step-down conversion ratios.
The high-side P-channel MOSFET can operate at 100% duty cycle for lowest dropout voltage and does not require a bootstrap capacitor for gate drive. Also, the current limit setpoint is adjustable to optimize inductor selection for a particular load current requirement. Selectable and adjustable start-up timing options include minimum delay (no soft start), internally fixed (900 μs), and externally programmable soft start using a capacitor. An open-drain PGOOD indicator can be used for sequencing, fault reporting, and output voltage monitoring. The LM5166 is available in a 10-pin VSON package with 0.5-mm pin pitch.
Device Information(1)
| PART NUMBER | OUTPUT | PACKAGE |
|---|---|---|
| LM5166 | Adjustable | |
| LM5166X | 5-V fixed | VSON (10) |
| LM5166Y | 3.3-V fixed |
Typical COT Mode Application Typical COT Mode Application Efficiency
Table of Contents
| 1 | Features 1 | 7.4 Device Functional Modes 25 | |
|---|---|---|---|
| 2 | Applications 1 | 8 | Applications and Implementation 26 |
| 3 | Description 1 | 8.1 Application Information 26 | |
| 4 | Revision History 2 | 8.2 Typical Applications 26 | |
| 5 | Pin Configuration and Functions 3 | 9 | Power Supply Recommendations 44 |
| 6 | Specifications 4 | 10 | Layout 44 |
| 6.1 Absolute Maximum Ratings 4 | 10.1 Layout Guidelines 44 | ||
| 6.2 ESD Ratings 4 | 10.2 Layout Example 46 | ||
| 6.3 Recommended Operating Conditions 4 | 11 | Device and Documentation Support 47 | |
| 6.4 Thermal Information 4 | 11.1 Device Support 47 | ||
| 6.5 Electrical Characteristics 5 | 11.2 Documentation Support 47 | ||
| 6.6 Switching Characteristics 6 | 11.3 Receiving Notification of Documentation Updates 48 | ||
| 6.7 Typical Characteristics 7 | 11.4 Community Resources 48 | ||
| 7 | Detailed Description 14 | 11.5 Trademarks 48 | |
| 7.1 Overview 14 | 11.6 Electrostatic Discharge Caution 48 | ||
| 7.2 Functional Block Diagram 14 | 11.7 Glossary 48 | ||
| 7.3 Feature Description 15 | 12 | Mechanical, Packaging, and Orderable Information 48 |
4 Revision History
| Changes from Revision A (December 2016) to Revision B | Page | |
|---|---|---|
| • | Updated data sheet text to the latest TI documentation and translations standards 1 | |
| • | Changed the language of WEBENCH list item; added additional content and links for WEBENCH in data sheet 1 | |
| • | Added LM5166X and LM5166Y output versions to the data sheet 1 | |
| • | Replaced the body size (NOM) column with output versions in the Device Information table 1 | |
| • | Changed the Typical COT Mode Application circuit to a fixed 5-V output 1 | |
| • | Changed the EN absolute maximum voltage from (VVIN + 0.3 V) to 68 V 4 | |
| • | Deleted note 5 under the Absolute Maximum Ratings table 4 | |
| • | Changed the EN max operating voltage from VVIN to 65 V 4 | |
| • | Removed note 2 under the Recommended Operating Conditions 4 | |
| • | Changed the IFB maximum from: 100 nA to: 25 nA 5 | |
| • | Added Figure 13 and Figure 14 8 | |
| • | Modified the Functional Block Diagram graphic 14 | |
| • | Changed RDSON1 to RDSON2 in Equation 3 17 | |
| • | Updated Equation 12 19 | |
| • | Added a link to TI Design TIDA-01395 to the Typical Applications section 26 | |
| • | Changed Design 3 to a 3.3-V fixed output, LM5166Y 35 | |
| • | Added a new part number to CIN ref description 35 | |
| • | Added a new part number to LF ref description 38 | |
| • | Added the Design 5: 12-V, 300-mA COT Converter Operating from 24-V or 48-V Input section to Typical Applications 41 | |
| • | Changed the PCB Layout and PCB Layout Guidelines section names to Layout and Layout Guidelines 44 | |
| • | Added content to the Documentation Support section 47 |
• Changed data sheet status from product preview to production data.................................................................................... 1
5 Pin Configuration and Functions
LM5166X and LM5166Y Fixed Output DRC Package 10-Pin VSON Top View
LM5166 Adjustable Output DRC Package 10-Pin VSON Top View
Pin Functions
| PIN | I/O (1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | 1,0 | DESCRIPTION |
| 1 | SW | P | Switching node that is internally connected to the drain of the PFET buck switch (high side) and the drain of the NFET synchronous rectifier (low side). Connect to the buck inductor. |
| 2 | VIN | P | Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input supply and input filter capacitor CIN . The path from the VIN pin to the input capacitor must be as short as possible. |
| 3 | ILIM | I | Programming pin for current limit. Connecting the appropriate resistance from the ILIM pin to GND selects one of the three current limit options. The available current limit options are detailed in Table 3. |
| 4 | SS | I | Programming pin for the soft-start delay. If a 100-k Ω resistor is connected from the SS pin to GND, the internal soft-start circuit is disabled and the FB comparator reference steps immediately from zero to full value when the regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start circuit ramps the FB reference from zero to full value in 900 μ s. If a capacitor is connected from the SS pin to GND, the soft-start time can be set longer than 900 μ s. |
| 5 | RT | - | Mode select and on-time programming pin for Constant On-Time control. Connect a resistor from the RT pin to GND to program the on-time and hence switching frequency. Short RT to GND to select PFM (pulse frequency modulation) operation. |
| 6 | PGOOD | 0 | Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when either FB or VOUT is not in regulation. Use a 10-kΩ to 100-kΩ pullup resistor to system voltage rail or VOUT (no higher than 12 V). |
| 7 | EN | I | Input pin of the precision enable / UVLO comparator. The regulator is enabled when the EN pin voltage is greater than 1.22 V. |
| 8 | 8 VOUT or FB I | Feedback input to the voltage regulation loop for the LM5166 Adjustable Output version, or a VOUT pin connects the internal feedback resistor divider to the regulator output voltage for the fixed 3.3-V or 5-V options. The FB pin connects the internal feedback comparator to an external resistor divider for the adjustable voltage option, and the reference for the FB pin comparator is 1.223 V. | |
| 9 | HYS | 0 | Drain of internal NFET that is turned off when the EN input is greater than the EN pin threshold. External resistors from HYS to EN and GND program the input UVLO threshold and hysteresis. |
| 10 | GND | G | Regulator ground return. |
| - | PAD | P | Connect to GND pin and system ground on PCB. Path to C IN must be as short as possible. |
(1) P = Power, G = Ground, I = Input, O = Output.
Copyright © 2016–2017, Texas Instruments Incorporated
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).(1)(2)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN, EN to GND | –0.3 | 68 V VVIN + 0.3 V –3 16 V | ||
| SW to GND | –0.7 | |||
| 20-ns transient | ||||
| PGOOD, VOUT(3) to GND | –0.3 | |||
| HYS to GND | –0.3 | 7 | V | |
| ILIM, SS, RT, FB(4) to GND | –0.3 | 3.6 | V | |
| Maximum junction temperature, TJ | –40 | 150 | °C | |
| Storage temperature, Tstg | –55 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | |||
| V(ESD) | Electrostatic discharge | Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | V |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).(1)
| MIN | NOM MAX | UNIT | ||
|---|---|---|---|---|
| VIN | 3 | 65 | ||
| EN | –0.3 | 65 | ||
| Input voltages | PGOOD | –0.3 | 12 | V |
| HYS | –0.3 | 5.5 | ||
| Output current | IOUT | 0 | 500 | mA |
| Temperature | Operating junction temperature | –40 | 150 | °C |
(1) Operating Ratings are conditions under which the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics.
6.4 Thermal Information
| LM5166 | ||
|---|---|---|
| THERMAL METRIC(1) | DRC (VSON) | |
| 10 PINS | ||
| RθJA | Junction-to-ambient thermal resistance | 49.1 |
| RθJC(top) | Junction-to-case (top) thermal resistance | 57.2 |
| RθJB | Junction-to-board thermal resistance | 26.6 |
| ψJT | Junction-to-top characterization parameter | 0.8 |
| ψJB | Junction-to-board characterization parameter | 23.8 |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.8 |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Product Folder Links: LM5166
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) Fixed output setting.
(4) Adjustable output setting.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.5 Electrical Characteristics
Typical values correspond to TJ = 25 °C. Minimum and maximum limits are based on TJ = -40 °C to +125 °C. VIN = 12 V (unless otherwise noted). (1)(2)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| IQ-SD | VIN DC supply current, shutdown | V EN = 0 V, T J = 25°C | 4 | 6 | μΑ | |
| I Q-SLEEP | VIN DC supply current, no load | V FB = 1.5 V, T J = 25°C | 9.7 | 15 | μΑ | |
| I Q-SLEEP- VINMAX | VIN DC supply current, no load | V FB = 1.5 V, V VIN = 65 V, T J = 25°C | 10 | 15 | μΑ | |
| I Q-ACTIVE-PFM | VIN DC supply current, active | PFM mode, RRT = 0 Ω , RSS = 100 kΩ | 205 | μΑ | ||
| I Q-ACTIVE-COT | VIN DC supply current, active | COT mode, RRT = RSS = 100 kΩ | 320 | μA | ||
| POWER SWIT | CHES | |||||
| R DSON1 | High-side MOSFET R DS(on) | ISW = -100 mA | 0.93 | Ω | ||
| R DSON2 | Low-side MOSFET R DS(on) | I SW = 100 mA | 0.48 | Ω | ||
| CURRENT LIN | IITING | |||||
| I HS_LIM1 | 1125 | 1250 | 1375 | |||
| I HS_LIM2 | High-side peak current limit threshold | See Table 3 | 675 | 750 | 825 | mA |
| I HS_LIM3 | - unconoid | 440 | 500 | 560 | ||
| I LS_LIM1 | Low-side valley current limit | One Table 0 | 415 | A | ||
| I LS_LIM2 | threshold | See Table 3 | 315 | mA | ||
| COMPARATOR | ||||||
| V VOUT5 | VOUT 5-V DC setpoint | LM5166X | 4.9 | 5.0 | 5.1 | V |
| V VOUT3.3 | VOUT 3.3-V DC setpoint | LM5166Y | 3.23 | 3.3 | 3.37 | V |
| V VOUT = 5 V, LM5166X | 7 | |||||
| I VOUT | VOUT pin input current | V VOUT = 3.3 V, LM5166Y | 3.8 | μA | ||
| V FB1 | Lower FB regulation threshold (PFM and COT) | Adjustable VOUT version | 1.208 | 1.223 | 1.238 | V |
| VFB2 | Upper FB regulation threshold (PFM) | Adjustable VOOT Version | 1.218 | 1.233 | 1.248 | V |
| I FB | FB pin input bias current | V FB = 1 V | 25 | nA | ||
| FB HYS-PFM | FB comparator PFM hysteresis | PFM mode | 10 | mV | ||
| FB HYS-COT | FB comparator dropout hysteresis | COT mode | 4 | mV | ||
| FB LINE-REG | FB threshold variation over line | V VIN = 3 V to 65 V | 0.005 | %/V | ||
| VOUT LINE-REG | VOUT threshold variation over line | LM5166X, V VIN = 6 V to 65 V LM5166Y, V VIN = 4.5 V to 65 V | 0.005 | %/V | ||
| POWER GOOD | ||||||
| UVT RISING | DCCCD | V FB rising relative to V FB1 threshold | 94% | |||
| UVT FALLING | PGOOD comparator | V FB falling relative to V FB1 threshold | 87% | |||
| R PGOOD | PGOOD on-resistance | V FB = 1 V | 80 | 200 | Ω | |
| V INMIN-PGOOD | Minimum required VIN for valid PGOOD | V VIN falling I PGOOD = 0.1 mA, V PGOOD < 0.5 V | 1.2 | 1.65 | V | |
| I PGOOD | PGOOD off-state leakage | V FB = 1.2 V, V PGOOD = 5.5 V | 10 | 100 | nA | |
| ENABLE / UVL | _0 | |||||
| V IN-ON | Turnon threshold | V VIN rising | 2.60 | 2.75 | 2.95 | V |
| V IN-OFF | Turnoff threshold | V VIN falling | 2.35 | 2.45 | 2.60 | V |
| V EN-ON | EN turnon threshold | V EN rising | 1.163 | 1.22 | 1.276 | V |
| V EN-OFF | EN turnoff threshold | V EN falling | 1.109 | 1.144 | 1.178 | V |
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Copyright © 2016-2017, Texas Instruments Incorporated Product Folder Links: LM5166
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD bullet θJA) where θJA (in °C/W) is the package thermal impedance provided in Thermal Information.
Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits are based on TJ = –40°C to +125°C. VIN = 12 V (unless otherwise noted).(1)(2)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VEN-HYS | EN hysteresis | 76 | mV | |||
| VEN-SD | EN shutdown threshold | VEN falling | 0.3 | 0.6 | V | |
| RHYS | HYS on-resistance | VEN = 1 V | 80 | 200 | Ω | |
| IHYS | HYS off-state leakage | VEN = 1.5 V, VHYS = 5.5 V | 10 | 100 | nA | |
| SOFT-START | ||||||
| ISS | Soft-start charging current | VSS = 1 V | 10 | μA | ||
| TSS-INT | Soft-start rise time | SS floating | 900 | μs | ||
| THERMAL SHUTDOWN | ||||||
| TJ-SD | Thermal shutdown threshold | 170 | °C | |||
| TJ-SD-HYS | Thermal shutdown hysteresis | 10 | °C |
6.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| TON-MIN | Minimum on-time | 180 | ns | |||
| TON1 | On-time | 16 kΩ from RT to GND | 280 | ns | ||
| TON2 | On-time | 75 kΩ from RT to GND | 1150 | ns |
Product Folder Links: LM5166
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6.7 Typical Characteristics
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Unless otherwise specified, VIN = 12 V , VOUT = 5 V . Please refer to Typical Applications for circuit designs.
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Copyright © 2016–2017, Texas Instruments Incorporated
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
7 Detailed Description
7.1 Overview
The LM5166 regulator is an easy-to-use synchronous buck DC-DC converter that operates from a supply voltage ranging from 3 V to 65 V. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 48-V unregulated, semi-regulated, and fully-regulated supply rails. With integrated high-side and low-side power MOSFETs, the LM5166 delivers up to 500-mA DC load current with exceptional efficiency and ultra-low input quiescent current in a very small solution size. Designed for simple implementation, a choice of operating modes offers flexibility to optimize its usage according to the target application. Fixed-frequency, constant on-time (COT) operation with discontinuous conduction mode (DCM) at light loads is ideal for low-noise, high current, fast transient load requirements. Alternatively, pulse frequency modulation (PFM) mode, complemented by an adjustable current limit, achieves ultra-high light-load efficiency performance. Control loop compensation is not required with either operating mode, which reduces design time and external component count.
The LM5166 incorporates other features for comprehensive system requirements, including an open-drain Power Good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable soft start, monotonic start-up into prebiased loads, precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO), and thermal shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for simple and optimized PCB Layout, requiring only a few external components.
7.2 Functional Block Diagram
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Integrated Power MOSFETs
The LM5166 is a step-down buck converter with integrated high-side PMOS buck switch and low-side NMOS synchronous switch. During the high-side MOSFET on-time, the SW voltage VSW swings up to approximately VIN , and the inductor current increases with slope (VIN-VOUT)/LF . When the high-side MOSFET is turned off by the control logic, the low-side MOSFET turns on after a fixed dead time. Inductor current flows through the low-side MOSFET with slope -VOUT/LF . Duty cycle D is defined as TON/TSW , where TON is the high-side MOSFET conduction time and TSW is the switching period.
7.3.2 Selectable PFM or COT Mode Converter Operation
Depending on how the RT pin is connected, the LM5166 operates in PFM or COT mode. With the RT pin tied to GND, the device operates in PFM mode. An RRT resistor connected between the RT and GND pins enables COT control and sets the desired switching frequency as defined by Equation 4. Figure 39 and Figure 40 show converter schematics for PFM and COT modes of operation.
Figure 39. PFM Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable Output Voltage With Programmable Soft Start, Current Limit, and UVLO
Figure 40. COT Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable Output Voltage With Programmable Soft Start, Current Limit, and UVLO
Copyright © 2016–2017, Texas Instruments Incorporated
Feature Description (continued)
7.3.2.1 PFM Mode Operation
In PFM mode, the LM5166 behaves as a hysteretic voltage regulator operating in boundary conduction mode. The output voltage is regulated between upper and lower threshold levels according to the PFM feedback comparator hysteresis of 10 mV. Figure 41 shows the relevant output voltage and inductor current waveforms. The LM5166 provides the required switching pulses to recharge the output capacitor to the upper threshold, followed by a sleep period where most of the internal circuits are disabled. The load current is supported by the output capacitor during this time, and the LM5166 current consumption reduces to 9.7 μ A. The sleep period duration depends on load current and output capacitance.
Figure 41. PFM Mode Output Voltage and Inductor Current Representative Waveforms
When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM pulse frequency as
$FSW(PFM) = frac{VOUT}{LF · IPK(PFM)} · ≤ft(1 - frac{VOUT}{VIN}right)where
IPK(PFM) is one of the programmable levels for peak current limit. See Adjustable Current Limit for more detail.
One of the supported ILIM settings enables a function that modulates the peak current threshold levels during the first three switching cycles of each active period as illustrated in Figure 42. This function improves efficiency under most application conditions at the expense of slightly degraded load transient response.

Feature Description (continued)

Figure 42. PFM Mode With Modulated ILIM, Output Voltage and Inductor Current Representative Waveforms
As expected, the choice of mode and switching frequency represents a compromise between conversion efficiency, quiescent current, and passive component size. Lower switching frequency implies reduced switching losses (including gate charge losses, transition losses, and so forth) and higher overall efficiency. Higher switching frequency, on the other hand, implies smaller LC output filter and hence, a more compact design. Lower inductance also helps transient response and reduces the inductor DCR conduction loss. The ideal switching frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates at lower input quiescent current levels.
7.3.2.2 COT Mode Operation
In COT mode, the LM5166-based converter turns on the high-side MOSFET with constant on-time that adapts to VIN, as defined by Equation 2, to operate with nearly fixed switching frequency when in continuous conduction mode (CCM). The high-side MOSFET turns on when the feedback voltage (VFB) falls below the reference voltage. The regulator control loop maintains a constant output voltage by adjusting the PWM off-time as defined with Equation 3. For stable operation, the feedback voltage must decrease monotonically in phase with the inductor current during the off-time as explained in Ripple Generation Methods.
tON[ns] = frac{175 · RRT[kΩ]}{VIN}$ (2)
$tOFF = frac{LF · Δ IL(nom)}{VOUT + (RDCR + RDSON2) · IOUT}(3
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains high efficiency at light load currents by decreasing the effective switching frequency. The COT-controlled LM5166 waveforms in CCM and DEM are shown in Figure 43.
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Pin Configuration
LM5166X and LM5166Y Fixed Output DRC Package 10-Pin VSON Top View
LM5166 Adjustable Output DRC Package 10-Pin VSON Top View
Pin Functions
| PIN | I/O (1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | 1,0 | DESCRIPTION |
| 1 | SW | P | Switching node that is internally connected to the drain of the PFET buck switch (high side) and the drain of the NFET synchronous rectifier (low side). Connect to the buck inductor. |
| 2 | VIN | P | Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input supply and input filter capacitor CIN . The path from the VIN pin to the input capacitor must be as short as possible. |
| 3 | ILIM | I | Programming pin for current limit. Connecting the appropriate resistance from the ILIM pin to GND selects one of the three current limit options. The available current limit options are detailed in Table 3. |
| 4 | SS | I | Programming pin for the soft-start delay. If a 100-k Ω resistor is connected from the SS pin to GND, the internal soft-start circuit is disabled and the FB comparator reference steps immediately from zero to full value when the regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start circuit ramps the FB reference from zero to full value in 900 μ s. If a capacitor is connected from the SS pin to GND, the soft-start time can be set longer than 900 μ s. |
| 5 | RT | - | Mode select and on-time programming pin for Constant On-Time control. Connect a resistor from the RT pin to GND to program the on-time and hence switching frequency. Short RT to GND to select PFM (pulse frequency modulation) operation. |
| 6 | PGOOD | 0 | Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when either FB or VOUT is not in regulation. Use a 10-kΩ to 100-kΩ pullup resistor to system voltage rail or VOUT (no higher than 12 V). |
| 7 | EN | I | Input pin of the precision enable / UVLO comparator. The regulator is enabled when the EN pin voltage is greater than 1.22 V. |
| 8 | 8 VOUT or FB I | Feedback input to the voltage regulation loop for the LM5166 Adjustable Output version, or a VOUT pin connects the internal feedback resistor divider to the regulator output voltage for the fixed 3.3-V or 5-V options. The FB pin connects the internal feedback comparator to an external resistor divider for the adjustable voltage option, and the reference for the FB pin comparator is 1.223 V. | |
| 9 | HYS | 0 | Drain of internal NFET that is turned off when the EN input is greater than the EN pin threshold. External resistors from HYS to EN and GND program the input UVLO threshold and hysteresis. |
| 10 | GND | G | Regulator ground return. |
| - | PAD | P | Connect to GND pin and system ground on PCB. Path to C IN must be as short as possible. |
(1) P = Power, G = Ground, I = Input, O = Output.
Copyright © 2016–2017, Texas Instruments Incorporated
Electrical Characteristics
Typical values correspond to TJ = 25 °C. Minimum and maximum limits are based on TJ = -40 °C to +125 °C. VIN = 12 V (unless otherwise noted). (1)(2)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| IQ-SD | VIN DC supply current, shutdown | V EN = 0 V, T J = 25°C | 4 | 6 | μΑ | |
| I Q-SLEEP | VIN DC supply current, no load | V FB = 1.5 V, T J = 25°C | 9.7 | 15 | μΑ | |
| I Q-SLEEP- VINMAX | VIN DC supply current, no load | V FB = 1.5 V, V VIN = 65 V, T J = 25°C | 10 | 15 | μΑ | |
| I Q-ACTIVE-PFM | VIN DC supply current, active | PFM mode, RRT = 0 Ω , RSS = 100 kΩ | 205 | μΑ | ||
| I Q-ACTIVE-COT | VIN DC supply current, active | COT mode, RRT = RSS = 100 kΩ | 320 | μA | ||
| POWER SWIT | CHES | |||||
| R DSON1 | High-side MOSFET R DS(on) | ISW = -100 mA | 0.93 | Ω | ||
| R DSON2 | Low-side MOSFET R DS(on) | I SW = 100 mA | 0.48 | Ω | ||
| CURRENT LIN | IITING | |||||
| I HS_LIM1 | 1125 | 1250 | 1375 | |||
| I HS_LIM2 | High-side peak current limit threshold | See Table 3 | 675 | 750 | 825 | mA |
| I HS_LIM3 | - unconoid | 440 | 500 | 560 | ||
| I LS_LIM1 | Low-side valley current limit | One Table 0 | 415 | A | ||
| I LS_LIM2 | threshold | See Table 3 | 315 | mA | ||
| COMPARATOR | ||||||
| V VOUT5 | VOUT 5-V DC setpoint | LM5166X | 4.9 | 5.0 | 5.1 | V |
| V VOUT3.3 | VOUT 3.3-V DC setpoint | LM5166Y | 3.23 | 3.3 | 3.37 | V |
| V VOUT = 5 V, LM5166X | 7 | |||||
| I VOUT | VOUT pin input current | V VOUT = 3.3 V, LM5166Y | 3.8 | μA | ||
| V FB1 | Lower FB regulation threshold (PFM and COT) | Adjustable VOUT version | 1.208 | 1.223 | 1.238 | V |
| VFB2 | Upper FB regulation threshold (PFM) | Adjustable VOOT Version | 1.218 | 1.233 | 1.248 | V |
| I FB | FB pin input bias current | V FB = 1 V | 25 | nA | ||
| FB HYS-PFM | FB comparator PFM hysteresis | PFM mode | 10 | mV | ||
| FB HYS-COT | FB comparator dropout hysteresis | COT mode | 4 | mV | ||
| FB LINE-REG | FB threshold variation over line | V VIN = 3 V to 65 V | 0.005 | %/V | ||
| VOUT LINE-REG | VOUT threshold variation over line | LM5166X, V VIN = 6 V to 65 V LM5166Y, V VIN = 4.5 V to 65 V | 0.005 | %/V | ||
| POWER GOOD | ||||||
| UVT RISING | DCCCD | V FB rising relative to V FB1 threshold | 94% | |||
| UVT FALLING | PGOOD comparator | V FB falling relative to V FB1 threshold | 87% | |||
| R PGOOD | PGOOD on-resistance | V FB = 1 V | 80 | 200 | Ω | |
| V INMIN-PGOOD | Minimum required VIN for valid PGOOD | V VIN falling I PGOOD = 0.1 mA, V PGOOD < 0.5 V | 1.2 | 1.65 | V | |
| I PGOOD | PGOOD off-state leakage | V FB = 1.2 V, V PGOOD = 5.5 V | 10 | 100 | nA | |
| ENABLE / UVL | _0 | |||||
| V IN-ON | Turnon threshold | V VIN rising | 2.60 | 2.75 | 2.95 | V |
| V IN-OFF | Turnoff threshold | V VIN falling | 2.35 | 2.45 | 2.60 | V |
| V EN-ON | EN turnon threshold | V EN rising | 1.163 | 1.22 | 1.276 | V |
| V EN-OFF | EN turnoff threshold | V EN falling | 1.109 | 1.144 | 1.178 | V |
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Copyright © 2016-2017, Texas Instruments Incorporated Product Folder Links: LM5166
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD bullet θJA) where θJA (in °C/W) is the package thermal impedance provided in Thermal Information.
Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).(1)(2)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN, EN to GND | –0.3 | 68 V VVIN + 0.3 V –3 16 V | ||
| SW to GND | –0.7 | |||
| 20-ns transient | ||||
| PGOOD, VOUT(3) to GND | –0.3 | |||
| HYS to GND | –0.3 | 7 | V | |
| ILIM, SS, RT, FB(4) to GND | –0.3 | 3.6 | V | |
| Maximum junction temperature, TJ | –40 | 150 | °C | |
| Storage temperature, Tstg | –55 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).(1)
| MIN | NOM MAX | UNIT | ||
|---|---|---|---|---|
| VIN | 3 | 65 | ||
| EN | –0.3 | 65 | ||
| Input voltages | PGOOD | –0.3 | 12 | V |
| HYS | –0.3 | 5.5 | ||
| Output current | IOUT | 0 | 500 | mA |
| Temperature | Operating junction temperature | –40 | 150 | °C |
(1) Operating Ratings are conditions under which the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics.
Thermal Information
| LM5166 | ||
|---|---|---|
| THERMAL METRIC(1) | DRC (VSON) | |
| 10 PINS | ||
| RθJA | Junction-to-ambient thermal resistance | 49.1 |
| RθJC(top) | Junction-to-case (top) thermal resistance | 57.2 |
| RθJB | Junction-to-board thermal resistance | 26.6 |
| ψJT | Junction-to-top characterization parameter | 0.8 |
| ψJB | Junction-to-board characterization parameter | 23.8 |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.8 |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Product Folder Links: LM5166
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) Fixed output setting.
(4) Adjustable output setting.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.5 Electrical Characteristics
Typical values correspond to TJ = 25 °C. Minimum and maximum limits are based on TJ = -40 °C to +125 °C. VIN = 12 V (unless otherwise noted). (1)(2)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| IQ-SD | VIN DC supply current, shutdown | V EN = 0 V, T J = 25°C | 4 | 6 | μΑ | |
| I Q-SLEEP | VIN DC supply current, no load | V FB = 1.5 V, T J = 25°C | 9.7 | 15 | μΑ | |
| I Q-SLEEP- VINMAX | VIN DC supply current, no load | V FB = 1.5 V, V VIN = 65 V, T J = 25°C | 10 | 15 | μΑ | |
| I Q-ACTIVE-PFM | VIN DC supply current, active | PFM mode, RRT = 0 Ω , RSS = 100 kΩ | 205 | μΑ | ||
| I Q-ACTIVE-COT | VIN DC supply current, active | COT mode, RRT = RSS = 100 kΩ | 320 | μA | ||
| POWER SWIT | CHES | |||||
| R DSON1 | High-side MOSFET R DS(on) | ISW = -100 mA | 0.93 | Ω | ||
| R DSON2 | Low-side MOSFET R DS(on) | I SW = 100 mA | 0.48 | Ω | ||
| CURRENT LIN | IITING | |||||
| I HS_LIM1 | 1125 | 1250 | 1375 | |||
| I HS_LIM2 | High-side peak current limit threshold | See Table 3 | 675 | 750 | 825 | mA |
| I HS_LIM3 | - unconoid | 440 | 500 | 560 | ||
| I LS_LIM1 | Low-side valley current limit | One Table 0 | 415 | A | ||
| I LS_LIM2 | threshold | See Table 3 | 315 | mA | ||
| COMPARATOR | ||||||
| V VOUT5 | VOUT 5-V DC setpoint | LM5166X | 4.9 | 5.0 | 5.1 | V |
| V VOUT3.3 | VOUT 3.3-V DC setpoint | LM5166Y | 3.23 | 3.3 | 3.37 | V |
| V VOUT = 5 V, LM5166X | 7 | |||||
| I VOUT | VOUT pin input current | V VOUT = 3.3 V, LM5166Y | 3.8 | μA | ||
| V FB1 | Lower FB regulation threshold (PFM and COT) | Adjustable VOUT version | 1.208 | 1.223 | 1.238 | V |
| VFB2 | Upper FB regulation threshold (PFM) | Adjustable VOOT Version | 1.218 | 1.233 | 1.248 | V |
| I FB | FB pin input bias current | V FB = 1 V | 25 | nA | ||
| FB HYS-PFM | FB comparator PFM hysteresis | PFM mode | 10 | mV | ||
| FB HYS-COT | FB comparator dropout hysteresis | COT mode | 4 | mV | ||
| FB LINE-REG | FB threshold variation over line | V VIN = 3 V to 65 V | 0.005 | %/V | ||
| VOUT LINE-REG | VOUT threshold variation over line | LM5166X, V VIN = 6 V to 65 V LM5166Y, V VIN = 4.5 V to 65 V | 0.005 | %/V | ||
| POWER GOOD | ||||||
| UVT RISING | DCCCD | V FB rising relative to V FB1 threshold | 94% | |||
| UVT FALLING | PGOOD comparator | V FB falling relative to V FB1 threshold | 87% | |||
| R PGOOD | PGOOD on-resistance | V FB = 1 V | 80 | 200 | Ω | |
| V INMIN-PGOOD | Minimum required VIN for valid PGOOD | V VIN falling I PGOOD = 0.1 mA, V PGOOD < 0.5 V | 1.2 | 1.65 | V | |
| I PGOOD | PGOOD off-state leakage | V FB = 1.2 V, V PGOOD = 5.5 V | 10 | 100 | nA | |
| ENABLE / UVL | _0 | |||||
| V IN-ON | Turnon threshold | V VIN rising | 2.60 | 2.75 | 2.95 | V |
| V IN-OFF | Turnoff threshold | V VIN falling | 2.35 | 2.45 | 2.60 | V |
| V EN-ON | EN turnon threshold | V EN rising | 1.163 | 1.22 | 1.276 | V |
| V EN-OFF | EN turnoff threshold | V EN falling | 1.109 | 1.144 | 1.178 | V |
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Copyright © 2016-2017, Texas Instruments Incorporated Product Folder Links: LM5166
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD bullet θJA) where θJA (in °C/W) is the package thermal impedance provided in Thermal Information.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| LM5166 | Texas Instruments | — |
| LM5166-BASED | Texas Instruments | — |
| LM5166DRCR | Texas Instruments | — |
| LM5166DRCR.A | Texas Instruments | — |
| LM5166DRCT | Texas Instruments | — |
| LM5166EVM-C33A | Texas Instruments | — |
| LM5166EVM-C50A | Texas Instruments | — |
| LM5166X | Texas Instruments | — |
| LM5166XDRCR | Texas Instruments | — |
| LM5166XDRCR.A | Texas Instruments | — |
| LM5166XDRCT | Texas Instruments | — |
| LM5166XDRCT.A | Texas Instruments | — |
| LM5166Y | Texas Instruments | — |
| LM5166YDRCR | Texas Instruments | — |
| LM5166YDRCR.A | Texas Instruments | — |
| LM5166YDRCT | Texas Instruments | — |
| LM5166YDRCT.A | Texas Instruments | — |
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